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IR: Handle 256-bit VBSL

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Extends VBSL to handle 256-bit vectors.
This commit is contained in:
lioncash committed 2022-10-03 18:06:27 +00:00
1 parent 8d8b029285
commit ecba1b6838
3 files changed
+43 -21
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External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
Vendored
+8 -7
View File
@@ -951,15 +951,16 @@ DEF_OP(VUnZip) {
DEF_OP(VBSL) {
auto Op = IROp->C<IR::IROp_VBSL>();
const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorMask);
const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorTrue);
const auto Src3 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorFalse);
const auto Src1 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorMask);
const auto Src2 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorTrue);
const auto Src3 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorFalse);
__uint128_t Tmp{};
Tmp = Src2 & Src1;
Tmp |= Src3 & ~Src1;
const auto Tmp = InterpVector256{
.Lower = (Src2.Lower & Src1.Lower) | (Src3.Lower & ~Src1.Lower),
.Upper = (Src2.Upper & Src1.Upper) | (Src3.Upper & ~Src1.Upper),
};
memcpy(GDP, &Tmp, 16);
memcpy(GDP, &Tmp, sizeof(Tmp));
}
DEF_OP(VCMPEQ) {
External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
Vendored
+25 -10
View File
@@ -2263,16 +2263,31 @@ DEF_OP(VUnZip2) {
}
DEF_OP(VBSL) {
auto Op = IROp->C<IR::IROp_VBSL>();
if (IROp->Size == 16) {
mov(VTMP1.V16B(), GetSrc(Op->VectorMask.ID()).V16B());
bsl(VTMP1.V16B(), GetSrc(Op->VectorTrue.ID()).V16B(), GetSrc(Op->VectorFalse.ID()).V16B());
mov(GetDst(Node).V16B(), VTMP1.V16B());
}
else {
mov(VTMP1.V8B(), GetSrc(Op->VectorMask.ID()).V8B());
bsl(VTMP1.V8B(), GetSrc(Op->VectorTrue.ID()).V8B(), GetSrc(Op->VectorFalse.ID()).V8B());
mov(GetDst(Node).V8B(), VTMP1.V8B());
const auto Op = IROp->C<IR::IROp_VBSL>();
const auto OpSize = IROp->Size;
const auto Dst = GetDst(Node);
const auto VectorFalse = GetSrc(Op->VectorFalse.ID());
const auto VectorTrue = GetSrc(Op->VectorTrue.ID());
const auto VectorMask = GetSrc(Op->VectorMask.ID());
if (HostSupportsSVE) {
// NOTE: Slight parameter difference from ASIMD
// ASIMD -> BSL Mask, True, False
// SVE -> BSL True, True, False, Mask
mov(VTMP1.Z().VnD(), VectorTrue.Z().VnD());
bsl(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VectorFalse.Z().VnD(), VectorMask.Z().VnD());
mov(Dst.Z().VnD(), VTMP1.Z().VnD());
} else {
if (OpSize == 8) {
mov(VTMP1.V8B(), VectorMask.V8B());
bsl(VTMP1.V8B(), VectorTrue.V8B(), VectorFalse.V8B());
mov(Dst.V8B(), VTMP1.V8B());
} else {
mov(VTMP1.V16B(), VectorMask.V16B());
bsl(VTMP1.V16B(), VectorTrue.V16B(), VectorFalse.V16B());
mov(Dst.V16B(), VTMP1.V16B());
}
}
}
External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
Vendored
+10 -4
View File
@@ -1410,10 +1410,16 @@ DEF_OP(VUnZip2) {
DEF_OP(VBSL) {
auto Op = IROp->C<IR::IROp_VBSL>();
vpand(xmm0, GetSrc(Op->VectorMask.ID()), GetSrc(Op->VectorTrue.ID()));
vpandn(xmm12, GetSrc(Op->VectorMask.ID()), GetSrc(Op->VectorFalse.ID()));
vpor(GetDst(Node), xmm0, xmm12);
const auto Op = IROp->C<IR::IROp_VBSL>();
const auto Dst = ToYMM(GetDst(Node));
const auto VectorFalse = ToYMM(GetSrc(Op->VectorFalse.ID()));
const auto VectorTrue = ToYMM(GetSrc(Op->VectorTrue.ID()));
const auto VectorMask = ToYMM(GetSrc(Op->VectorMask.ID()));
vpand(ymm0, VectorMask, VectorTrue);
vpandn(ymm12, VectorMask, VectorFalse);
vpor(Dst, ymm0, ymm12);
}
DEF_OP(VCMPEQ) {