diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
index 57a915eb3..03fe9dba2 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
@@ -951,15 +951,16 @@ DEF_OP(VUnZip) {
 
 DEF_OP(VBSL) {
   auto Op = IROp->C<IR::IROp_VBSL>();
-  const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorMask);
-  const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorTrue);
-  const auto Src3 = *GetSrc<__uint128_t*>(Data->SSAData, Op->VectorFalse);
+  const auto Src1 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorMask);
+  const auto Src2 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorTrue);
+  const auto Src3 = *GetSrc<InterpVector256*>(Data->SSAData, Op->VectorFalse);
 
-  __uint128_t Tmp{};
-  Tmp = Src2 & Src1;
-  Tmp |= Src3 & ~Src1;
+  const auto Tmp = InterpVector256{
+    .Lower = (Src2.Lower & Src1.Lower) | (Src3.Lower & ~Src1.Lower),
+    .Upper = (Src2.Upper & Src1.Upper) | (Src3.Upper & ~Src1.Upper),
+  };
 
-  memcpy(GDP, &Tmp, 16);
+  memcpy(GDP, &Tmp, sizeof(Tmp));
 }
 
 DEF_OP(VCMPEQ) {
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
index 0a0866a93..a098bebee 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -2263,16 +2263,31 @@ DEF_OP(VUnZip2) {
 }
 
 DEF_OP(VBSL) {
-  auto Op = IROp->C<IR::IROp_VBSL>();
-  if (IROp->Size == 16) {
-    mov(VTMP1.V16B(), GetSrc(Op->VectorMask.ID()).V16B());
-    bsl(VTMP1.V16B(), GetSrc(Op->VectorTrue.ID()).V16B(), GetSrc(Op->VectorFalse.ID()).V16B());
-    mov(GetDst(Node).V16B(), VTMP1.V16B());
-  }
-  else {
-    mov(VTMP1.V8B(), GetSrc(Op->VectorMask.ID()).V8B());
-    bsl(VTMP1.V8B(), GetSrc(Op->VectorTrue.ID()).V8B(), GetSrc(Op->VectorFalse.ID()).V8B());
-    mov(GetDst(Node).V8B(), VTMP1.V8B());
+  const auto Op = IROp->C<IR::IROp_VBSL>();
+  const auto OpSize = IROp->Size;
+
+  const auto Dst = GetDst(Node);
+  const auto VectorFalse = GetSrc(Op->VectorFalse.ID());
+  const auto VectorTrue = GetSrc(Op->VectorTrue.ID());
+  const auto VectorMask = GetSrc(Op->VectorMask.ID());
+
+  if (HostSupportsSVE) {
+    // NOTE: Slight parameter difference from ASIMD
+    //       ASIMD -> BSL Mask, True, False
+    //       SVE   -> BSL True, True, False, Mask
+    mov(VTMP1.Z().VnD(), VectorTrue.Z().VnD());
+    bsl(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VectorFalse.Z().VnD(), VectorMask.Z().VnD());
+    mov(Dst.Z().VnD(), VTMP1.Z().VnD());
+  } else {
+    if (OpSize == 8) {
+      mov(VTMP1.V8B(), VectorMask.V8B());
+      bsl(VTMP1.V8B(), VectorTrue.V8B(), VectorFalse.V8B());
+      mov(Dst.V8B(), VTMP1.V8B());
+    } else {
+      mov(VTMP1.V16B(), VectorMask.V16B());
+      bsl(VTMP1.V16B(), VectorTrue.V16B(), VectorFalse.V16B());
+      mov(Dst.V16B(), VTMP1.V16B());
+    }
   }
 }
 
diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
index 58ce303ed..053d4bdea 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
@@ -1410,10 +1410,16 @@ DEF_OP(VUnZip2) {
 
 
 DEF_OP(VBSL) {
-  auto Op = IROp->C<IR::IROp_VBSL>();
-  vpand(xmm0, GetSrc(Op->VectorMask.ID()), GetSrc(Op->VectorTrue.ID()));
-  vpandn(xmm12, GetSrc(Op->VectorMask.ID()), GetSrc(Op->VectorFalse.ID()));
-  vpor(GetDst(Node), xmm0, xmm12);
+  const auto Op = IROp->C<IR::IROp_VBSL>();
+
+  const auto Dst = ToYMM(GetDst(Node));
+  const auto VectorFalse = ToYMM(GetSrc(Op->VectorFalse.ID()));
+  const auto VectorTrue = ToYMM(GetSrc(Op->VectorTrue.ID()));
+  const auto VectorMask = ToYMM(GetSrc(Op->VectorMask.ID()));
+
+  vpand(ymm0, VectorMask, VectorTrue);
+  vpandn(ymm12, VectorMask, VectorFalse);
+  vpor(Dst, ymm0, ymm12);
 }
 
 DEF_OP(VCMPEQ) {