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ARMEmitter: Handle SVE ANDV (predicated)

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Lioncache committed 2023-02-03 21:31:41 -05:00
1 parent 3508f7a667
commit db8317caf8
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External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
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@@ -782,6 +782,10 @@ public:
constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
SVEReductionOperation(Op, 0b01, size, vd, pg, zn);
}
void andv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
SVEReductionOperation(Op, 0b10, size, vd, pg, zn);
}
// SVE Bitwise Shift - Predicated
// SVE bitwise shift by immediate (predicated)