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https://github.com/FEX-Emu/FEX.git
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Merge pull request #4708 from Sonicadvance1/geekbench_microtest
unittests/instcountci: Adds a long-lived ymm_high test
This commit is contained in:
1 file changed
+162
@@ -1601,6 +1601,168 @@
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"str w20, [x9, #72]",
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"subs x26, x19, #0x0 (0)"
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]
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},
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"Long-lived ymm_high test": {
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"x86InstructionCount": 16,
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"ExpectedInstructionCount": 132,
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"Comment": [
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"Inspired from a Geekbench benchmark hammering this instruction",
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"Keeps a bunch of ymm_high values live that can get spilled in to spill-slots",
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"These can instead be spilled back in to the context without any stack usage",
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"Useful to ensure we aren't evicting cachelines unnnecessarily"
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],
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"x86Insts": [
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"vpmaddwd ymm0, ymm1, ymm15",
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"vpmaddwd ymm1, ymm2, ymm14",
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"vpmaddwd ymm2, ymm3, ymm13",
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"vpmaddwd ymm3, ymm4, ymm12",
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"vpmaddwd ymm4, ymm5, ymm11",
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"vpmaddwd ymm5, ymm6, ymm10",
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"vpmaddwd ymm6, ymm7, ymm9",
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"vpmaddwd ymm7, ymm8, ymm8",
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"vpmaddwd ymm8, ymm9, ymm7",
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"vpmaddwd ymm9, ymm10, ymm6",
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"vpmaddwd ymm10, ymm11, ymm5",
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"vpmaddwd ymm11, ymm12, ymm4",
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"vpmaddwd ymm12, ymm13, ymm3",
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"vpmaddwd ymm13, ymm14, ymm2",
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"vpmaddwd ymm14, ymm15, ymm1",
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"vpmaddwd ymm15, ymm0, ymm0"
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],
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"ExpectedArm64ASM": [
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"sub sp, sp, #0xa0 (160)",
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"ldr q2, [x28, #48]",
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"ldr q3, [x28, #272]",
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"smull v4.4s, v17.4h, v31.4h",
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"smull2 v5.4s, v17.8h, v31.8h",
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"addp v16.4s, v4.4s, v5.4s",
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"smull v4.4s, v2.4h, v3.4h",
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"smull2 v2.4s, v2.8h, v3.8h",
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"addp v2.4s, v4.4s, v2.4s",
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"ldr q4, [x28, #64]",
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"ldr q5, [x28, #256]",
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"smull v6.4s, v18.4h, v30.4h",
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"smull2 v7.4s, v18.8h, v30.8h",
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"addp v17.4s, v6.4s, v7.4s",
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"smull v6.4s, v4.4h, v5.4h",
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"smull2 v4.4s, v4.8h, v5.8h",
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"addp v4.4s, v6.4s, v4.4s",
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"ldr q6, [x28, #80]",
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"ldr q7, [x28, #240]",
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"smull v8.4s, v19.4h, v29.4h",
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"smull2 v9.4s, v19.8h, v29.8h",
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"addp v18.4s, v8.4s, v9.4s",
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"smull v8.4s, v6.4h, v7.4h",
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"smull2 v6.4s, v6.8h, v7.8h",
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"addp v6.4s, v8.4s, v6.4s",
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"ldr q8, [x28, #96]",
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"ldr q9, [x28, #224]",
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"smull v10.4s, v20.4h, v28.4h",
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"smull2 v11.4s, v20.8h, v28.8h",
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"addp v19.4s, v10.4s, v11.4s",
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"smull v10.4s, v8.4h, v9.4h",
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"smull2 v8.4s, v8.8h, v9.8h",
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"addp v8.4s, v10.4s, v8.4s",
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"ldr q10, [x28, #112]",
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"ldr q11, [x28, #208]",
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"smull v12.4s, v21.4h, v27.4h",
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"smull2 v13.4s, v21.8h, v27.8h",
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"addp v20.4s, v12.4s, v13.4s",
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"smull v12.4s, v10.4h, v11.4h",
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"smull2 v10.4s, v10.8h, v11.8h",
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"addp v10.4s, v12.4s, v10.4s",
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"ldr q12, [x28, #128]",
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"ldr q13, [x28, #192]",
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"smull v14.4s, v22.4h, v26.4h",
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"smull2 v15.4s, v22.8h, v26.8h",
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"addp v21.4s, v14.4s, v15.4s",
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"smull v14.4s, v12.4h, v13.4h",
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"smull2 v12.4s, v12.8h, v13.8h",
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"addp v12.4s, v14.4s, v12.4s",
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"ldr q14, [x28, #144]",
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"ldr q15, [x28, #176]",
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"str q2, [sp]",
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"smull v2.4s, v23.4h, v25.4h",
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"str q3, [sp, #32]",
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"smull2 v3.4s, v23.8h, v25.8h",
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"addp v22.4s, v2.4s, v3.4s",
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"smull v2.4s, v14.4h, v15.4h",
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"smull2 v3.4s, v14.8h, v15.8h",
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"addp v2.4s, v2.4s, v3.4s",
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"ldr q3, [x28, #160]",
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"smull v14.4s, v24.4h, v24.4h",
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"str q4, [sp, #64]",
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"smull2 v4.4s, v24.8h, v24.8h",
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"addp v23.4s, v14.4s, v4.4s",
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"smull v4.4s, v3.4h, v3.4h",
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"smull2 v3.4s, v3.8h, v3.8h",
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"addp v3.4s, v4.4s, v3.4s",
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"smull v4.4s, v25.4h, v23.4h",
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"smull2 v14.4s, v25.8h, v23.8h",
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"addp v24.4s, v4.4s, v14.4s",
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"smull v4.4s, v15.4h, v3.4h",
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"smull2 v14.4s, v15.8h, v3.8h",
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"addp v4.4s, v4.4s, v14.4s",
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"smull v14.4s, v26.4h, v22.4h",
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"smull2 v15.4s, v26.8h, v22.8h",
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"addp v25.4s, v14.4s, v15.4s",
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"smull v14.4s, v13.4h, v2.4h",
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"smull2 v13.4s, v13.8h, v2.8h",
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"addp v13.4s, v14.4s, v13.4s",
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"smull v14.4s, v27.4h, v21.4h",
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"smull2 v15.4s, v27.8h, v21.8h",
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"addp v26.4s, v14.4s, v15.4s",
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"smull v14.4s, v11.4h, v12.4h",
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"smull2 v11.4s, v11.8h, v12.8h",
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"addp v11.4s, v14.4s, v11.4s",
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"smull v14.4s, v28.4h, v20.4h",
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"smull2 v15.4s, v28.8h, v20.8h",
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"addp v27.4s, v14.4s, v15.4s",
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"smull v14.4s, v9.4h, v10.4h",
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"smull2 v9.4s, v9.8h, v10.8h",
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"addp v9.4s, v14.4s, v9.4s",
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"smull v14.4s, v29.4h, v19.4h",
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"smull2 v15.4s, v29.8h, v19.8h",
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"addp v28.4s, v14.4s, v15.4s",
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"smull v14.4s, v7.4h, v8.4h",
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"smull2 v7.4s, v7.8h, v8.8h",
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"addp v7.4s, v14.4s, v7.4s",
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"smull v14.4s, v30.4h, v18.4h",
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"smull2 v15.4s, v30.8h, v18.8h",
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"addp v29.4s, v14.4s, v15.4s",
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"smull v14.4s, v5.4h, v6.4h",
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"smull2 v5.4s, v5.8h, v6.8h",
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"addp v5.4s, v14.4s, v5.4s",
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"smull v14.4s, v31.4h, v17.4h",
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"smull2 v15.4s, v31.8h, v17.8h",
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"addp v30.4s, v14.4s, v15.4s",
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"ldr q14, [sp, #32]",
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"ldr q15, [sp, #64]",
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"str q6, [sp, #96]",
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"smull v6.4s, v14.4h, v15.4h",
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"smull2 v14.4s, v14.8h, v15.8h",
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"addp v6.4s, v6.4s, v14.4s",
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"smull v14.4s, v16.4h, v16.4h",
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"smull2 v15.4s, v16.8h, v16.8h",
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"addp v31.4s, v14.4s, v15.4s",
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"ldr q14, [sp]",
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"smull v15.4s, v14.4h, v14.4h",
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"str q8, [sp, #128]",
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"smull2 v8.4s, v14.8h, v14.8h",
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"addp v8.4s, v15.4s, v8.4s",
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"stp q6, q8, [x28, #256]",
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"stp q7, q5, [x28, #224]",
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"stp q11, q9, [x28, #192]",
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"stp q4, q13, [x28, #160]",
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"stp q2, q3, [x28, #128]",
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"stp q10, q12, [x28, #96]",
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"ldr q2, [sp, #96]",
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"ldr q3, [sp, #128]",
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"stp q2, q3, [x28, #64]",
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"ldr q2, [sp, #64]",
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"stp q14, q2, [x28, #32]",
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"add sp, sp, #0xa0 (160)"
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]
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}
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}
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}
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