diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 85eeb75d0..8bac6e7bb 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -1601,6 +1601,168 @@ "str w20, [x9, #72]", "subs x26, x19, #0x0 (0)" ] + }, + "Long-lived ymm_high test": { + "x86InstructionCount": 16, + "ExpectedInstructionCount": 132, + "Comment": [ + "Inspired from a Geekbench benchmark hammering this instruction", + "Keeps a bunch of ymm_high values live that can get spilled in to spill-slots", + "These can instead be spilled back in to the context without any stack usage", + "Useful to ensure we aren't evicting cachelines unnnecessarily" + ], + "x86Insts": [ + "vpmaddwd ymm0, ymm1, ymm15", + "vpmaddwd ymm1, ymm2, ymm14", + "vpmaddwd ymm2, ymm3, ymm13", + "vpmaddwd ymm3, ymm4, ymm12", + "vpmaddwd ymm4, ymm5, ymm11", + "vpmaddwd ymm5, ymm6, ymm10", + "vpmaddwd ymm6, ymm7, ymm9", + "vpmaddwd ymm7, ymm8, ymm8", + "vpmaddwd ymm8, ymm9, ymm7", + "vpmaddwd ymm9, ymm10, ymm6", + "vpmaddwd ymm10, ymm11, ymm5", + "vpmaddwd ymm11, ymm12, ymm4", + "vpmaddwd ymm12, ymm13, ymm3", + "vpmaddwd ymm13, ymm14, ymm2", + "vpmaddwd ymm14, ymm15, ymm1", + "vpmaddwd ymm15, ymm0, ymm0" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0xa0 (160)", + "ldr q2, [x28, #48]", + "ldr q3, [x28, #272]", + "smull v4.4s, v17.4h, v31.4h", + "smull2 v5.4s, v17.8h, v31.8h", + "addp v16.4s, v4.4s, v5.4s", + "smull v4.4s, v2.4h, v3.4h", + "smull2 v2.4s, v2.8h, v3.8h", + "addp v2.4s, v4.4s, v2.4s", + "ldr q4, [x28, #64]", + "ldr q5, [x28, #256]", + "smull v6.4s, v18.4h, v30.4h", + "smull2 v7.4s, v18.8h, v30.8h", + "addp v17.4s, v6.4s, v7.4s", + "smull v6.4s, v4.4h, v5.4h", + "smull2 v4.4s, v4.8h, v5.8h", + "addp v4.4s, v6.4s, v4.4s", + "ldr q6, [x28, #80]", + "ldr q7, [x28, #240]", + "smull v8.4s, v19.4h, v29.4h", + "smull2 v9.4s, v19.8h, v29.8h", + "addp v18.4s, v8.4s, v9.4s", + "smull v8.4s, v6.4h, v7.4h", + "smull2 v6.4s, v6.8h, v7.8h", + "addp v6.4s, v8.4s, v6.4s", + "ldr q8, [x28, #96]", + "ldr q9, [x28, #224]", + "smull v10.4s, v20.4h, v28.4h", + "smull2 v11.4s, v20.8h, v28.8h", + "addp v19.4s, v10.4s, v11.4s", + "smull v10.4s, v8.4h, v9.4h", + "smull2 v8.4s, v8.8h, v9.8h", + "addp v8.4s, v10.4s, v8.4s", + "ldr q10, [x28, #112]", + "ldr q11, [x28, #208]", + "smull v12.4s, v21.4h, v27.4h", + "smull2 v13.4s, v21.8h, v27.8h", + "addp v20.4s, v12.4s, v13.4s", + "smull v12.4s, v10.4h, v11.4h", + "smull2 v10.4s, v10.8h, v11.8h", + "addp v10.4s, v12.4s, v10.4s", + "ldr q12, [x28, #128]", + "ldr q13, [x28, #192]", + "smull v14.4s, v22.4h, v26.4h", + "smull2 v15.4s, v22.8h, v26.8h", + "addp v21.4s, v14.4s, v15.4s", + "smull v14.4s, v12.4h, v13.4h", + "smull2 v12.4s, v12.8h, v13.8h", + "addp v12.4s, v14.4s, v12.4s", + "ldr q14, [x28, #144]", + "ldr q15, [x28, #176]", + "str q2, [sp]", + "smull v2.4s, v23.4h, v25.4h", + "str q3, [sp, #32]", + "smull2 v3.4s, v23.8h, v25.8h", + "addp v22.4s, v2.4s, v3.4s", + "smull v2.4s, v14.4h, v15.4h", + "smull2 v3.4s, v14.8h, v15.8h", + "addp v2.4s, v2.4s, v3.4s", + "ldr q3, [x28, #160]", + "smull v14.4s, v24.4h, v24.4h", + "str q4, [sp, #64]", + "smull2 v4.4s, v24.8h, v24.8h", + "addp v23.4s, v14.4s, v4.4s", + "smull v4.4s, v3.4h, v3.4h", + "smull2 v3.4s, v3.8h, v3.8h", + "addp v3.4s, v4.4s, v3.4s", + "smull v4.4s, v25.4h, v23.4h", + "smull2 v14.4s, v25.8h, v23.8h", + "addp v24.4s, v4.4s, v14.4s", + "smull v4.4s, v15.4h, v3.4h", + "smull2 v14.4s, v15.8h, v3.8h", + "addp v4.4s, v4.4s, v14.4s", + "smull v14.4s, v26.4h, v22.4h", + "smull2 v15.4s, v26.8h, v22.8h", + "addp v25.4s, v14.4s, v15.4s", + "smull v14.4s, v13.4h, v2.4h", + "smull2 v13.4s, v13.8h, v2.8h", + "addp v13.4s, v14.4s, v13.4s", + "smull v14.4s, v27.4h, v21.4h", + "smull2 v15.4s, v27.8h, v21.8h", + "addp v26.4s, v14.4s, v15.4s", + "smull v14.4s, v11.4h, v12.4h", + "smull2 v11.4s, v11.8h, v12.8h", + "addp v11.4s, v14.4s, v11.4s", + "smull v14.4s, v28.4h, v20.4h", + "smull2 v15.4s, v28.8h, v20.8h", + "addp v27.4s, v14.4s, v15.4s", + "smull v14.4s, v9.4h, v10.4h", + "smull2 v9.4s, v9.8h, v10.8h", + "addp v9.4s, v14.4s, v9.4s", + "smull v14.4s, v29.4h, v19.4h", + "smull2 v15.4s, v29.8h, v19.8h", + "addp v28.4s, v14.4s, v15.4s", + "smull v14.4s, v7.4h, v8.4h", + "smull2 v7.4s, v7.8h, v8.8h", + "addp v7.4s, v14.4s, v7.4s", + "smull v14.4s, v30.4h, v18.4h", + "smull2 v15.4s, v30.8h, v18.8h", + "addp v29.4s, v14.4s, v15.4s", + "smull v14.4s, v5.4h, v6.4h", + "smull2 v5.4s, v5.8h, v6.8h", + "addp v5.4s, v14.4s, v5.4s", + "smull v14.4s, v31.4h, v17.4h", + "smull2 v15.4s, v31.8h, v17.8h", + "addp v30.4s, v14.4s, v15.4s", + "ldr q14, [sp, #32]", + "ldr q15, [sp, #64]", + "str q6, [sp, #96]", + "smull v6.4s, v14.4h, v15.4h", + "smull2 v14.4s, v14.8h, v15.8h", + "addp v6.4s, v6.4s, v14.4s", + "smull v14.4s, v16.4h, v16.4h", + "smull2 v15.4s, v16.8h, v16.8h", + "addp v31.4s, v14.4s, v15.4s", + "ldr q14, [sp]", + "smull v15.4s, v14.4h, v14.4h", + "str q8, [sp, #128]", + "smull2 v8.4s, v14.8h, v14.8h", + "addp v8.4s, v15.4s, v8.4s", + "stp q6, q8, [x28, #256]", + "stp q7, q5, [x28, #224]", + "stp q11, q9, [x28, #192]", + "stp q4, q13, [x28, #160]", + "stp q2, q3, [x28, #128]", + "stp q10, q12, [x28, #96]", + "ldr q2, [sp, #96]", + "ldr q3, [sp, #128]", + "stp q2, q3, [x28, #64]", + "ldr q2, [sp, #64]", + "stp q14, q2, [x28, #32]", + "add sp, sp, #0xa0 (160)" + ] } } }