Merge pull request #5968 from javelina-pkwy/feat/rdrand-fallback

Add software fallback for RDRAND/RDSEED

FEXCore/Source/Interface/Config/Config.json.in

@@ -141,6 +141,14 @@
           "Hides hybrid CPU core arrangement."
         ]
       },
+      "SoftwareRNG": {
+        "Type": "bool",
+        "Default": "false",
+        "AffectsCodeGen": "true",
+        "Desc": [
+          "Emulates RDRAND and RDSEED in software when the host does not implement FEAT_RNG."
+        ]
+      },
       "CPUFeatureRegisters": {
         "Type": "str",
         "Default": "",

FEXCore/Source/Interface/Context/Context.h

@@ -369,10 +369,16 @@ public:
     FEX_CONFIG_OPT(DisableTelemetry, DISABLETELEMETRY);
     FEX_CONFIG_OPT(DisableVixlIndirectCalls, DISABLE_VIXL_INDIRECT_RUNTIME_CALLS);
     FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
+    FEX_CONFIG_OPT(SoftwareRNG, SOFTWARERNG);
     FEX_CONFIG_OPT(StrictInProcessSplitLocks, STRICTINPROCESSSPLITLOCKS);
     FEX_CONFIG_OPT(MonoHacks, MONOHACKS);
   } Config;
 
+  bool SoftwareRNGEnabled() const {
+    return Config.SoftwareRNG() && HostRNGAvailable;
+  }
+  bool HostRNGAvailable {};
+
   FEXCore::Utils::WritePriorityMutex::Mutex CodeInvalidationMutex {};
 
   uint32_t StrictSplitLockMutex {};

FEXCore/Source/Interface/Core/CPUID.cpp

@@ -458,6 +458,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
             (Cores << 16) |     // Number of addressable IDs for the logical cores in the physical CPU
             (GetCPUID() << 24); // Local APIC ID
 
+  const uint32_t SupportsRAND = CTX->HostFeatures.SupportsRAND || CTX->SoftwareRNGEnabled();
+
   Res.ecx = (1 << 0) |                                      // SSE3
             (CTX->HostFeatures.SupportsPMULL_128Bit << 1) | // PCLMULQDQ
             (1 << 2) |                                      // DS area supports 64bit layout
@@ -488,7 +490,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
             (SupportsAVX() << 27) |                         // OSXSAVE
             (SupportsAVX() << 28) |                         // AVX
             (SupportsAVX() << 29) |                         // F16C
-            (CTX->HostFeatures.SupportsRAND << 30) |        // RDRAND
+            (SupportsRAND << 30) |                          // RDRAND
             (Hypervisor << 31);
 
   Res.edx = (1 << 0) |  // FPU
@@ -670,42 +672,44 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
     const uint32_t SupportsVPCLMULQDQ = CTX->HostFeatures.SupportsPMULL_128Bit && SupportsAVX();
     const uint32_t SupportsWFXT = CTX->HostFeatures.SupportsWFXT;
 
+    const uint32_t SupportsRAND = CTX->HostFeatures.SupportsRAND || CTX->SoftwareRNGEnabled();
+
     // Number of subfunctions
     // TODO: For now, subfunction 1 only exposes AVX-VNNI so we make it conditional
     // on AVX-VNNI support. We should revisit this if/when we add more to this leaf.
     Res.eax = SupportsAVXVNNI;
-    Res.ebx = (1 << 0) |                               // FS/GS support
-              (0 << 1) |                               // TSC adjust MSR
-              (0 << 2) |                               // SGX
-              (SupportsAVX() << 3) |                   // BMI1
-              (0 << 4) |                               // Intel Hardware Lock Elison
-              (SupportsAVX() << 5) |                   // AVX2 support
-              (1 << 6) |                               // FPU data pointer updated only on exception
-              (1 << 7) |                               // SMEP support
-              (SupportsAVX() << 8) |                   // BMI2
-              (SupportsEnhancedREPMOVS << 9) |         // Enhanced REP MOVSB/STOSB
-              (1 << 10) |                              // INVPCID for system software control of process-context
-              (0 << 11) |                              // Restricted transactional memory
-              (0 << 12) |                              // Intel resource directory technology Monitoring
-              (1 << 13) |                              // Deprecates FPU CS and DS
-              (0 << 14) |                              // Intel MPX
-              (0 << 15) |                              // Intel Resource Directory Technology Allocation
-              (0 << 16) |                              // AVX512-F
-              (0 << 17) |                              // AVX512-DQ
-              (CTX->HostFeatures.SupportsRAND << 18) | // RDSEED
-              (1 << 19) |                              // ADCX and ADOX instructions
-              (0 << 20) |                              // SMAP Supervisor mode access prevention and CLAC/STAC instructions
-              (0 << 21) |                              // AVX512-IFMA
-              (0 << 22) |                              // PCOMMIT (deprecated?)
-              (1 << 23) |                              // CLFLUSHOPT instruction
-              (1 << 24) |                              // CLWB instruction
-              (0 << 25) |                              // Intel processor trace
-              (0 << 26) |                              // AVX512-PF
-              (0 << 27) |                              // AVX512-ER
-              (0 << 28) |                              // AVX512-CD
-              (Features.SHA << 29) |                   // SHA instructions
-              (0 << 30) |                              // AVX512-BW
-              (0 << 31);                               // AVX512-VL
+    Res.ebx = (1 << 0) |                       // FS/GS support
+              (0 << 1) |                       // TSC adjust MSR
+              (0 << 2) |                       // SGX
+              (SupportsAVX() << 3) |           // BMI1
+              (0 << 4) |                       // Intel Hardware Lock Elison
+              (SupportsAVX() << 5) |           // AVX2 support
+              (1 << 6) |                       // FPU data pointer updated only on exception
+              (1 << 7) |                       // SMEP support
+              (SupportsAVX() << 8) |           // BMI2
+              (SupportsEnhancedREPMOVS << 9) | // Enhanced REP MOVSB/STOSB
+              (1 << 10) |                      // INVPCID for system software control of process-context
+              (0 << 11) |                      // Restricted transactional memory
+              (0 << 12) |                      // Intel resource directory technology Monitoring
+              (1 << 13) |                      // Deprecates FPU CS and DS
+              (0 << 14) |                      // Intel MPX
+              (0 << 15) |                      // Intel Resource Directory Technology Allocation
+              (0 << 16) |                      // AVX512-F
+              (0 << 17) |                      // AVX512-DQ
+              (SupportsRAND << 18) |           // RDSEED
+              (1 << 19) |                      // ADCX and ADOX instructions
+              (0 << 20) |                      // SMAP Supervisor mode access prevention and CLAC/STAC instructions
+              (0 << 21) |                      // AVX512-IFMA
+              (0 << 22) |                      // PCOMMIT (deprecated?)
+              (1 << 23) |                      // CLFLUSHOPT instruction
+              (1 << 24) |                      // CLWB instruction
+              (0 << 25) |                      // Intel processor trace
+              (0 << 26) |                      // AVX512-PF
+              (0 << 27) |                      // AVX512-ER
+              (0 << 28) |                      // AVX512-CD
+              (Features.SHA << 29) |           // SHA instructions
+              (0 << 30) |                      // AVX512-BW
+              (0 << 31);                       // AVX512-VL
 
     Res.ecx = (1 << 0) |                                // PREFETCHWT1
               (0 << 1) |                                // AVX512VBMI

FEXCore/Source/Interface/Core/Core.cpp

@@ -105,6 +105,14 @@ ContextImpl::ContextImpl(const FEXCore::HostFeatures& Features)
   // Track atomic TSO emulation configuration.
   UpdateAtomicTSOEmulationConfig();
 
+#ifndef _WIN32
+  // Check if the kernel supports getrandom().
+  uint64_t Probe {};
+  HostRNGAvailable = FHU::Syscalls::getrandom(&Probe, sizeof(Probe), 0) == sizeof(Probe);
+#else
+  HostRNGAvailable = true;
+#endif
+
   DiskCache.Init(this);
 }
 

FEXCore/Source/Interface/Core/DiskCache.h

@@ -244,7 +244,7 @@ namespace DiskCache {
   // The current version of the diskcache.
   // This must be changed any time codegen changes occur!
   // Be aware of the impact of changing this frequently!
-  static constexpr uint16_t FormatVersion = 24;
+  static constexpr uint16_t FormatVersion = 25;
 
   static constexpr uint32_t LOOKUP_KEY_MAX_BUCKET_DEPTH = 20;
 

FEXCore/Source/Interface/Core/JIT/JIT.cpp

@@ -36,7 +36,14 @@ $end_info$
 
 #include <cstdio>
 #include <cstring>
+#include <optional>
+#include <type_traits>
 #include <unistd.h>
+#ifdef _WIN32
+#include <atomic>
+#else
+#include <FEXHeaderUtils/Syscalls.h>
+#endif
 
 namespace {
 struct DivRem {
@@ -63,6 +70,35 @@ LDIV(uint64_t SrcHigh, uint64_t SrcLow, int64_t Divisor) {
   };
 }
 
+#ifndef _WIN32
+
+static std::optional<uint64_t>
+RDRANDFallback(uint64_t Reseed) {
+  uint64_t Value {};
+  FHU::Syscalls::getrandom(&Value, sizeof(Value), 0);
+  return Value;
+}
+
+#else
+
+// Windows does not have an equivalent to getrandom() without dynamically linking
+// bcrypt et al. Since this fallback is just for compat it does not need to be
+// cryptographic, so instead we vendor SplitMix64 as a naive fallback.
+
+// Reference implementation by Sebastiano Vigna, public domain (CC0)
+// https://prng.di.unimi.it/splitmix64.c
+static std::atomic<uint64_t>
+  RNGState {static_cast<uint64_t>(__builtin_readcyclecounter())};
+
+static std::optional<uint64_t> RDRANDFallback(uint64_t Reseed) {
+  const uint64_t State = RNGState.load(std::memory_order_relaxed) + 0x9E3779B97F4A7C15ULL;
+  RNGState.store(State, std::memory_order_relaxed);
+  uint64_t Value = (State ^ (State >> 30)) * 0xBF58476D1CE4E5B9ULL;
+  Value = (Value ^ (Value >> 27)) * 0x94D049BB133111EBULL;
+  return Value ^ (Value >> 31);
+}
+#endif
+
 static void
 PrintValue(uint64_t Value) {
   LogMan::Msg::DFmt("Value: 0x{:x}", Value);
@@ -664,6 +700,7 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In
     Ptrs.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Arm64JITCore::ExitFunctionLink);
     Ptrs.LUDIV = reinterpret_cast<uint64_t>(LUDIV);
     Ptrs.LDIV = reinterpret_cast<uint64_t>(LDIV);
+    Ptrs.RDRANDFallback = reinterpret_cast<uint64_t>(RDRANDFallback);
   }
 
   CurrentCodeBuffer = SharedCodeBuffers.GetLatest();

FEXCore/Source/Interface/Core/JIT/MiscOps.cpp

@@ -309,7 +309,39 @@ DEF_OP(ProcessorID) {
 DEF_OP(RDRAND) {
   auto Op = IROp->C<IR::IROp_RDRAND>();
 
-  mrs(GetReg(Node), Op->GetReseeded ? ARMEmitter::SystemRegister::RNDRRS : ARMEmitter::SystemRegister::RNDR);
+  if (CTX->HostFeatures.SupportsRAND) {
+    mrs(GetReg(Node), Op->GetReseeded ? ARMEmitter::SystemRegister::RNDRRS : ARMEmitter::SystemRegister::RNDR);
+    return;
+  }
+
+  // Software fallback, call the host RNG generator.
+  PushDynamicRegs(TMP4);
+  SpillStaticRegs(TMP4);
+
+  // x0 = Reseed
+  // x1 = Generator
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, Op->GetReseeded ? 1 : 0);
+  ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.RDRANDFallback));
+
+  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
+    GenerateIndirectRuntimeCall<__uint128_t, uint64_t>(ARMEmitter::Reg::r1);
+  } else {
+    blr(ARMEmitter::Reg::r1);
+  }
+
+  if (!TMP_ABIARGS) {
+    mov(ARMEmitter::Size::i64Bit, TMP1, ARMEmitter::Reg::r0);
+    mov(ARMEmitter::Size::i64Bit, TMP2, ARMEmitter::Reg::r1);
+  }
+
+  FillStaticRegs();
+  PopDynamicRegs();
+
+  // Results are in x0, x1
+  // std::optional<uint64_t>: value in x0, engaged flag in the low byte of x1. Match the hardware behaviour of setting Z when
+  // no number was produced.
+  mov(ARMEmitter::Size::i64Bit, GetReg(Node), TMP1);
+  tst(ARMEmitter::Size::i64Bit, TMP2, 0xFF);
 }
 
 DEF_OP(Yield) {

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -5125,7 +5125,7 @@ void OpDispatchBuilder::CRC32(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::RDRANDOp(OpcodeArgs, bool Reseed) {
-  if (!CTX->HostFeatures.SupportsRAND) {
+  if (!CTX->HostFeatures.SupportsRAND && !CTX->SoftwareRNGEnabled()) {
     UnimplementedOp(Op);
     return;
   }

FEXCore/Source/Interface/IR/IR.json

@@ -275,7 +275,8 @@
                  "The boolean argument asks if we should be reading the reseeded number or not",
                  "Reseeded RNG calculation is more expensive and will be heavier to use",
                  "Returns the 64-bit number",
-                 "Sets the Z flag if the number is valid.",
+                 "Falls back to a host RNG call when the hardware doesn't support it",
+                 "Sets the Z flag if the number is invalid.",
                  "RNG hardware is allowed to fail early and return. Software must always check this"
                 ],
         "HasSideEffects": true,

FEXCore/include/FEXCore/Core/CoreState.h

@@ -350,6 +350,7 @@ struct JITPointers {
   uint64_t MonoBackpatcherWrite {};
   uint64_t LUDIV {};
   uint64_t LDIV {};
+  uint64_t RDRANDFallback {};
   uint64_t ThunkCallbackRet {};
 
   // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3

FEXHeaderUtils/FEXHeaderUtils/Syscalls.h

@@ -96,6 +96,10 @@ inline int32_t renameat2(int olddirfd, const char* oldpath, int newdirfd, const
 inline int32_t pidfd_open(pid_t pid, unsigned int flags) {
   return ::syscall(SYS_pidfd_open, pid, flags);
 }
+
+inline ssize_t getrandom(void* buf, size_t buflen, unsigned int flags) {
+  return ::syscall(SYS_getrandom, buf, buflen, flags);
+}
 #else
 
 inline int32_t getcpu(uint32_t* cpu, uint32_t* node) {

unittests/FEXLinuxTests/CMakeLists.txt

@@ -63,6 +63,11 @@ function(AddTests Tests BinDirectory Bitness)
       set_property(TEST "${TEST_CASE}.jit.flt" APPEND PROPERTY ENVIRONMENT "FEX_THUNKCONFIG=${CMAKE_SOURCE_DIR}/Data/CI/FEXLinuxTestsThunks.json")
     endif()
 
+    if(TEST_NAME STREQUAL "rdrand")
+      # Force use of the software fallback to exercise that path
+      set_property(TEST "${TEST_CASE}.jit.flt" APPEND PROPERTY ENVIRONMENT "FEX_HOSTFEATURES=disablerng;FEX_SOFTWARERNG=1")
+    endif()
+
     if(TEST_NAME STREQUAL "vulkan_procaddr")
       set_property(TEST "${TEST_CASE}.jit.flt" APPEND PROPERTY ENVIRONMENT
         "FEX_THUNKCONFIG=${CMAKE_SOURCE_DIR}/Data/CI/VulkanThunks.json;FEX_THUNKHOSTLIBS=${HOSTLIBS_DATA_DIRECTORY}/HostThunks;FEX_THUNKGUESTLIBS=${CMAKE_INSTALL_PREFIX}/share/fex-emu/GuestThunks")

unittests/FEXLinuxTests/tests/cpu/rdrand.cpp

@@ -0,0 +1,37 @@
+#include <catch2/catch_test_macros.hpp>
+
+#include <cstdint>
+
+// Retries until the instruction reports success.
+// clang-format off
+#define RNG(insn, Value)            \
+  __asm volatile(".Lretry%=:\n"     \
+                 insn " %0\n"       \
+                 "jnc .Lretry%=\n"  \
+                 : "=r"(Value)      \
+                 :                  \
+                 : "cc")
+// clang-format on
+
+// This test is designed to test the software fallback implementation for RDRAND and RDSEED.
+// To that end, it is executed with FEX_HOSTFEATURES=disablerng.
+
+TEST_CASE("rdrand") {
+  uint32_t eax, ebx, ecx, edx;
+  __asm volatile("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "a"(1), "c"(0));
+  CHECK((ecx >> 30) & 1); // RDRAND
+  __asm volatile("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "a"(7), "c"(0));
+  CHECK((ebx >> 18) & 1); // RDSEED
+
+  uintptr_t A, B;
+  RNG("rdrand", A);
+  RNG("rdrand", B);
+
+  // This assert is not technically correct,
+  // but at a 1/(2^32) chance of failure, I like our odds.
+  CHECK(A != B);
+
+  RNG("rdseed", A);
+  RNG("rdseed", B);
+  CHECK(A != B);
+}

unittests/InstructionCountCI/AFP/H0F3A.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "roundss xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/AFP/SVE256/Secondary.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {

unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {

unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {

unittests/InstructionCountCI/AFP/Secondary.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {

unittests/InstructionCountCI/AFP/Secondary_REP.json

@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {

unittests/InstructionCountCI/AFP/Secondary_REPNE.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {

unittests/InstructionCountCI/AFP/VEX_map1.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vsqrtss xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AFP/VEX_map3.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vroundss xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/AVX128/FMA4.json

@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
@@ -20,7 +20,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -34,7 +34,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -48,7 +48,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -62,7 +62,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -76,7 +76,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -90,7 +90,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -104,7 +104,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -118,7 +118,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -132,7 +132,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -146,7 +146,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -160,7 +160,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -174,7 +174,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -188,7 +188,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -202,7 +202,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -216,7 +216,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -230,7 +230,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -244,7 +244,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -258,7 +258,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -272,7 +272,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -286,7 +286,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -300,7 +300,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -314,7 +314,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -328,7 +328,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -342,7 +342,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -356,7 +356,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -370,7 +370,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -384,7 +384,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -398,7 +398,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -412,7 +412,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -426,7 +426,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     }

unittests/InstructionCountCI/AVX128/VEX_map1.json

@@ -13,7 +13,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {
@@ -1116,7 +1116,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1128,7 +1128,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1140,7 +1140,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1165,7 +1165,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1179,7 +1179,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1193,7 +1193,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1217,7 +1217,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1229,7 +1229,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1241,7 +1241,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1268,7 +1268,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1282,7 +1282,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1296,7 +1296,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1320,7 +1320,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1332,7 +1332,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1344,7 +1344,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -1371,7 +1371,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1385,7 +1385,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1399,7 +1399,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
-        "ldr x0, [x28, #2720]",
+        "ldr x0, [x28, #2728]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -2283,7 +2283,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -2297,7 +2297,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q4, [x0, #16]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2310,7 +2310,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -2324,7 +2324,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q4, [x0, #32]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2337,7 +2337,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
@@ -2351,7 +2351,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q4, [x0, #48]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",

unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json

@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vmovntps [rax], xmm0": {

unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json

@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {

unittests/InstructionCountCI/AVX128/VEX_map2.json

@@ -11,7 +11,7 @@
       "I8MM",
       "DOTPROD"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json

@@ -8,7 +8,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vfmadd132ss xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json

@@ -12,7 +12,7 @@
       "SVE256",
       "I8MM"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json

@@ -11,7 +11,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vmovntdqa xmm0, [rax]": {

unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json

@@ -11,7 +11,7 @@
       "SVE256",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {

unittests/InstructionCountCI/AVX128/VEX_map3.json

@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {

unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json

@@ -8,7 +8,7 @@
       "AFP",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vblendvps xmm0, xmm1, xmm2, xmm3": {

unittests/InstructionCountCI/AVX128/VEX_map_group.json

@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {

unittests/InstructionCountCI/Atomics.json

@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "lock add byte [rax], cl": {

unittests/InstructionCountCI/Crypto/H0F38.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {
@@ -32,7 +32,7 @@
         "0x66 0x0f 0x38 0xca"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q2, [x0, #432]",
         "tbl v3.16b, {v16.16b}, v2.16b",
         "tbl v4.16b, {v17.16b}, v2.16b",

unittests/InstructionCountCI/Crypto/H0F38_SVE128.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {

unittests/InstructionCountCI/Crypto/H0F3A.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "pclmulqdq xmm0, xmm1, 00000b": {
@@ -87,7 +87,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #3712]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -104,7 +104,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #3728]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -121,7 +121,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #3744]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -138,7 +138,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #3760]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",

unittests/InstructionCountCI/DDD.json

@@ -10,7 +10,7 @@
       "AFP",
       "RPRES"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",

unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json

@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"

unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json

@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"

unittests/InstructionCountCI/FEXOpt/MultiInst.json

@@ -13,7 +13,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json

@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json

@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json

@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json

@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/libnss.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [],
   "Instructions": {

unittests/InstructionCountCI/FlagM/Atomics.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "lock add byte [rax], cl": {

unittests/InstructionCountCI/FlagM/FlagOpts.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Chained add": {

unittests/InstructionCountCI/FlagM/H0F38.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "ptest xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/HotBlocks.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "The Witcher 3": {
@@ -896,8 +896,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0xd",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",

unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Sonic Mania movie player": {

unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json

@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "FMOD scalar loop": {

unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "The Sims 1 hot block": {

unittests/InstructionCountCI/FlagM/Primary.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "add bl, cl": {

unittests/InstructionCountCI/FlagM/PrimaryGroup.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "add al, 1": {

unittests/InstructionCountCI/FlagM/Primary_32Bit.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "push es": {

unittests/InstructionCountCI/FlagM/Secondary.json

@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "ucomiss xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/SecondaryGroup.json

@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "sgdt [rax]": {

unittests/InstructionCountCI/FlagM/SecondaryModRM.json

@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "xgetbv": {

unittests/InstructionCountCI/FlagM/Secondary_OpSize.json

@@ -11,7 +11,7 @@
       "AFP",
       "FCMA"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "ucomisd xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/Secondary_REP.json

@@ -12,7 +12,7 @@
       "AFP",
       "CSSC"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "popcnt ax, bx": {

unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "popcnt ax, bx": {

unittests/InstructionCountCI/FlagM/VEX_map1.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {
@@ -84,7 +84,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2536]",
+        "ldr x0, [x28, #2544]",
         "ld1b {z2.b}, p7/z, [x0]",
         "mrs x0, nzcv",
         "mov z0.d, #0",

unittests/InstructionCountCI/FlagM/VEX_map2.json

@@ -10,7 +10,7 @@
       "AFP",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/VEX_map_group.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "blsr eax, ebx": {

unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2201,7 +2201,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3056]",
+        "ldr x0, [x28, #3064]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2224,7 +2224,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3080]",
+        "ldr x0, [x28, #3088]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2248,7 +2248,7 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3048]",
+        "ldr x0, [x28, #3056]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2284,7 +2284,7 @@
         "ldr d3, [x22, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3072]",
+        "ldr x0, [x28, #3080]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2361,7 +2361,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3104]",
+        "ldr x0, [x28, #3112]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2411,7 +2411,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3096]",
+        "ldr x0, [x28, #3104]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2435,7 +2435,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3088]",
+        "ldr x0, [x28, #3096]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2472,13 +2472,13 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3032]",
+        "ldr x0, [x28, #3040]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2525,7 +2525,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3064]",
+        "ldr x0, [x28, #3072]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2543,7 +2543,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3032]",
+        "ldr x0, [x28, #3040]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2562,7 +2562,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -3458,8 +3458,8 @@
         "ld1 {v2.h}[4], [x20]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -3487,8 +3487,8 @@
         "ldr d2, [x21, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5514,8 +5514,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5527,8 +5527,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5540,8 +5540,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5553,8 +5553,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5566,8 +5566,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5579,8 +5579,8 @@
         "and v3.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
@@ -5592,8 +5592,8 @@
         "and v2.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -5606,8 +5606,8 @@
         "mov v2.h[4], v3.h[0]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -5656,8 +5656,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5668,8 +5668,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5680,8 +5680,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5692,8 +5692,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5704,8 +5704,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5716,8 +5716,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5728,8 +5728,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -5740,8 +5740,8 @@
         "ldr d2, [x0, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
@@ -8185,15 +8185,15 @@
         "ld1 {v2.h}[4], [x20]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #2008]",
-        "ldr x3, [x28, #2016]",
+        "ldr x0, [x28, #2016]",
+        "ldr x3, [x28, #2024]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #1688]",
-        "ldr x3, [x28, #1696]",
+        "ldr x0, [x28, #1696]",
+        "ldr x3, [x28, #1704]",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -8221,15 +8221,15 @@
         "ldr d2, [x21, #1056]",
         "str x30, [sp, #-16]!",
         "fmov d0, d2",
-        "ldr x0, [x28, #1656]",
-        "ldr x3, [x28, #1664]",
+        "ldr x0, [x28, #1664]",
+        "ldr x3, [x28, #1672]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
-        "ldr x0, [x28, #1992]",
-        "ldr x3, [x28, #2000]",
+        "ldr x0, [x28, #2000]",
+        "ldr x3, [x28, #2008]",
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",

unittests/InstructionCountCI/H0F38.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "pshufb mm0, mm1": {

unittests/InstructionCountCI/H0F3A.json

@@ -8,7 +8,7 @@
       "AFP",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "SSE4.2 string instructions are skipped here.",
@@ -475,7 +475,7 @@
         "0x66 0x0f 0x3a 0x0e"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2768]",
+        "ldr x0, [x28, #2776]",
         "ldr q2, [x0, #3440]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]

unittests/InstructionCountCI/H0F3A_SVE128.json

@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "dpps xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/MOPS/Primary.json

@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "rep movsb": {

unittests/InstructionCountCI/Primary.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "MOPS"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "add bl, cl": {
@@ -2473,7 +2473,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -2488,7 +2488,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },
@@ -2503,7 +2503,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2968]",
+        "ldr x0, [x28, #2976]",
         "br x0"
       ]
     },

unittests/InstructionCountCI/PrimaryGroup.json

@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
@@ -2787,7 +2787,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3016]",
+        "ldr x3, [x28, #3024]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2838,7 +2838,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3024]",
+        "ldr x3, [x28, #3032]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",

unittests/InstructionCountCI/Primary_32Bit.json

@@ -9,7 +9,7 @@
       "FlagM",
       "FlagM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "push es": {

unittests/InstructionCountCI/RPRES/DDD.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "pfrcpv mm0, mm1": {

unittests/InstructionCountCI/RPRES/Secondary.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "rsqrtps xmm0, xmm1": {

unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "rsqrtss xmm0, xmm1": {

unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json

@@ -8,7 +8,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "vrsqrtps xmm0, xmm1": {

unittests/InstructionCountCI/Repeat.json

@@ -6,7 +6,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {}
 }

unittests/InstructionCountCI/SSE42_Strings.json

@@ -33,7 +33,7 @@
       "      - 1b: ECX = MSB",
       "[7]   - Reserved"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
@@ -43,8 +43,8 @@
         "0x66 0x0f 0x3A 0x60"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -69,8 +69,8 @@
         "0x66 0x0f 0x3A 0x60"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -95,8 +95,8 @@
         "0x66 0x0f 0x3A 0x60"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -153,8 +153,8 @@
         "0x66 0x0f 0x3A 0x60"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -195,8 +195,8 @@
         "0x66 0x0f 0x3A 0x61"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -225,8 +225,8 @@
         "0x66 0x0f 0x3A 0x61"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2360]",
-        "ldr x0, [x28, #2368]",
+        "ldr x3, [x28, #2368]",
+        "ldr x0, [x28, #2376]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -259,8 +259,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x0",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -283,8 +283,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x1",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -307,8 +307,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x40",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -363,8 +363,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x41",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -403,8 +403,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x0",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -431,8 +431,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x1",
-        "ldr x1, [x28, #2376]",
-        "ldr x3, [x28, #2384]",
+        "ldr x1, [x28, #2384]",
+        "ldr x3, [x28, #2392]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",

unittests/InstructionCountCI/Secondary.json

@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Comment": [
     "MMX instructions are defined as optimal without SRA being used for these instructions.",
@@ -3549,7 +3549,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
       ]
@@ -3558,7 +3558,7 @@
       "ExpectedInstructionCount": 5,
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q2, [x0, #16]",
         "mov v0.16b, v17.16b",
         "mov v1.16b, v16.16b",
@@ -3570,7 +3570,7 @@
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2744]",
+        "ldr x0, [x28, #2752]",
         "ldr q3, [x0, #16]",
         "mov v0.16b, v16.16b",
         "mov v1.16b, v2.16b",

unittests/InstructionCountCI/SecondaryGroup.json

@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "sgdt [rax]": {

unittests/InstructionCountCI/SecondaryModRM.json

@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "xgetbv": {

unittests/InstructionCountCI/Secondary_32Bit.json

@@ -7,7 +7,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "push fs": {

unittests/InstructionCountCI/Secondary_OpSize.json

@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "movupd xmm0, xmm0": {
@@ -526,7 +526,7 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -540,7 +540,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v2.16b}, v3.16b"
       ]
@@ -678,7 +678,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2736]",
+        "ldr x0, [x28, #2744]",
         "ldr q3, [x0, #2480]",
         "tbl v16.16b, {v2.16b}, v3.16b"
       ]

unittests/InstructionCountCI/Secondary_OpSize_FCMA.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "addsubpd xmm0, xmm1": {

unittests/InstructionCountCI/Secondary_OpSize_SVE128.json

@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "psrlw xmm0, xmm1": {

unittests/InstructionCountCI/Secondary_OpSize_SVE256.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "pmulhuw xmm0, xmm1": {

unittests/InstructionCountCI/Secondary_REP.json

@@ -12,7 +12,7 @@
       "FRINTTS",
       "CSSC"
     ],
-    "BinaryCacheVersion": 24
+    "BinaryCacheVersion": 25
   },
   "Instructions": {
     "movss xmm0, xmm1": {
@@ -398,7 +398,7 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q2, [x0, #1280]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -411,7 +411,7 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2728]",
+        "ldr x0, [x28, #2736]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]