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InstrCountCI: Bump disk cache version and regen

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This commit is contained in:
Justin Becker committed 2026-09-17 11:25:52 -07:00
1 parent 26f0e5017f
commit 54b178d151
107 files changed
+14334 -14334
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FEXCore/Source/Interface/Core/DiskCache.h
+1 -1
View File
@@ -224,7 +224,7 @@ namespace DiskCache {
// The current version of the diskcache.
// This must be changed any time codegen changes occur!
// Be aware of the impact of changing this frequently!
static constexpr uint16_t FormatVersion = 24;
static constexpr uint16_t FormatVersion = 25;
} // namespace DiskCache
unittests/InstructionCountCI/AFP/H0F3A.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"roundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/VEX_map1.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vsqrtss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AFP/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vroundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AVX128/FMA4.json
+31 -31
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
@@ -20,7 +20,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -34,7 +34,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -48,7 +48,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -62,7 +62,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -76,7 +76,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -90,7 +90,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -104,7 +104,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -118,7 +118,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -132,7 +132,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -146,7 +146,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -160,7 +160,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -174,7 +174,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -188,7 +188,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -202,7 +202,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -216,7 +216,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -230,7 +230,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -244,7 +244,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -258,7 +258,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -272,7 +272,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -286,7 +286,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -300,7 +300,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -314,7 +314,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -328,7 +328,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -342,7 +342,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -356,7 +356,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -370,7 +370,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -384,7 +384,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -398,7 +398,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -412,7 +412,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -426,7 +426,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
}
unittests/InstructionCountCI/AVX128/VEX_map1.json
+25 -25
View File
@@ -13,7 +13,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vmovups xmm0, xmm0": {
@@ -1116,7 +1116,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1128,7 +1128,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1140,7 +1140,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1165,7 +1165,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1179,7 +1179,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1193,7 +1193,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1217,7 +1217,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1229,7 +1229,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1241,7 +1241,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1268,7 +1268,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1282,7 +1282,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1296,7 +1296,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1320,7 +1320,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1332,7 +1332,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1344,7 +1344,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -1371,7 +1371,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1385,7 +1385,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1399,7 +1399,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -2283,7 +2283,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -2297,7 +2297,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2310,7 +2310,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -2324,7 +2324,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2337,7 +2337,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #192]"
@@ -2351,7 +2351,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"ldr q3, [x28, #224]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vmovntps [rax], xmm0": {
unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vucomiss xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map2.json
+1 -1
View File
@@ -11,7 +11,7 @@
"I8MM",
"DOTPROD"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vfmadd132ss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json
+1 -1
View File
@@ -12,7 +12,7 @@
"SVE256",
"I8MM"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vmovntdqa xmm0, [rax]": {
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"SVEBITPERM"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vblendvps xmm0, xmm1, xmm2, xmm3": {
unittests/InstructionCountCI/AVX128/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
unittests/InstructionCountCI/Atomics.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/Crypto/H0F38.json
+2 -2
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
@@ -32,7 +32,7 @@
"0x66 0x0f 0x38 0xca"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #432]",
"tbl v3.16b, {v16.16b}, v2.16b",
"tbl v4.16b, {v17.16b}, v2.16b",
unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
unittests/InstructionCountCI/Crypto/H0F3A.json
+5 -5
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pclmulqdq xmm0, xmm1, 00000b": {
@@ -87,7 +87,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3712]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -104,7 +104,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3728]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -121,7 +121,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3744]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -138,7 +138,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3760]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
unittests/InstructionCountCI/DDD.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"RPRES"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+1 -1
View File
@@ -13,7 +13,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/libnss.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [],
"Instructions": {
unittests/InstructionCountCI/FlagM/Atomics.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/FlagM/FlagOpts.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Chained add": {
unittests/InstructionCountCI/FlagM/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"ptest xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/HotBlocks.json
+3 -3
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"The Witcher 3": {
@@ -896,8 +896,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0xd",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Sonic Mania movie player": {
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"FMOD scalar loop": {
unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"The Sims 1 hot block": {
unittests/InstructionCountCI/FlagM/Primary.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"add bl, cl": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"add al, 1": {
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"ucomiss xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"sgdt [rax]": {
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+1 -1
View File
@@ -11,7 +11,7 @@
"AFP",
"FCMA"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"ucomisd xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+1 -1
View File
@@ -12,7 +12,7 @@
"AFP",
"CSSC"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/VEX_map1.json
+2 -2
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vucomiss xmm0, xmm1": {
@@ -84,7 +84,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2536]",
"ldr x0, [x28, #2544]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
unittests/InstructionCountCI/FlagM/VEX_map2.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"SVEBITPERM"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"blsr eax, ebx": {
unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+1919 -1919
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+383 -383
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+4577 -4577
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+5845 -5845
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+619 -619
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64.json
+57 -57
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"fadd dword [rax]": {
@@ -2201,7 +2201,7 @@
"add x20, x28, x20, lsl #4",
"ldr d2, [x20, #1056]",
"fmov d0, d2",
"ldr x0, [x28, #3056]",
"ldr x0, [x28, #3064]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2224,7 +2224,7 @@
"ldr d3, [x23, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3080]",
"ldr x0, [x28, #3088]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2248,7 +2248,7 @@
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"fmov d0, d2",
"ldr x0, [x28, #3048]",
"ldr x0, [x28, #3056]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2284,7 +2284,7 @@
"ldr d3, [x22, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3072]",
"ldr x0, [x28, #3080]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2361,7 +2361,7 @@
"ldr d3, [x20, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3104]",
"ldr x0, [x28, #3112]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2411,7 +2411,7 @@
"ldr d3, [x20, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3096]",
"ldr x0, [x28, #3104]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2435,7 +2435,7 @@
"ldr d3, [x23, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3088]",
"ldr x0, [x28, #3096]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2472,13 +2472,13 @@
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"fmov d0, d2",
"ldr x0, [x28, #3032]",
"ldr x0, [x28, #3040]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
"fmov d0, d2",
"ldr x0, [x28, #3040]",
"ldr x0, [x28, #3048]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2525,7 +2525,7 @@
"ldr d3, [x20, #1056]",
"fmov d0, d3",
"fmov d1, d2",
"ldr x0, [x28, #3064]",
"ldr x0, [x28, #3072]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2543,7 +2543,7 @@
"add x20, x28, x20, lsl #4",
"ldr d2, [x20, #1056]",
"fmov d0, d2",
"ldr x0, [x28, #3032]",
"ldr x0, [x28, #3040]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -2562,7 +2562,7 @@
"add x20, x28, x20, lsl #4",
"ldr d2, [x20, #1056]",
"fmov d0, d2",
"ldr x0, [x28, #3040]",
"ldr x0, [x28, #3048]",
"str x30, [sp, #-16]!",
"blr x0",
"ldr x30, [sp], #16",
@@ -3458,8 +3458,8 @@
"ld1 {v2.h}[4], [x20]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
@@ -3487,8 +3487,8 @@
"ldr d2, [x21, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5514,8 +5514,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5527,8 +5527,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5540,8 +5540,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5553,8 +5553,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5566,8 +5566,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5579,8 +5579,8 @@
"and v3.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d3, d0",
@@ -5592,8 +5592,8 @@
"and v2.16b, v3.16b, v2.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
@@ -5606,8 +5606,8 @@
"mov v2.h[4], v3.h[0]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
@@ -5656,8 +5656,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5668,8 +5668,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5680,8 +5680,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5692,8 +5692,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5704,8 +5704,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5716,8 +5716,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5728,8 +5728,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -5740,8 +5740,8 @@
"ldr d2, [x0, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
@@ -8185,15 +8185,15 @@
"ld1 {v2.h}[4], [x20]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #2008]",
"ldr x3, [x28, #2016]",
"ldr x0, [x28, #2016]",
"ldr x3, [x28, #2024]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"ldr x0, [x28, #1696]",
"ldr x3, [x28, #1704]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
@@ -8221,15 +8221,15 @@
"ldr d2, [x21, #1056]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"ldr x0, [x28, #1664]",
"ldr x3, [x28, #1672]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1992]",
"ldr x3, [x28, #2000]",
"ldr x0, [x28, #2000]",
"ldr x3, [x28, #2008]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"CRYPTO"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pshufb mm0, mm1": {
unittests/InstructionCountCI/H0F3A.json
+2 -2
View File
@@ -8,7 +8,7 @@
"AFP",
"CRYPTO"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"SSE4.2 string instructions are skipped here.",
@@ -475,7 +475,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2768]",
"ldr x0, [x28, #2776]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/H0F3A_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"dpps xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/MOPS/Primary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"rep movsb": {
unittests/InstructionCountCI/Primary.json
+4 -4
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"MOPS"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"add bl, cl": {
@@ -2473,7 +2473,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -2488,7 +2488,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
@@ -2503,7 +2503,7 @@
"str x20, [x28, #24]",
"mov w0, #0x401",
"str x0, [x28, #1496]",
"ldr x0, [x28, #2968]",
"ldr x0, [x28, #2976]",
"br x0"
]
},
unittests/InstructionCountCI/PrimaryGroup.json
+3 -3
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
@@ -2787,7 +2787,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3016]",
"ldr x3, [x28, #3024]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2838,7 +2838,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3024]",
"ldr x3, [x28, #3032]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
unittests/InstructionCountCI/Primary_32Bit.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FlagM",
"FlagM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/RPRES/DDD.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pfrcpv mm0, mm1": {
unittests/InstructionCountCI/RPRES/Secondary.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"rsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"rsqrtss xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vrsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/Repeat.json
+1 -1
View File
@@ -6,7 +6,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {}
}
unittests/InstructionCountCI/SSE42_Strings.json
+25 -25
View File
@@ -33,7 +33,7 @@
" - 1b: ECX = MSB",
"[7] - Reserved"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
@@ -43,8 +43,8 @@
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -69,8 +69,8 @@
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -95,8 +95,8 @@
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -153,8 +153,8 @@
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -195,8 +195,8 @@
"0x66 0x0f 0x3A 0x61"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -225,8 +225,8 @@
"0x66 0x0f 0x3A 0x61"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2360]",
"ldr x0, [x28, #2368]",
"ldr x3, [x28, #2368]",
"ldr x0, [x28, #2376]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -259,8 +259,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -283,8 +283,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x1",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -307,8 +307,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x40",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -363,8 +363,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x41",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -403,8 +403,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -431,8 +431,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x1",
"ldr x1, [x28, #2376]",
"ldr x3, [x28, #2384]",
"ldr x1, [x28, #2384]",
"ldr x3, [x28, #2392]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
unittests/InstructionCountCI/Secondary.json
+4 -4
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Comment": [
"MMX instructions are defined as optimal without SRA being used for these instructions.",
@@ -3549,7 +3549,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
]
@@ -3558,7 +3558,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #16]",
"mov v0.16b, v17.16b",
"mov v1.16b, v16.16b",
@@ -3570,7 +3570,7 @@
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q3, [x0, #16]",
"mov v0.16b, v16.16b",
"mov v1.16b, v2.16b",
unittests/InstructionCountCI/SecondaryGroup.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"sgdt [rax]": {
unittests/InstructionCountCI/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/Secondary_32Bit.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"push fs": {
unittests/InstructionCountCI/Secondary_OpSize.json
+4 -4
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"movupd xmm0, xmm0": {
@@ -526,7 +526,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -540,7 +540,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -678,7 +678,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #2480]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"addsubpd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"psrlw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pmulhuw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP.json
+3 -3
View File
@@ -12,7 +12,7 @@
"FRINTTS",
"CSSC"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"movss xmm0, xmm1": {
@@ -398,7 +398,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -411,7 +411,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+3 -3
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"movsd xmm0, xmm1": {
@@ -291,7 +291,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -304,7 +304,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"addsubps xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"cvttss2si eax, xmm0": {
unittests/InstructionCountCI/Secondary_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"movmskps eax, xmm0": {
unittests/InstructionCountCI/VEX_map1.json
+41 -41
View File
@@ -13,7 +13,7 @@
"FLAGM2",
"FRINTTS"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vmovups xmm0, xmm0": {
@@ -927,7 +927,7 @@
"sqxtnb z2.b, z17.h",
"uzp1 z2.b, z2.b, z2.b",
"splice z2.b, p6, z2.b, z1.b",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -1022,7 +1022,7 @@
"sqxtunb z2.b, z17.h",
"uzp1 z2.b, z2.b, z2.b",
"splice z2.b, p6, z2.b, z1.b",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -1042,7 +1042,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1053,7 +1053,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1064,7 +1064,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1100,7 +1100,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #16]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1117,7 +1117,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #32]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1134,7 +1134,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2736]",
"ldr x0, [x28, #2744]",
"ldr q3, [x0, #48]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1173,7 +1173,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1184,7 +1184,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1195,7 +1195,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1233,7 +1233,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #16]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1250,7 +1250,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #32]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1267,7 +1267,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2728]",
"ldr x0, [x28, #2736]",
"ldr q3, [x0, #48]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1306,7 +1306,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1317,7 +1317,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1328,7 +1328,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -1366,7 +1366,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #16]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1383,7 +1383,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #32]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -1400,7 +1400,7 @@
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"ldr x0, [x28, #2720]",
"ldr x0, [x28, #2728]",
"ldr q3, [x0, #48]",
"tbl v2.16b, {v2.16b}, v3.16b",
"tbl v3.16b, {v17.16b}, v3.16b",
@@ -2526,7 +2526,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2537,7 +2537,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2548,7 +2548,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2603,7 +2603,7 @@
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"mov z3.q, z18.q[1]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #16]",
"tbl v5.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2621,7 +2621,7 @@
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"mov z3.q, z18.q[1]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #32]",
"tbl v5.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2639,7 +2639,7 @@
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"mov z3.q, z18.q[1]",
"ldr x0, [x28, #2744]",
"ldr x0, [x28, #2752]",
"ldr q4, [x0, #48]",
"tbl v5.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -3641,9 +3641,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2664]",
"ldr x0, [x28, #2672]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2624]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -3675,9 +3675,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2664]",
"ldr x0, [x28, #2672]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2624]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -4090,7 +4090,7 @@
"sqxtnb z2.h, z17.s",
"uzp1 z2.h, z2.h, z2.h",
"splice z2.h, p6, z2.h, z1.h",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -4214,7 +4214,7 @@
"uzp1 z2.d, z0.d, z0.d",
"uzp2 z1.d, z0.d, z0.d",
"splice z2.d, p6, z2.d, z1.d",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -4239,7 +4239,7 @@
"uzp1 z2.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z2.d, p6, z2.d, z1.d",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -4264,7 +4264,7 @@
"uzp1 z2.d, z17.d, z18.d",
"uzp2 z3.d, z17.d, z18.d",
"fsub z2.d, z2.d, z3.d",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -4289,7 +4289,7 @@
"uzp1 z2.s, z17.s, z18.s",
"uzp2 z3.s, z17.s, z18.s",
"fsub z2.s, z2.s, z3.s",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -4367,7 +4367,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2424]",
"ldr x0, [x28, #2432]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@@ -4390,7 +4390,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2408]",
"ldr x0, [x28, #2416]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
@@ -4529,7 +4529,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2536]",
"ldr x0, [x28, #2544]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
@@ -4921,7 +4921,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3664]",
"ldr x0, [x28, #2640]",
"ldr x0, [x28, #2648]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -4983,7 +4983,7 @@
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #3664]",
"ldr x0, [x28, #2640]",
"ldr x0, [x28, #2648]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map1_FCMA.json
+1 -1
View File
@@ -8,7 +8,7 @@
"FCMA"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+7 -7
View File
@@ -13,7 +13,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vcvttss2si eax, xmm0": {
@@ -113,9 +113,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2664]",
"ldr x0, [x28, #2672]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2624]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -143,9 +143,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2664]",
"ldr x0, [x28, #2672]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2624]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -175,7 +175,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3664]",
"ldr x0, [x28, #2640]",
"ldr x0, [x28, #2648]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -210,7 +210,7 @@
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #3664]",
"ldr x0, [x28, #2640]",
"ldr x0, [x28, #2648]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map2.json
+20 -20
View File
@@ -13,7 +13,7 @@
"I8MM",
"DOTPROD"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
@@ -64,7 +64,7 @@
"uzp2 z1.h, z0.h, z0.h",
"uzp1 z2.h, z0.h, z0.h",
"splice z2.d, p6, z2.d, z1.d",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -89,7 +89,7 @@
"uzp2 z1.s, z0.s, z0.s",
"uzp1 z2.s, z0.s, z0.s",
"splice z2.d, p6, z2.d, z1.d",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -114,7 +114,7 @@
"uzp1 z2.h, z17.h, z18.h",
"uzp2 z3.h, z17.h, z18.h",
"sqadd z2.h, z2.h, z3.h",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -173,7 +173,7 @@
"uzp1 z2.h, z17.h, z18.h",
"uzp2 z3.h, z17.h, z18.h",
"sub z2.h, z2.h, z3.h",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -198,7 +198,7 @@
"uzp1 z2.s, z17.s, z18.s",
"uzp2 z3.s, z17.s, z18.s",
"sub z2.s, z2.s, z3.s",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -223,7 +223,7 @@
"uzp1 z2.h, z17.h, z18.h",
"uzp2 z3.h, z17.h, z18.h",
"sqsub z2.h, z2.h, z3.h",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -917,7 +917,7 @@
"sqxtunb z2.h, z17.s",
"uzp1 z2.h, z2.h, z2.h",
"splice z2.h, p6, z2.h, z1.h",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2560]",
"ld1b {z3.b}, p7/z, [x0]",
"tbl z16.b, {z2.b}, z3.b"
]
@@ -3769,7 +3769,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2408]",
"ldr x0, [x28, #2416]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3795,7 +3795,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2424]",
"ldr x0, [x28, #2432]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3821,7 +3821,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2440]",
"ldr x0, [x28, #2448]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3847,7 +3847,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2456]",
"ldr x0, [x28, #2464]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -4721,7 +4721,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2408]",
"ldr x0, [x28, #2416]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4747,7 +4747,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2424]",
"ldr x0, [x28, #2432]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4773,7 +4773,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2440]",
"ldr x0, [x28, #2448]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4799,7 +4799,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2456]",
"ldr x0, [x28, #2464]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4825,7 +4825,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2408]",
"ldr x0, [x28, #2416]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4850,7 +4850,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2424]",
"ldr x0, [x28, #2432]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4875,7 +4875,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2440]",
"ldr x0, [x28, #2448]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4900,7 +4900,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2456]",
"ldr x0, [x28, #2464]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
unittests/InstructionCountCI/VEX_map2_DOTPROD.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVEBITPERM",
"I8MM"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map2_I8MM.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM2",
"SVEBITPERM"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map2_svebitperm.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
"BinaryCacheVersion": 25
},
"Instructions": {
"pext eax, ebx, ecx": {
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