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@@ -18,18 +18,4 @@ DEF_OP(RMWHandle) {
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mov(ARMEmitter::Size::i64Bit, GetReg(Node), GetReg(IROp->Args[0]));
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}
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DEF_OP(Swap1) {
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auto Op = IROp->C<IR::IROp_Swap1>();
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auto A = GetReg(Op->A), B = GetReg(Op->B);
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LOGMAN_THROW_A_FMT(B == GetReg(Node), "Invariant");
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mov(ARMEmitter::Size::i64Bit, TMP1, A);
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mov(ARMEmitter::Size::i64Bit, A, B);
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mov(ARMEmitter::Size::i64Bit, B, TMP1);
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}
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DEF_OP(Swap2) {
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// Implemented above
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}
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} // namespace FEXCore::CPU
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@@ -352,20 +352,6 @@
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"GPR = Copy GPR:$Source": {
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"Desc": ["GPR copy, generated by RA to split live ranges"],
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"DestSize": "OpSize::i64Bit"
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},
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"GPR = Swap1 GPR:$A, GPR:$B": {
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"Desc": ["GPR swap part 1, generated by RA. Returns value of first source.",
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"Destination must be second GPR."],
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"DestSize": "OpSize::i64Bit"
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},
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"GPR = Swap2": {
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"Desc": ["GPR swap part 2, generated by RA. Returns source source.",
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"Must immediately succeed Swap1 with no intervening instructions",
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"Kludge to workaround single destination restriction on IR",
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"Hopefully temporary"],
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"DestSize": "OpSize::i64Bit"
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}
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},
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"StaticRA": {
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