diff --git a/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp b/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp
index 9627e0cd4..f51f6370b 100644
--- a/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/MoveOps.cpp
@@ -18,18 +18,4 @@ DEF_OP(RMWHandle) {
   mov(ARMEmitter::Size::i64Bit, GetReg(Node), GetReg(IROp->Args[0]));
 }
 
-DEF_OP(Swap1) {
-  auto Op = IROp->C<IR::IROp_Swap1>();
-  auto A = GetReg(Op->A), B = GetReg(Op->B);
-  LOGMAN_THROW_A_FMT(B == GetReg(Node), "Invariant");
-
-  mov(ARMEmitter::Size::i64Bit, TMP1, A);
-  mov(ARMEmitter::Size::i64Bit, A, B);
-  mov(ARMEmitter::Size::i64Bit, B, TMP1);
-}
-
-DEF_OP(Swap2) {
-  // Implemented above
-}
-
 } // namespace FEXCore::CPU
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 7f09bf4cb..be6443668 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -352,20 +352,6 @@
       "GPR = Copy GPR:$Source": {
         "Desc": ["GPR copy, generated by RA to split live ranges"],
         "DestSize": "OpSize::i64Bit"
-      },
-
-      "GPR = Swap1 GPR:$A, GPR:$B": {
-        "Desc": ["GPR swap part 1, generated by RA. Returns value of first source.",
-                 "Destination must be second GPR."],
-        "DestSize": "OpSize::i64Bit"
-      },
-
-      "GPR = Swap2": {
-        "Desc": ["GPR swap part 2, generated by RA. Returns source source.",
-                 "Must immediately succeed Swap1 with no intervening instructions",
-                 "Kludge to workaround single destination restriction on IR",
-                 "Hopefully temporary"],
-        "DestSize": "OpSize::i64Bit"
       }
     },
     "StaticRA": {