Files
FEX-Emu--FEX/External/FEXCore/Source/Interface/Core
Lioncache ec5bc9cf3e IR: Allow specifying register sizes for AES enc/dec ops
This will allow us to support operating on 256-bit vectors.

Currently only sets up the bits and pieces on the x86-64 side, since
facilities for testing the 256-bit operations on ARM isn't set up yet.
2023-02-08 16:25:19 -05:00
..
2020-03-06 09:07:37 +02:00
2023-01-18 17:56:21 -08:00
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2020-03-06 09:07:37 +02:00
2022-03-13 13:05:00 -07:00