Lioncache ec5bc9cf3e IR: Allow specifying register sizes for AES enc/dec ops ...

This will allow us to support operating on 256-bit vectors.

Currently only sets up the bits and pieces on the x86-64 side, since
facilities for testing the 256-bit operations on ARM isn't set up yet.

2023-02-08 16:25:19 -05:00

..

Config

ELFCodeLoader: Adds an option to inject libSegFault

2023-02-04 11:17:26 -08:00

Context

Core: Fixes uninitialized ParentThread variable

2023-01-07 12:09:09 -08:00

Core

IR: Allow specifying register sizes for AES enc/dec ops

2023-02-08 16:25:19 -05:00

GDBJIT

GDBSymbols: Cleanups

2022-06-27 14:44:07 +03:00

HLE/Thunks

Support 32-bit thunks ABI

2022-12-14 11:29:19 -08:00

IR

IR: Allow specifying register sizes for AES enc/dec ops

2023-02-08 16:25:19 -05:00