mirror of
https://github.com/FEX-Emu/FEX.git
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Ryan Houdek
8dbfd1635a
I keep needing to look these up to remember the limitations. Add a doc file so I can more easily point to the information.
153 lines
5.2 KiB
Markdown
153 lines
5.2 KiB
Markdown
# What is x86-TSO and what is different compared to ARM's weak memory model?
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x86's memory model is a very strictly coherent memory model that effectively mandates that all memory accesses are "atomic". While atomicity is
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actually a bit more strict, we actually need to emulate it in ARM using atomic instructions. We are also required to emulate this strictness with
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unaligned accesses, which is due to x86 CPUs allowing unaligned atomics for "free" within a cacheline. Intel also takes this a step more and allowing
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full atomics with a feature called "split-locks", AMD gains this same feature in Zen 5.
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# Emulating loads
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Due to x86 SIB addressing, this can happen on most instructions. FEX emulates these in a variety of ways depending on features.
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Most instructions are emulated with an atomic instruction but we also implement a feature called "half-barrier" atomics for unaligned atomics.
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## Base ARMv8.0
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- Addressing limitations
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- Register only
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This is emulated using an atomic load instruction plus a nop.
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- On unaligned access the code gets backpatched to a non-atomic load plus a memory barrier
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## FEAT_LRCPC
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- Addressing limitations
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- Register only
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This matches the base ARMv8.0 implementation but adds new instructions that match x86-TSO behaviour, making the emulation slightly quicker.
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- On unaligned access it still gets backpatched to non-atomic load plus a memory barrier.
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## FEAT_LRCPC2
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- Addressing limitations
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- Register plus 9-bit signed immediate (-256, 255)
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Adds some new instructions that allow immediate encoding inside of the previous LRCPC instructions
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## FEAT_LRCPC3
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Adds a handful of GPR instructions that aren't super interesting
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FEX doesn't currently implement these since no hardware supports it.
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- ldapr - Post-index load for stack
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- ldiapr - Post-index load pair for stack
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- stilp - pre-index store pair for stack
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- stlr - pre-index store for stack
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# Emulating stores
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Again due to x86 SIB addressing, this can also happen on most instructions. There are less options for FEX with this extension, so in most cases this
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just turns in to an atomic store with half-barrier backpatching for unaligned accesses
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## FEAT_LRCPC, FEAT_LRCPC2
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Adds nothing for emulating stores
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## FEAT_LRCPC3
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# Emulating atomic instructions
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x86 has atomic memory operations that can do a variety of operations. For unaligned atomic operations FEX will emulate the operation inside the signal
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handler if it happens to be unaligned.
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## CASPair - cmpxchg
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## Base ARMv8.0
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- Addressing limitations
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- Register only
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This is emulated with a ldaxp+stlxp pair of instructions.
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## FEAT_LSE
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- Addressing limitations
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- Register only
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Adds a new caspal instruction that does the operation almost exactly like x86.
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## CAS - cmpxchg8b/cmpxchg16b
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## Base ARMv8.0
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- Addressing limitations
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- Register only
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Similar to CASPair but now only uses a ldaxr+stlxr pair
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## FEAT_LSE
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- Addressing limitations
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- Register only
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Similar to CASPair adds a new casal instruction that operates basically like x86
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# AtomicFetch<Op>
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## Op from the following list
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- Add
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- Sub
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- And
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- CLR
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- Or
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- Xor
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- Neg
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- Swap
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## Base ARMv8.0
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- Addressing limitations
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- Register only
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All operations get emulated with an ldaxr+stlxr+<op> instruction
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## FEAT_LSE
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- Addressing limitations
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- Register only
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Almost all operations now have a native atomic memory operation instruction. The only outlier is atomicNeg which doesn't have an LSE equivalent and
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uses the ARMv8.0 implementation.
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# Vector loads
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Since almost all memory accesses on x86 are TSO, this includes vector operations.
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## Base ARMv8.0
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- Addressing limitations
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- Register plus 9-bit signed immediate (-256, 255)
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- Register plus 12-bit unsigned scaled immediate (Scaled by access size)
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Emulated using half-barriers, which means a load+dmb
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## FEAT_LRCPC3
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- LDAP1 added for element loads. Register only address encoding
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- LDAPUR added for vector register loads, supports 9-bit simm offset
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# Vector stores
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Just like loads, these are emulated using half-barriers
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## Base ARMv8.0
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- Addressing limitations
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- Register plus 9-bit signed immediate (-256, 255)
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- Register plus 12-bit unsigned scaled immediate (Scaled by access size)
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Emulated using half-barriers, which means a dmb+str
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## FEAT_LRCPC3
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- STL1 added for element stores. Register only address encoding
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- STLUR added for vector register stores, supports 9-bit simm offset
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# Addressing limitations depending on operating mode
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## GPR loadstores
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### TSO Emulation disabled
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- Register only (ldr/str)
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- Register + Register + scale (ldr/str)
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- Register + 9-bit simm (ldur/stru)
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- Register + 12-bit unsigned scaled imm (ldr/str)
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### TSO Emulation enabled
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- Register only (ldar/stlr)
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- Register only (ldapr/stlr) - FEAT_LRCPC
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- Register + 9-bit simm (ldapr/stlur) - FEAT_LRCPC2
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## Vector loadstores
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### TSO Emulation disabled
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- Register only (ldr/str)
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- Register + Register + scale (ldr/str)
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- Register + 9-bit simm (ldur/stru)
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- Register + 12-bit unsigned scaled imm (ldr/str)
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### TSO Emulation enabled
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- Same as TSO emulation disabled due to half-barrier implementation
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### TSO Emulation enabled (FEAT_LRCPC3)
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- Register only (ldap1/stl1) - Element loadstore
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- Register + 9-bit simm (ldapur/stlur)
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## Atomic memory operations
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Always TSO emulation enabled, always register only.
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