Alyssa Rosenzweig d7ff1b78fb IR: handle 8/16-bit AddNZCV/SubNZCV ...

we can do it more effectively than the current s/w lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-02-12 12:36:09 -04:00

..

Crypto.cpp

OpcodeDispatcher: reassociate and sink W in sha1

2024-02-02 13:03:07 -04:00

Flags.cpp

IR: handle 8/16-bit AddNZCV/SubNZCV

2024-02-12 12:36:09 -04:00

Vector.cpp

Revert "OpcodeDispatcher: Initial support for runtime long-mode switch"

2024-02-01 18:14:24 -08:00

X87.cpp

FEXCore: Moves IREmitter from the public API to backend

2023-12-25 07:00:29 -08:00

X87F64.cpp

FEXCore: Moves IREmitter from the public API to backend

2023-12-25 07:00:29 -08:00