mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-07 21:00:18 +02:00
Ryan Houdek
d19e2507e5
Due to Intel dropping support for legacy segment registers[1] there is a concern that this will break legacy 32-bit software that is doing some magic segment register handling. Adds some simple telemetry for 32-bit applications that when they encounter an instruction that sets the segment register or uses a segment register that the JIT will do a /relatively/ quick four instruction check to see if it is not a null segment. It's not enough to just check if the segment index is 0 or not, 32-bit Linux software starts with non-zero segment register indexes but the LDT for each segment index is a null-descriptor. Once the segment address is loaded, the IR operation will do a quick check against zero and if it /isn't/ zero then set the telemetry value. A very minor optimization that segment registers only get checked once per block to ensure overhead stays low. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html - 3.6 - Restricted Subset of Segmentation - `Bases are supported for FS, GS, GDT, IDT, LDT, and TSS registers; the base for CS, DS, ES, and SS is ignored for 32-bit mode, same as 64-bit mode (treated as zero).` - 4.2.17 - MOV to Segment Register - Will fault if SS is written (Breaking anything that writes to SS). - Will not fault if CS, DS, ES are written (Thus it sets the segment but gets ignored due to 3.6).
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
#include "FEXCore/Utils/AllocatorHooks.h"
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#include "Interface/Context/Context.h"
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#include "Interface/Core/Dispatcher/Dispatcher.h"
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#include <FEXCore/Core/CPUBackend.h>
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namespace FEXCore {
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namespace CPU {
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CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
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: ThreadState(ThreadState), InitialCodeSize(InitialCodeSize), MaxCodeSize(MaxCodeSize) {
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#ifndef FEX_DISABLE_TELEMETRY
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auto &Common = ThreadState->CurrentFrame->Pointers.Common;
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// Fill in telemetry values
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for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) {
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auto &Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast<FEXCore::Telemetry::TelemetryType>(i));
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Common.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(Telem.GetAddr());
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}
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#endif
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}
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CPUBackend::~CPUBackend() {
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for (auto CodeBuffer : CodeBuffers) {
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FreeCodeBuffer(CodeBuffer);
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}
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CodeBuffers.clear();
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}
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auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer * {
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if (ThreadState->CurrentFrame->SignalHandlerRefCounter == 0) {
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if (CodeBuffers.empty()) {
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auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
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EmplaceNewCodeBuffer(NewCodeBuffer);
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} else {
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if (CodeBuffers.size() > 1) {
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// If we have more than one code buffer we are tracking then walk them and delete
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// This is a cleanup step
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for (size_t i = 1; i < CodeBuffers.size(); i++) {
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FreeCodeBuffer(CodeBuffers[i]);
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}
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CodeBuffers.resize(1);
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}
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// Set the current code buffer to the initial
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CurrentCodeBuffer = &CodeBuffers[0];
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if (CurrentCodeBuffer->Size != MaxCodeSize) {
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FreeCodeBuffer(*CurrentCodeBuffer);
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// Resize the code buffer and reallocate our code size
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CurrentCodeBuffer->Size *= 1.5;
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CurrentCodeBuffer->Size = std::min(CurrentCodeBuffer->Size, MaxCodeSize);
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*CurrentCodeBuffer = AllocateNewCodeBuffer(CurrentCodeBuffer->Size);
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}
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}
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} else {
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// We have signal handlers that have generated code
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// This means that we can not safely clear the code at this point in time
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// Allocate some new code buffers that we can switch over to instead
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auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
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EmplaceNewCodeBuffer(NewCodeBuffer);
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}
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return CurrentCodeBuffer;
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}
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auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
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CodeBuffer Buffer;
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Buffer.Size = Size;
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Buffer.Ptr = static_cast<uint8_t *>(
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FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
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LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
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if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
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static_cast<Context::ContextImpl*>(ThreadState->CTX)->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
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}
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return Buffer;
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}
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void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
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FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
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}
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bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
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for (auto &Buffer: CodeBuffers) {
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auto start = (uintptr_t)Buffer.Ptr;
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auto end = start + Buffer.Size;
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if (Address >= start && Address < end) {
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return true;
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}
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}
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return false;
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}
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}
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}
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