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Ryan Houdek
d19e2507e5
Due to Intel dropping support for legacy segment registers[1] there is a concern that this will break legacy 32-bit software that is doing some magic segment register handling. Adds some simple telemetry for 32-bit applications that when they encounter an instruction that sets the segment register or uses a segment register that the JIT will do a /relatively/ quick four instruction check to see if it is not a null segment. It's not enough to just check if the segment index is 0 or not, 32-bit Linux software starts with non-zero segment register indexes but the LDT for each segment index is a null-descriptor. Once the segment address is loaded, the IR operation will do a quick check against zero and if it /isn't/ zero then set the telemetry value. A very minor optimization that segment registers only get checked once per block to ensure overhead stays low. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html - 3.6 - Restricted Subset of Segmentation - `Bases are supported for FS, GS, GDT, IDT, LDT, and TSS registers; the base for CS, DS, ES, and SS is ignored for 32-bit mode, same as 64-bit mode (treated as zero).` - 4.2.17 - MOV to Segment Register - Will fault if SS is written (Breaking anything that writes to SS). - Will not fault if CS, DS, ES are written (Thus it sets the segment but gets ignored due to 3.6).