mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
389 lines
8.7 KiB
JSON
389 lines
8.7 KiB
JSON
{
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"Features": {
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"EnabledHostFeatures": [
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP"
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],
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"BinaryCacheVersion": 12
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},
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"Instructions": {
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"Chained add": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 5,
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"x86Insts": [
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"add rax, rbx",
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"adc rcx, rcx"
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],
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"ExpectedArm64ASM": [
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"adds x4, x4, x6",
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"mov w27, #0x0",
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"adcs x26, x7, x7",
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"cfinv",
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"mov x7, x26"
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]
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},
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"Chained sub": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 4,
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"x86Insts": [
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"sub rax, rbx",
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"sbb rcx, rdx"
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],
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"ExpectedArm64ASM": [
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"subs x4, x4, x6",
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"eor x27, x7, x5",
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"sbcs x26, x7, x5",
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"mov x7, x26"
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]
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},
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"Inverted add": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 4,
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"x86Insts": [
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"add rax, rbx",
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"adc rcx, rdx",
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"cmc"
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],
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"ExpectedArm64ASM": [
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"adds x4, x4, x6",
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"eor x27, x7, x5",
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"adcs x26, x7, x5",
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"mov x7, x26"
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]
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},
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"Inverted sub": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 5,
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"x86Insts": [
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"sub rax, rbx",
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"sbb rcx, rcx",
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"cmc"
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],
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"ExpectedArm64ASM": [
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"subs x4, x4, x6",
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"mov w27, #0x0",
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"sbcs x26, x7, x7",
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"mov x7, x26",
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"cfinv"
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]
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},
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"ADC dead": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 3,
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"x86Insts": [
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"add rax, rbx",
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"adc rcx, rcx",
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"test rcx, rcx"
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],
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"ExpectedArm64ASM": [
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"adds x4, x4, x6",
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"adc x7, x7, x7",
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"subs x26, x7, #0x0 (0)"
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]
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},
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"INC consumed": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"add rax, rbx",
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"inc rax"
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],
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"ExpectedArm64ASM": [
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"adds x4, x4, x6",
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"cset x20, lo",
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"adds x26, x4, #0x1 (1)",
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"rmif x20, #63, #nzCv",
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"mov x27, x4",
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"mov x4, x26"
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]
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},
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"INC dead": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 4,
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"x86Insts": [
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"add rax, rbx",
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"inc rax",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"add x4, x4, x6",
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"add x4, x4, #0x1 (1)",
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"ands x26, x4, x5",
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"cfinv"
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]
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},
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"DEC consumed": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"sub rax, rbx",
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"dec rax"
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],
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"ExpectedArm64ASM": [
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"subs x4, x4, x6",
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"cset x20, hs",
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"subs x26, x4, #0x1 (1)",
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"rmif x20, #63, #nzCv",
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"mov x27, x4",
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"mov x4, x26"
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]
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},
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"DEC dead": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 4,
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"x86Insts": [
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"sub rax, rbx",
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"dec rax",
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"test rax, rcx"
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],
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"ExpectedArm64ASM": [
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"sub x4, x4, x6",
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"sub x4, x4, #0x1 (1)",
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"ands x26, x4, x7",
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"cfinv"
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]
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},
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"8-bit DEC consumed": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 11,
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"x86Insts": [
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"sub al, ah",
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"dec al"
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],
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"ExpectedArm64ASM": [
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"lsr w20, w4, #8",
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"lsl w0, w4, #24",
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"cmp w0, w20, lsl #24",
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"sub w20, w4, w20",
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"bfxil x4, x20, #0, #8",
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"uxtb w27, w4",
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"sub w26, w27, #0x1 (1)",
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"setf8 w26",
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"bic w20, w27, w26",
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"rmif x20, #7, #nzcV",
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"bfxil x4, x26, #0, #8"
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]
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},
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"8-bit DEC dead": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 9,
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"x86Insts": [
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"sub al, ah",
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"dec al",
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"test al, al"
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],
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"ExpectedArm64ASM": [
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"lsr w20, w4, #8",
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"sub w20, w4, w20",
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"bfxil x4, x20, #0, #8",
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"uxtb w20, w4",
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"sub w20, w20, #0x1 (1)",
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"bfxil x4, x20, #0, #8",
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"cmn wzr, w4, lsl #24",
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"cfinv",
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"mov x26, x4"
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]
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},
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"Variable shift dead": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 3,
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"x86Insts": [
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"sar rax, cl",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"asr x4, x4, x7",
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"ands x26, x4, x5",
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"cfinv"
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]
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},
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"Variable rotate-through-carry dead": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 11,
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"x86Insts": [
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"rcr rax, cl",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"and x20, x7, #0x3f",
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"cbz x20, #+0x20",
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"lsr x20, x4, x7",
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"cset x21, lo",
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"neg x22, x7",
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"lsl x23, x4, x22",
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"orr x20, x20, x23, lsl #1",
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"lsl x21, x21, x22",
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"orr x4, x20, x21",
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"ands x26, x4, x5",
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"cfinv"
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]
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},
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"Partial NZCV select (cmp)": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"cmp rax, rbx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"cmp x4, x6",
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"cset x20, eq",
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"bfxil x7, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"Partial NZCV select (add)": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"add rax, rbx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"adds x4, x4, x6",
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"cset x20, eq",
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"bfxil x7, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"AND use only ZF": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"and eax, ebx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"ands w4, w4, w6",
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"cset x20, eq",
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"bfxil x7, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"AND use only PF": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 10,
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"x86Insts": [
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"and eax, ebx",
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"setp cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"and w26, w4, w6",
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"mov x4, x26",
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"eor w0, w26, w26, lsr #4",
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"eor w0, w0, w0, lsr #2",
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"eon w20, w0, w0, lsr #1",
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"and w20, w20, #0x1",
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"bfxil x7, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"UCOMISS use only PF": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 4,
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"x86Insts": [
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"ucomiss xmm0, xmm1",
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"setnp cl",
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"test rax, rax"
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],
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"ExpectedArm64ASM": [
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"fcmp s16, s17",
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"cset x26, vc",
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"bfxil x7, x26, #0, #8",
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"subs x26, x4, #0x0 (0)"
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]
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},
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"Test use only zero - self 16-bit": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 6,
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"x86Insts": [
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"test ax, ax",
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"setz al",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"tst w4, #0xffff",
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"cset x20, eq",
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"bfxil x4, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"Test use only zero - non constant 16-bit": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 7,
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"x86Insts": [
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"test ax, bx",
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"setz al",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"and w0, w4, w6",
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"tst w0, #0xffff",
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"cset x20, eq",
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"bfxil x4, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"Test use only zero - constant 8-bit": {
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"x86InstructionCount": 3,
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"ExpectedInstructionCount": 8,
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"x86Insts": [
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"test al, 137",
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"setnz al",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"mov w20, #0x89",
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"and w0, w4, w20",
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"tst w0, #0xff",
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"cset x20, ne",
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"bfxil x4, x20, #0, #8",
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"cmn wzr, w7, lsl #24",
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"cfinv",
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"mov x26, x7"
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]
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},
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"Dead cmpxchg flags": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 10,
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"x86Insts": [
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"cmpxchg8b [rbp]",
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"test rax, rax"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"mov x21, x5",
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"caspal w20, w21, w6, w7, [x9]",
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"mrs x0, nzcv",
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"cmp w20, w4",
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"ccmp w21, w5, #nzcv, eq",
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"rmif x0, #28, #NzCV",
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"csel x4, x20, x4, ne",
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"csel x5, x21, x5, ne",
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"subs x26, x4, #0x0 (0)"
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]
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}
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}
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}
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