FEX-Emu--FEX/unittests/InstructionCountCI/Crypto/H0F3A.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "CRYPTO"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP"
    ],
    "BinaryCacheVersion": 12
  },
  "Instructions": {
    "pclmulqdq xmm0, xmm1, 00000b": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0x66 0x0f 0x3a 0x44"
      ],
      "ExpectedArm64ASM": [
        "pmull v16.1q, v16.1d, v17.1d"
      ]
    },
    "pclmulqdq xmm0, xmm1, 00001b": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x66 0x0f 0x3a 0x44"
      ],
      "ExpectedArm64ASM": [
        "dup v0.2d, v16.d[1]",
        "pmull v16.1q, v0.1d, v17.1d"
      ]
    },
    "pclmulqdq xmm0, xmm1, 10000b": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x66 0x0f 0x3a 0x44"
      ],
      "ExpectedArm64ASM": [
        "dup v0.2d, v17.d[1]",
        "pmull v16.1q, v0.1d, v16.1d"
      ]
    },
    "pclmulqdq xmm0, xmm1, 10001b": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0x66 0x0f 0x3a 0x44"
      ],
      "ExpectedArm64ASM": [
        "pmull2 v16.1q, v16.2d, v17.2d"
      ]
    },
    "aeskeygenassist xmm0, xmm1, 0": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x66 0x0f 0x3a 0xdf"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3296]",
        "movi v3.2d, #0x0",
        "mov v16.16b, v17.16b",
        "aese v16.16b, v3.16b",
        "tbl v16.16b, {v16.16b}, v2.16b"
      ]
    },
    "aeskeygenassist xmm0, xmm1, 0xFF": {
      "ExpectedInstructionCount": 8,
      "Comment": [
        "0x66 0x0f 0x3a 0xdf"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3296]",
        "movi v3.2d, #0x0",
        "mov v16.16b, v17.16b",
        "aese v16.16b, v3.16b",
        "tbl v16.16b, {v16.16b}, v2.16b",
        "mov x0, #0xff00000000",
        "dup v1.2d, x0",
        "eor v16.16b, v16.16b, v1.16b"
      ]
    },
    "sha1rnds4 xmm0, xmm1, 00b": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0x66 0x0f 0x3a 0xcc"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3712]",
        "movi v3.2d, #0x0",
        "ldr x0, [x28, #2736]",
        "ldr q4, [x0, #432]",
        "tbl v5.16b, {v16.16b}, v4.16b",
        "tbl v6.16b, {v17.16b}, v4.16b",
        "add v2.4s, v6.4s, v2.4s",
        "sha1c q5, s3, v2.4s",
        "tbl v16.16b, {v5.16b}, v4.16b"
      ]
    },
    "sha1rnds4 xmm0, xmm1, 01b": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0x66 0x0f 0x3a 0xcc"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3728]",
        "movi v3.2d, #0x0",
        "ldr x0, [x28, #2736]",
        "ldr q4, [x0, #432]",
        "tbl v5.16b, {v16.16b}, v4.16b",
        "tbl v6.16b, {v17.16b}, v4.16b",
        "add v2.4s, v6.4s, v2.4s",
        "sha1p q5, s3, v2.4s",
        "tbl v16.16b, {v5.16b}, v4.16b"
      ]
    },
    "sha1rnds4 xmm0, xmm1, 10b": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0x66 0x0f 0x3a 0xcc"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3744]",
        "movi v3.2d, #0x0",
        "ldr x0, [x28, #2736]",
        "ldr q4, [x0, #432]",
        "tbl v5.16b, {v16.16b}, v4.16b",
        "tbl v6.16b, {v17.16b}, v4.16b",
        "add v2.4s, v6.4s, v2.4s",
        "sha1m q5, s3, v2.4s",
        "tbl v16.16b, {v5.16b}, v4.16b"
      ]
    },
    "sha1rnds4 xmm0, xmm1, 11b": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0x66 0x0f 0x3a 0xcc"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3760]",
        "movi v3.2d, #0x0",
        "ldr x0, [x28, #2736]",
        "ldr q4, [x0, #432]",
        "tbl v5.16b, {v16.16b}, v4.16b",
        "tbl v6.16b, {v17.16b}, v4.16b",
        "add v2.4s, v6.4s, v2.4s",
        "sha1p q5, s3, v2.4s",
        "tbl v16.16b, {v5.16b}, v4.16b"
      ]
    }
  }
}