mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 15:00:17 +02:00
Ryan Houdek
d2c92808f5
NFC - Renames CodeBufferManager to SharedCodeBufferManager to be more explicit about it being shared between threads - Renames `CodeBuffers` to `SharedCodeBuffers` to make it more explicit about sharing these buffers between threads. - Separates the Manager to its own file so it is distinct from the rest of the CPUBackend code Makes it easier to parse ownership and lifetime semantics of these buffers.
363 lines
15 KiB
C++
363 lines
15 KiB
C++
// SPDX-License-Identifier: MIT
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#include "FEXCore/Config/Config.h"
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#include "Interface/Context/Context.h"
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#include "Interface/Core/CPUBackend.h"
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#include "Interface/Core/LookupCache.h"
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#include "Interface/Core/Dispatcher/Dispatcher.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/Utils/AllocatorHooks.h>
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#include <FEXCore/Utils/PrctlUtils.h>
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#include <cstdint>
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namespace FEXCore {
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namespace CPU {
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constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2] = {
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{0x0003'0002'0001'0000ULL, 0x0007'0006'0005'0004ULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX
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{0x000B'000A'0009'0008ULL, 0x000F'000E'000D'000CULL}, // NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER
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{0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT
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{0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
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{0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT
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{0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
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{0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT
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{0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT_UPPER
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{0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT
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{0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT_UPPER
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{0x0000'0001'0000'0000ULL, 0x0000'0003'0000'0002ULL}, // NAMED_VECTOR_MOVMSKPS_SHIFT
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{0x040B'0E01'0B0E'0104ULL, 0x0C03'0609'0306'090CULL}, // NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE
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{0x0706'0504'FFFF'FFFFULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0110B
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{0x0706'0504'0302'0100ULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0111B
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{0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1001B
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{0x0706'0504'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1011B
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{0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1101B
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{0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B
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{0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB
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{0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER
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{0x0706'0504'0302'0100ULL, 0x1716'1514'1312'1110ULL}, // NAMED_VECTOR_256_MID_ELEMENT_SWAP
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{0x0F0E'0D0C'0B0A'0908ULL, 0x1F1E'1D1C'1B1A'1918ULL}, // NAMED_VECTOR_256_MID_ELEMENT_SWAP_UPPER
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{0x8000'0000'0000'0000ULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_ONE
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{0xD49A'784B'CD1B'8AFEULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_LOG2_10
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{0xB8AA'3B29'5C17'F0BCULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_LOG2_E
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{0xC90F'DAA2'2168'C235ULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_PI
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{0x9A20'9A84'FBCF'F799ULL, 0x0000'0000'0000'3FFDULL}, // NAMED_VECTOR_X87_LOG10_2
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{0xB172'17F7'D1CF'79ACULL, 0x0000'0000'0000'3FFEULL}, // NAMED_VECTOR_X87_LOG_2
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{0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32
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{0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32_UPPER
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{0x5F00'0000'5F00'0000ULL, 0x5F00'0000'5F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I64
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{0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32
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{0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32_UPPER
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{0x43E0'0000'0000'0000ULL, 0x43E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I64
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{0x8000'0000'8000'0000ULL, 0x8000'0000'8000'0000ULL}, // NAMED_VECTOR_CVTMAX_I32
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{0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_I64
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{0x0000'0000'0000'0000ULL, 0x0000'0000'0000'8000ULL}, // NAMED_VECTOR_F80_SIGN_MASK
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{0x5A82'7999'5A82'7999ULL, 0x5A82'7999'5A82'7999ULL}, // NAMED_VECTOR_SHA1RNDS_K0
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{0x6ED9'EBA1'6ED9'EBA1ULL, 0x6ED9'EBA1'6ED9'EBA1ULL}, // NAMED_VECTOR_SHA1RNDS_K1
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{0x8F1B'BCDC'8F1B'BCDCULL, 0x8F1B'BCDC'8F1B'BCDCULL}, // NAMED_VECTOR_SHA1RNDS_K2
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{0xCA62'C1D6'CA62'C1D6ULL, 0xCA62'C1D6'CA62'C1D6ULL}, // NAMED_VECTOR_SHA1RNDS_K3
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};
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constexpr static auto PSHUFLW_LUT {[]() consteval {
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struct LUTType {
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uint64_t Val[2];
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};
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// Expectation for this LUT is to simulate PSHUFLW with ARM's TBL (single register) instruction
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// PSHUFLW behaviour:
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// 16-bit words in [63:48], [47:32], [31:16], [15:0] are selected using the 8-bit Index.
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// For 128-bit PSHUFLW, bits [127:64] are identity copied.
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constexpr uint64_t IdentityCopyUpper = 0x0f'0e'0d'0c'0b'0a'09'08;
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std::array<LUTType, 256> TotalLUT {};
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uint64_t WordSelection[4] = {
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0x01'00,
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0x03'02,
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0x05'04,
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0x07'06,
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};
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for (size_t i = 0; i < 256; ++i) {
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auto& LUT = TotalLUT[i];
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const auto Word0 = (i >> 0) & 0b11;
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const auto Word1 = (i >> 2) & 0b11;
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const auto Word2 = (i >> 4) & 0b11;
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const auto Word3 = (i >> 6) & 0b11;
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LUT.Val[0] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 16) | (WordSelection[Word2] << 32) | (WordSelection[Word3] << 48);
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LUT.Val[1] = IdentityCopyUpper;
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}
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return TotalLUT;
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}()};
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constexpr static auto PSHUFHW_LUT {[]() consteval {
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struct LUTType {
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uint64_t Val[2];
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};
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// Expectation for this LUT is to simulate PSHUFHW with ARM's TBL (single register) instruction
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// PSHUFHW behaviour:
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// 16-bit words in [127:112], [111:96], [95:80], [79:64] are selected using the 8-bit Index.
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// Incoming words come from bits [127:64] of the source.
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// Bits [63:0] are identity copied.
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constexpr uint64_t IdentityCopyLower = 0x07'06'05'04'03'02'01'00;
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std::array<LUTType, 256> TotalLUT {};
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uint64_t WordSelection[4] = {
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0x09'08,
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0x0b'0a,
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0x0d'0c,
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0x0f'0e,
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};
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for (size_t i = 0; i < 256; ++i) {
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auto& LUT = TotalLUT[i];
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const auto Word0 = (i >> 0) & 0b11;
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const auto Word1 = (i >> 2) & 0b11;
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const auto Word2 = (i >> 4) & 0b11;
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const auto Word3 = (i >> 6) & 0b11;
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LUT.Val[0] = IdentityCopyLower;
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LUT.Val[1] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 16) | (WordSelection[Word2] << 32) | (WordSelection[Word3] << 48);
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}
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return TotalLUT;
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}()};
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constexpr static auto PSHUFD_LUT {[]() consteval {
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struct LUTType {
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uint64_t Val[2];
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};
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// Expectation for this LUT is to simulate PSHUFD with ARM's TBL (single register) instruction
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// PSHUFD behaviour:
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// 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
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std::array<LUTType, 256> TotalLUT {};
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uint64_t WordSelection[4] = {
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0x03'02'01'00,
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0x07'06'05'04,
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0x0b'0a'09'08,
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0x0f'0e'0d'0c,
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};
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for (size_t i = 0; i < 256; ++i) {
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auto& LUT = TotalLUT[i];
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const auto Word0 = (i >> 0) & 0b11;
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const auto Word1 = (i >> 2) & 0b11;
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const auto Word2 = (i >> 4) & 0b11;
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const auto Word3 = (i >> 6) & 0b11;
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LUT.Val[0] = (WordSelection[Word0] << 0) | (WordSelection[Word1] << 32);
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LUT.Val[1] = (WordSelection[Word2] << 0) | (WordSelection[Word3] << 32);
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}
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return TotalLUT;
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}()};
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constexpr static auto SHUFPS_LUT {[]() consteval {
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struct LUTType {
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uint64_t Val[2];
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};
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// 32-bit words in [127:96], [95:64], [63:32], [31:0] are selected using the 8-bit Index.
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// Expectation for this LUT is to simulate SHUFPS with ARM's TBL (two register) instruction.
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// SHUFPS behaviour:
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// Two 32-bits words from each source are selected from each source in the lower and upper halves of the 128-bit destination.
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// Dest[31:0] = Src1[<Word0>]
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// Dest[63:32] = Src1[<Word1>]
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// Dest[95:64] = Src2[<Word2>]
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// Dest[127:96] = Src2[<Word3>]
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std::array<LUTType, 256> TotalLUT {};
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const uint64_t WordSelectionSrc1[4] = {
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0x03'02'01'00,
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0x07'06'05'04,
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0x0b'0a'09'08,
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0x0f'0e'0d'0c,
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};
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// Src2 needs to offset each byte index by 16-bytes to pull from the second source.
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const uint64_t WordSelectionSrc2[4] = {
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0x03'02'01'00 + (0x10101010),
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0x07'06'05'04 + (0x10101010),
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0x0b'0a'09'08 + (0x10101010),
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0x0f'0e'0d'0c + (0x10101010),
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};
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for (size_t i = 0; i < 256; ++i) {
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auto& LUT = TotalLUT[i];
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const auto Word0 = (i >> 0) & 0b11;
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const auto Word1 = (i >> 2) & 0b11;
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const auto Word2 = (i >> 4) & 0b11;
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const auto Word3 = (i >> 6) & 0b11;
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LUT.Val[0] = (WordSelectionSrc1[Word0] << 0) | (WordSelectionSrc1[Word1] << 32);
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LUT.Val[1] = (WordSelectionSrc2[Word2] << 0) | (WordSelectionSrc2[Word3] << 32);
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}
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return TotalLUT;
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}()};
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constexpr static auto DPPS_MASK {[]() consteval {
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struct LUTType {
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uint32_t Val[4];
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};
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std::array<LUTType, 16> TotalLUT {};
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for (size_t i = 0; i < TotalLUT.size(); ++i) {
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auto& LUT = TotalLUT[i];
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constexpr auto GetLUT = [](size_t i, size_t Index) {
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if (i & (1U << Index)) {
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return -1U;
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}
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return 0U;
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};
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LUT.Val[0] = GetLUT(i, 0);
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LUT.Val[1] = GetLUT(i, 1);
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LUT.Val[2] = GetLUT(i, 2);
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LUT.Val[3] = GetLUT(i, 3);
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}
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return TotalLUT;
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}()};
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constexpr static auto DPPD_MASK {[]() consteval {
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struct LUTType {
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uint64_t Val[2];
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};
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std::array<LUTType, 4> TotalLUT {};
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for (size_t i = 0; i < TotalLUT.size(); ++i) {
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auto& LUT = TotalLUT[i];
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constexpr auto GetLUT = [](size_t i, size_t Index) {
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if (i & (1U << Index)) {
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return -1ULL;
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}
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return 0ULL;
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};
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LUT.Val[0] = GetLUT(i, 0);
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LUT.Val[1] = GetLUT(i, 1);
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}
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return TotalLUT;
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}()};
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constexpr static auto PBLENDW_LUT {[]() consteval {
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struct LUTType {
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uint16_t Val[8];
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};
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// 16-bit words in [127:112], [111:96], [95:80], [79:64], [63:48], [47:32], [31:16], [15:0] are selected using 8-bit swizzle.
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// Expectation for this LUT is to simulate PBLENDW with ARM's TBX (one register) instruction.
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// PBLENDW behaviour:
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// 16-bit words from the source is moved in to the destination based on the bit in the swizzle.
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// Dest[15:0] = Swizzle[0] ? Src[15:0] : Dest[15:0]
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// Dest[31:16] = Swizzle[1] ? Src[31:16] : Dest[31:16]
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// Dest[47:32] = Swizzle[2] ? Src[47:32] : Dest[47:32]
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// Dest[63:48] = Swizzle[3] ? Src[63:48] : Dest[63:48]
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// Dest[79:64] = Swizzle[4] ? Src[79:64] : Dest[79:64]
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// Dest[95:80] = Swizzle[5] ? Src[95:80] : Dest[95:80]
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// Dest[111:96] = Swizzle[6] ? Src[111:96] : Dest[111:96]
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// Dest[127:112] = Swizzle[7] ? Src[127:112] : Dest[127:112]
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std::array<LUTType, 256> TotalLUT {};
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const uint16_t WordSelectionSrc[8] = {
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0x01'00, 0x03'02, 0x05'04, 0x07'06, 0x09'08, 0x0B'0A, 0x0D'0C, 0x0F'0E,
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};
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constexpr uint16_t OriginalDest = 0xFF'FF;
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for (size_t i = 0; i < 256; ++i) {
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auto& LUT = TotalLUT[i];
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for (size_t j = 0; j < 8; ++j) {
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LUT.Val[j] = ((i >> j) & 1) ? WordSelectionSrc[j] : OriginalDest;
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}
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}
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return TotalLUT;
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}()};
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CPUBackend::CPUBackend(SharedCodeBufferManager& SharedCodeBuffers, FEXCore::Core::InternalThreadState* ThreadState)
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: ThreadState(ThreadState)
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, SharedCodeBuffers(SharedCodeBuffers) {
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auto& Ptrs = ThreadState->CurrentFrame->Pointers;
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// Initialize named vector constants.
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for (size_t i = 0; i < FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX; ++i) {
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Ptrs.NamedVectorConstantPointers[i] = reinterpret_cast<uint64_t>(NamedVectorConstants[i]);
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}
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// Copy named vector constants.
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memcpy(Ptrs.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants));
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// Initialize Indexed named vector constants.
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] =
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reinterpret_cast<uint64_t>(PSHUFLW_LUT.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] =
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reinterpret_cast<uint64_t>(PSHUFHW_LUT.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] =
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reinterpret_cast<uint64_t>(PSHUFD_LUT.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] =
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reinterpret_cast<uint64_t>(SHUFPS_LUT.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] =
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reinterpret_cast<uint64_t>(DPPS_MASK.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] =
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reinterpret_cast<uint64_t>(DPPD_MASK.data());
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Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] =
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reinterpret_cast<uint64_t>(PBLENDW_LUT.data());
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#ifndef FEX_DISABLE_TELEMETRY
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// Fill in telemetry values
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for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) {
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auto& Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast<FEXCore::Telemetry::TelemetryType>(i));
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Ptrs.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(&Telem);
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}
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#endif
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}
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CPUBackend::~CPUBackend() = default;
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auto CPUBackend::GetEmptySharedCodeBuffer() -> CodeBuffer* {
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auto PrevCodeBuffer = CurrentCodeBuffer;
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// Resize the code buffer and reallocate our code size
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CurrentCodeBuffer = SharedCodeBuffers.StartLargerCodeBuffer();
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RegisterForSignalHandler(std::move(PrevCodeBuffer));
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return CurrentCodeBuffer.get();
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}
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void CPUBackend::RegisterForSignalHandler(fextl::shared_ptr<CodeBuffer> CodeBuffer) {
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if (ThreadState->CurrentFrame->SignalHandlerRefCounter != 0) {
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// We have signal handlers that have generated code
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// This means that we can not safely clear the code at this point in time
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// Keep a reference to the old code buffer to delay deallocation
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SignalHandlerCodeBuffers.push_back(std::move(CodeBuffer));
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} else {
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SignalHandlerCodeBuffers.clear();
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}
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}
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fextl::shared_ptr<CodeBuffer> CPUBackend::CheckCodeBufferUpdate() {
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auto NewCodeBuffer = SharedCodeBuffers.GetLatest();
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if (CurrentCodeBuffer != NewCodeBuffer) {
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RegisterForSignalHandler(CurrentCodeBuffer);
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return std::exchange(CurrentCodeBuffer, NewCodeBuffer);
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}
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return nullptr;
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}
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bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
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const auto CheckCodeBuffer = [](const CodeBuffer& Buffer, uintptr_t Address) {
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const auto BufferPtr = reinterpret_cast<uintptr_t>(Buffer.Ptr);
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// The last page of the code buffer is protected, so we need to exclude it from the valid range
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// when checking if the address is in the code buffer.
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const uintptr_t LastPageAddr = AlignDown(BufferPtr + Buffer.AllocatedSize - 1, FEXCore::Utils::FEX_PAGE_SIZE);
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return (Address >= BufferPtr && Address < LastPageAddr);
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};
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if (CheckCodeBuffer(*CurrentCodeBuffer, Address)) {
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return true;
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}
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for (const auto& Buffer : SignalHandlerCodeBuffers) {
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if (CheckCodeBuffer(*Buffer, Address)) {
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return true;
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}
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}
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return false;
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}
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} // namespace CPU
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} // namespace FEXCore
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