Alyssa Rosenzweig a01e29ac99 IR: extend the IR header with RA info ...

Beyond the actual registers allocated, there are two pieces of sideband data we
store in the RAData object:

* # of spill slots (explicitly)
* whether RA has run (implicitly by the existence of RAData)

We want to get rid of RAData, so we'll move these to the header.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2025-05-19 13:42:59 -04:00

..

Config

FEXCore: Move CPUInfo to FEX

2025-04-08 22:54:43 -07:00

Context

FEXCore: Removes unused argument on CreateThread

2025-05-05 11:17:02 -07:00

Core

IR: extend the IR header with RA info

2025-05-19 13:42:59 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

IR

IR: extend the IR header with RA info

2025-05-19 13:42:59 -04:00