LC 9b7c9f0fb6 Vector: Trim one instruction off insertq ...

We can fold a bitwise not and and pair into a bic

2026-07-09 14:58:04 -04:00

..

AVX_128.cpp

IR: Remove need to specify element size for vector bitwise ops

2026-07-09 13:26:51 -04:00

BaseTables.h

FEXCore: Revert literal optimization from #4884

2025-12-22 10:00:55 -08:00

Crypto.cpp

IR: Remove need to specify element size for vector bitwise ops

2026-07-09 13:26:51 -04:00

DDDTables.h

[SVE256] Handle SSE insertions for Float->Int/Int->Float conversions

2026-06-17 04:44:39 -04:00

Flags.cpp

FEXCore: Switch constant emission to default to NoPad

2025-12-29 11:45:51 -08:00

H0F3ATables.h

[SVE256] Ensure insertion behavior for AES operations on SSE

2026-07-03 19:35:31 -04:00

H0F38Tables.h

[SVE256] Ensure insertion behavior for AES operations on SSE

2026-07-03 19:35:31 -04:00

PrimaryGroupTables.h

OpcodeDispatcher: Implement support for CALLF/RETF

2025-08-13 16:18:12 -07:00

SecondaryGroupTables.h

OpcodeDispatcher: Make use of Bind consistently

2026-06-16 15:07:59 -04:00

SecondaryModRMTables.h

X86Tables: Move Second ModRM table to be constexpr

2025-08-27 12:24:25 -07:00

SecondaryTables.h

Vector: Move MOVQ2DQ over to Bind

2026-06-19 17:45:41 -04:00

Vector.cpp

Vector: Trim one instruction off insertq

2026-07-09 14:58:04 -04:00

VEXTables.h

FEXCore/OpcodeDispatcher: Removes tuple usage for Dispatch tables

2025-07-16 13:57:16 -07:00

X87.cpp

IR: Remove need to specify element size for vector bitwise ops

2026-07-09 13:26:51 -04:00

X87F64.cpp

Merge pull request #5448 from bylaws/claudefix6

2026-04-30 14:42:08 -07:00