Ryan Houdek db5056f275 OpcodeDispatcher: Implement shufps with VTBL2 in worst case ...

In the case that source registers are sequential then this turns in to a
load of the vector constant (2 instructions) and the single tbl
instruction.

If the registers aren't sequential then the tbl turns in to 2 moves and
then the single tbl, which with zero-cycle rename isn't too bad.

Since this is a worst case option this is significantly better than the
previous implementation doing a bunch of inserts which was always 9
instructions.
We should still strive to implement faster versions without the use of
TBL2 if possible but this makes it less of a concern.

2023-09-13 11:31:20 -07:00

..

FEXCore

OpcodeDispatcher: Implement shufps with VTBL2 in worst case

2023-09-13 11:31:20 -07:00

git_version.h.in

Move External/FEXCore/ to FEXCore/

2023-08-17 16:32:16 -04:00