FEX-Emu--FEX/unittests/InstructionCountCI/AFP/Secondary_REPNE.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "AFP"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256"
    ],
    "BinaryCacheVersion": 28
  },
  "Instructions": {
    "cvtsi2sd xmm0, eax": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x2a"
      ],
      "ExpectedArm64ASM": [
        "scvtf d16, w4"
      ]
    },
    "cvtsi2sd xmm0, dword [rax]": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0xf2 0x0f 0x2a"
      ],
      "ExpectedArm64ASM": [
        "ldr w20, [x4]",
        "scvtf d16, w20"
      ]
    },
    "cvtsi2sd xmm0, rax": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x2a"
      ],
      "ExpectedArm64ASM": [
        "scvtf d16, x4"
      ]
    },
    "cvtsi2sd xmm0, qword [rax]": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0xf2 0x0f 0x2a"
      ],
      "ExpectedArm64ASM": [
        "ldr d2, [x4]",
        "scvtf d16, d2"
      ]
    },
    "sqrtsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x51"
      ],
      "ExpectedArm64ASM": [
        "fsqrt d16, d17"
      ]
    },
    "addsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x58"
      ],
      "ExpectedArm64ASM": [
        "fadd d16, d16, d17"
      ]
    },
    "mulsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x59"
      ],
      "ExpectedArm64ASM": [
        "fmul d16, d16, d17"
      ]
    },
    "cvtsd2ss xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x5a"
      ],
      "ExpectedArm64ASM": [
        "fcvt s16, d17"
      ]
    },
    "cvtsd2ss xmm0, [rax]": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0xf2 0x0f 0x5a"
      ],
      "ExpectedArm64ASM": [
        "ldr d2, [x4]",
        "fcvt s16, d2"
      ]
    },
    "subsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x5c"
      ],
      "ExpectedArm64ASM": [
        "fsub d16, d16, d17"
      ]
    },
    "minsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x5d"
      ],
      "ExpectedArm64ASM": [
        "fmin d16, d16, d17"
      ]
    },
    "divsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x5e"
      ],
      "ExpectedArm64ASM": [
        "fdiv d16, d16, d17"
      ]
    },
    "maxsd xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x5f"
      ],
      "ExpectedArm64ASM": [
        "fmax d16, d16, d17"
      ]
    },
    "cmpsd xmm0, xmm1, 0": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmeq d16, d17, d16"
      ]
    },
    "cmpsd xmm0, xmm1, 1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmgt d16, d17, d16"
      ]
    },
    "cmpsd xmm0, xmm1, 2": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmge d16, d17, d16"
      ]
    },
    "cmpsd xmm0, xmm1, 3": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmge d0, d16, d17",
        "fcmgt d1, d17, d16",
        "orr v0.8b, v0.8b, v1.8b",
        "mvn v0.8b, v0.8b",
        "mov v16.d[0], v0.d[0]"
      ]
    },
    "cmpsd xmm0, xmm1, 4": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmeq d0, d17, d16",
        "mvn v0.8b, v0.8b",
        "mov v16.d[0], v0.d[0]"
      ]
    },
    "cmpsd xmm0, xmm1, 5": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmgt d2, d17, d16",
        "mvn v2.16b, v2.16b",
        "mov v16.d[0], v2.d[0]"
      ]
    },
    "cmpsd xmm0, xmm1, 6": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmge d2, d17, d16",
        "mvn v2.16b, v2.16b",
        "mov v16.d[0], v2.d[0]"
      ]
    },
    "cmpsd xmm0, xmm1, 7": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0xf2 0x0f 0xc2"
      ],
      "ExpectedArm64ASM": [
        "fcmge d0, d16, d17",
        "fcmgt d1, d17, d16",
        "orr v0.8b, v0.8b, v1.8b",
        "mov v16.d[0], v0.d[0]"
      ]
    }
  }
}