mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 10:00:16 +02:00
421 lines
11 KiB
JSON
421 lines
11 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"FRINTTS"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP",
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"RPRES"
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],
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"BinaryCacheVersion": 14
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},
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"Comment": [
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"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
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"This accounts for the overhead of loading and storing the registers in each instruction",
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"Could technically save some instructions by using SRA for MMX registers."
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],
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"Instructions": {
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"pi2fw mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": [
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"0x0f 0x0f 0x0c"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"uzp1 v2.4h, v2.4h, v2.4h",
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"sxtl v2.4s, v2.4h",
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"scvtf v2.2s, v2.2s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pi2fd mm0, mm1": {
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"ExpectedInstructionCount": 7,
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"Comment": [
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"0x0f 0x0f 0x0d"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"scvtf v2.2s, v2.2s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pf2iw mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": [
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"0x0f 0x0f 0x1c"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fcvtzs v2.2s, v2.2s",
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"sqxtn v2.4h, v2.4s",
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"sxtl v2.4s, v2.4h",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pf2id mm0, mm1": {
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"ExpectedInstructionCount": 7,
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"Comment": [
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"0x0f 0x0f 0x1d"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fcvtzs v2.2s, v2.2s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcpv mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": [
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"0x0f 0x0f 0x86"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fmov v0.4s, #0x70 (1.0000)",
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"fdiv v2.4s, v0.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrsqrtv mm0, mm1": {
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"ExpectedInstructionCount": 12,
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"Comment": [
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"0x0f 0x0f 0x87"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fabs v3.4s, v2.4s",
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"fmov v0.4s, #0x70 (1.0000)",
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"fsqrt v1.4s, v3.4s",
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"fdiv v3.4s, v0.4s, v1.4s",
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"movi v0.2s, #0x80, lsl #24",
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"bit v3.8b, v2.8b, v0.8b",
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"str d3, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfnacc mm0, mm1": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x0f 0x0f 0x8a",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1056]",
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"ldr d3, [x28, #1072]",
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"uzp1 v4.2s, v2.2s, v3.2s",
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"uzp2 v2.2s, v2.2s, v3.2s",
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"fsub v2.4s, v4.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfpnacc mm0, mm1": {
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"ExpectedInstructionCount": 11,
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"Comment": "0x0f 0x0f 0x8e",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1056]",
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"ldr d3, [x28, #1072]",
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"dup v4.2s, v2.s[1]",
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"fsub s2, s2, s4",
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"faddp v3.2s, v3.2s, v3.2s",
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"mov v2.s[1], v3.s[0]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfcmpge mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0x90",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fcmge v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfmin mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": "0x0f 0x0f 0x94",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fcmgt v0.4s, v2.4s, v3.4s",
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"bif v3.16b, v2.16b, v0.16b",
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"str d3, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcp mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": [
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"0x0f 0x0f 0x96"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fmov s0, #0x70 (1.0000)",
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"fdiv s2, s0, s2",
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"dup v2.2s, v2.s[0]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrsqrt mm0, mm1": {
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"ExpectedInstructionCount": 13,
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"Comment": [
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"0x0f 0x0f 0x97"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"fabs v3.4s, v2.4s",
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"fmov v0.4s, #0x70 (1.0000)",
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"fsqrt v1.4s, v3.4s",
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"fdiv v3.4s, v0.4s, v1.4s",
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"movi v0.2s, #0x80, lsl #24",
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"bit v3.8b, v2.8b, v0.8b",
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"dup v2.2s, v3.s[0]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfsub mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0x9a",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fsub v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfadd mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0x9e",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fadd v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfcmpgt mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0xa0",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fcmgt v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfmax mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": "0x0f 0x0f 0xa4",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fcmgt v0.4s, v3.4s, v2.4s",
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"bif v3.16b, v2.16b, v0.16b",
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"str d3, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcpit1 mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0x0f 0xa6",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcpit1 mm0, mm0": {
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"ExpectedInstructionCount": 0,
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"Comment": "0x0f 0x0f 0xa6",
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"ExpectedArm64ASM": []
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},
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"pfrsqit1 mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0x0f 0xa7",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrsqit1 mm0, mm0": {
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"ExpectedInstructionCount": 0,
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"Comment": "0x0f 0x0f 0xa7",
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"ExpectedArm64ASM": []
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},
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"pfsubr mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0xaa",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fsub v2.4s, v2.4s, v3.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfcmpeq mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0xb0",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fcmeq v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfmul mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0xb4",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"fmul v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcpit2 mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0x0f 0xb6",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pfrcpit2 mm0, mm0": {
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"ExpectedInstructionCount": 0,
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"Comment": "0x0f 0x0f 0xb6",
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"ExpectedArm64ASM": []
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},
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"db 0x0f, 0x0f, 0xc1, 0xb7": {
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"ExpectedInstructionCount": 11,
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"Comment": [
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"nasm doesn't support emitting this instruction",
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"pmulhrw mm0, mm1",
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"0x0f 0x0f 0xb7"
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],
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1056]",
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"ldr d3, [x28, #1072]",
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"smull v2.4s, v2.4h, v3.4h",
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"movi v3.4s, #0x80, lsl #8",
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"add v2.4s, v2.4s, v3.4s",
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"shrn v2.4h, v2.4s, #16",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pswapd mm0, mm1": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x0f 0x0f 0xbb",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"rev64 v2.2s, v2.2s",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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},
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"pavgusb mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0x0f 0xbf",
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"ExpectedArm64ASM": [
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"strb wzr, [x28, #1051]",
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"mov w20, #0xffff",
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"strb w20, [x28, #1202]",
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"ldr d2, [x28, #1072]",
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"ldr d3, [x28, #1056]",
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"urhadd v2.16b, v3.16b, v2.16b",
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"str d2, [x28, #1056]",
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"strh w20, [x28, #1064]"
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]
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}
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}
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}
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