Docs: Update for release FEX-2508.1

this provokes RA spilling and hit an assertion fail on main.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

.git-blame-ignore-revs

@@ -20,5 +20,3 @@
 # Whole-tree reformat with clang-format-19
 5267cde60e7642852d18f20ae8568643bb5293d5
 
-# Minor reformat with clang-format-19
-9fdd96af61c969cb5732471223f00eda64b7a069

.github/workflows/ccpp.yml

@@ -13,7 +13,6 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
-  FEX_PORTABLE: 1
 
 jobs:
   build_plus_test:
@@ -34,6 +33,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable
@@ -136,9 +136,6 @@ jobs:
     - name: FEXLinuxTests
       working-directory: ${{runner.workspace}}/build
       shell: bash
-      env:
-        # These tests require non-portable install due to thunks.
-        FEX_PORTABLE: 0
       run: cmake --build . --config $BUILD_TYPE --target fex_linux_tests_all
 
     - name: FEXLinuxTests Results move

.github/workflows/glibc_fault.yml

@@ -20,7 +20,6 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
-  FEX_PORTABLE: 1
 
 jobs:
   glibc_fault_test:
@@ -41,6 +40,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable

.github/workflows/hostrunner.yml

@@ -13,7 +13,6 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
-  FEX_PORTABLE: 1
 
 jobs:
   hostrunner_tests:
@@ -34,6 +33,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable

.github/workflows/instcountci.yml

@@ -33,6 +33,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable

.github/workflows/mingw_build.yml

@@ -48,6 +48,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable
@@ -77,7 +78,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTING=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTS=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
 
     - name: Build
       working-directory: ${{runner.workspace}}/build

.github/workflows/pr-code-format.yml

@@ -60,6 +60,7 @@ jobs:
           START_REV: ${{ github.event.pull_request.base.sha }}
           END_REV: ${{ github.event.pull_request.head.sha }}
           CHANGED_FILES: ${{ steps.changed-files.outputs.all_changed_files }}
+        # Using --diff_from_common_commit option available in clang-format-19
         run: |
           python ./External/code-format-helper/code-format-helper.py \
             --repo "FEX-emu/FEX" \

.github/workflows/vixl_simulator.yml

@@ -13,7 +13,6 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
-  FEX_PORTABLE: 1
 
 jobs:
   vixl_simulator:
@@ -35,6 +34,7 @@ jobs:
         echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
         echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
 
     - name: Update RootFS cache
       # Use a bash shell so we can use the same syntax for environment variable

.github/workflows/wine_dll_artifacts.yml

@@ -46,12 +46,12 @@ jobs:
     - name: Configure CMake arm64ec
       shell: bash
       working-directory: ${{runner.workspace}}/build_arm64ec
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=arm64ec-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=/usr -DBUILD_TESTING=False -DCMAKE_INSTALL_PREFIX=/usr
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=arm64ec-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=/usr -DBUILD_TESTS=False -DCMAKE_INSTALL_PREFIX=/usr
 
     - name: Configure CMake wow64
       shell: bash
       working-directory: ${{runner.workspace}}/build_wow64
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=aarch64-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=/usr -DBUILD_TESTING=False -DCMAKE_INSTALL_PREFIX=/usr
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake -DMINGW_TRIPLE=aarch64-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=/usr -DBUILD_TESTS=False -DCMAKE_INSTALL_PREFIX=/usr
 
     - name: Build arm64ec
       working-directory: ${{runner.workspace}}/build_arm64ec

.gitmodules

@@ -46,6 +46,3 @@
 [submodule "External/tracy"]
 	path = External/tracy
 	url = https://github.com/wolfpld/tracy
-[submodule "External/range-v3"]
-	path = External/range-v3
-	url = https://github.com/ericniebler/range-v3.git

CMakeLists.txt

@@ -4,6 +4,7 @@ project(FEX C CXX ASM)
 INCLUDE (CheckIncludeFiles)
 CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
 
+option(BUILD_TESTS "Build unit tests to ensure sanity" TRUE)
 option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
 option(BUILD_FEXCONFIG "Build FEXConfig" TRUE)
@@ -303,8 +304,7 @@ set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-poin
 
 include_directories(External/robin-map/include/)
 
-include(CTest)
-if (BUILD_TESTING OR ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
+if (BUILD_TESTS OR ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
   add_subdirectory(External/vixl/)
   include_directories(SYSTEM External/vixl/src/)
 endif()
@@ -335,7 +335,7 @@ endif()
 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
 
-if (BUILD_TESTING)
+if (BUILD_TESTS)
   find_package(Catch2 3 QUIET)
   if (NOT Catch2_FOUND)
     add_subdirectory(External/Catch2/)
@@ -345,9 +345,6 @@ if (BUILD_TESTING)
   endif()
 
   include(Catch)
-else ()
-  # Override any previously generated test list to avoid running stale test binaries
-  file(GENERATE OUTPUT CTestTestfile.cmake CONTENT "# No tests since BUILD_TESTING is disabled")
 endif()
 
 find_package(fmt QUIET)
@@ -357,12 +354,6 @@ if (NOT fmt_FOUND)
   add_subdirectory(External/fmt/)
 endif()
 
-find_package(range-v3 QUIET)
-if (NOT range-v3_FOUND)
-  add_subdirectory(External/range-v3/)
-  target_compile_definitions(range-v3 INTERFACE RANGES_DISABLE_DEPRECATED_WARNINGS)
-endif()
-
 add_subdirectory(External/tiny-json/)
 include_directories(External/tiny-json/)
 
@@ -458,8 +449,13 @@ endif()
 
 add_compile_options(-Wall)
 
-if (BUILD_TESTING)
+include(CTest)
+if (BUILD_TESTS)
   message(STATUS "Unit tests are enabled")
+  if (NOT BUILD_TESTING)
+    # CMake checks this variable before generating CTestTestfile.cmake
+    message(SEND_ERROR "Unit tests require BUILD_TESTING to be enabled")
+  endif()
 
   set (TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
   if (TEST_JOB_COUNT)
@@ -490,11 +486,10 @@ file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/Data/*.js
 # Any application configuration json file gets installed
 foreach(CONFIG_SRC ${CONFIG_SOURCES})
   install(FILES ${CONFIG_SRC}
-    DESTINATION ${DATA_DIRECTORY}/
-    COMPONENT Runtime)
+    DESTINATION ${DATA_DIRECTORY}/)
 endforeach()
 
-if (BUILD_TESTING)
+if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()
 
@@ -555,7 +550,6 @@ if (BUILD_THUNKS)
     WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
     )"
     DEPENDS guest-libs
-    COMPONENT Runtime
   )
 
   install(
@@ -565,7 +559,6 @@ if (BUILD_THUNKS)
     WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32
     )"
     DEPENDS guest-libs-32
-    COMPONENT Runtime
   )
 
   add_custom_target(uninstall_guest-libs
@@ -607,3 +600,46 @@ if (OVERRIDE_VERSION STREQUAL "detect")
 else()
   set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
 endif()
+
+# Parse the version here
+# Change something like `FEX-2106.1-76-<hash>` in to a list
+string(REPLACE "-" ";" DESCRIBE_LIST ${GIT_DESCRIBE_STRING})
+
+# Extract the `2106.1` element
+list(GET DESCRIBE_LIST 1 DESCRIBE_LIST)
+
+# Change `2106.1` in to a list
+string(REPLACE "." ";" DESCRIBE_LIST ${DESCRIBE_LIST})
+
+# Calculate list size
+list(LENGTH DESCRIBE_LIST LIST_SIZE)
+
+# Pull out the major version
+list(GET DESCRIBE_LIST 0 FEX_VERSION_MAJOR)
+
+# Minor version only exists if there is a .1 at the end
+# eg: 2106 versus 2106.1
+if (LIST_SIZE GREATER 1)
+  list(GET DESCRIBE_LIST 1 FEX_VERSION_MINOR)
+endif()
+
+# Package creation
+set (CPACK_GENERATOR "DEB")
+set (CPACK_PACKAGE_NAME fex-emu)
+set (CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${GIT_DESCRIBE_STRING}_${CMAKE_SYSTEM_PROCESSOR}")
+set (CPACK_PACKAGE_CONTACT "FEX-Emu Maintainers <team@fex-emu.com>")
+set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
+set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")
+set (CPACK_PACKAGE_VERSION_PATCH "${FEX_VERSION_PATCH}")
+set (CPACK_PACKAGE_DESCRIPTION_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/CPack/Description.txt")
+
+# Debian defines
+set (CPACK_DEBIAN_PACKAGE_DEPENDS "libc6, libstdc++6, libepoxy0, libsdl2-2.0-0, libegl1, libx11-6, squashfuse")
+set (CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA
+  "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/CPack/postinst;${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/CPack/prerm;${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/CPack/triggers")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  # binfmt_misc conflicts with qemu-user-static
+  # We also only install binfmt_misc on aarch64 hosts
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "${CPACK_DEBIAN_PACKAGE_CONFLICTS}, qemu-user-static")
+endif()
+include (CPack)

CodeEmitter/CodeEmitter/ALUOps.inl

@@ -36,33 +36,24 @@ public:
     DataProcessing_PCRel_Imm(Op, rd, Imm);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, const BackwardLabel* Label) {
+  void adr(ARMEmitter::Register rd, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
     LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
 
-    if (IsADRRange(Imm)) [[likely]] {
-      constexpr uint32_t Op = 0b0001'0000 << 24;
-      DataProcessing_PCRel_Imm(Op, rd, Imm);
-      return BranchEncodeSucceeded::Success;
-    }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    constexpr uint32_t Op = 0b0001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, ForwardLabel* Label) {
+  void adr(ARMEmitter::Register rd, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::ADR});
     constexpr uint32_t Op = 0b0001'0000 << 24;
     DataProcessing_PCRel_Imm(Op, rd, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
+  void adr(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return adr(rd, &Label->Backward);
+      adr(rd, &Label->Backward);
     } else {
-      return adr(rd, &Label->Forward);
+      adr(rd, &Label->Forward);
     }
   }
 
@@ -71,42 +62,32 @@ public:
     DataProcessing_PCRel_Imm(Op, rd, Imm);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, const BackwardLabel* Label) {
+  void adrp(ARMEmitter::Register rd, const BackwardLabel* Label) {
     int64_t Imm = reinterpret_cast<int64_t>(Label->Location) - (GetCursorAddress<int64_t>() & ~0xFFFLL);
     LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
 
-    if (IsADRPRange(Imm) && IsADRPAligned(Imm)) [[likely]] {
-      constexpr uint32_t Op = 0b1001'0000 << 24;
-      DataProcessing_PCRel_Imm(Op, rd, Imm);
-      return BranchEncodeSucceeded::Success;
-    }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    constexpr uint32_t Op = 0b1001'0000 << 24;
+    DataProcessing_PCRel_Imm(Op, rd, Imm);
   }
-
-  [[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, ForwardLabel* Label) {
+  void adrp(ARMEmitter::Register rd, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::ADRP});
     constexpr uint32_t Op = 0b1001'0000 << 24;
     DataProcessing_PCRel_Imm(Op, rd, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
+  void adrp(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return adrp(rd, &Label->Backward);
+      adrp(rd, &Label->Backward);
     } else {
-      return adrp(rd, &Label->Forward);
+      adrp(rd, &Label->Forward);
     }
   }
 
-  [[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, const BackwardLabel* Label) {
+  void LongAddressGen(ARMEmitter::Register rd, const BackwardLabel* Label) {
     int64_t Imm = reinterpret_cast<int64_t>(Label->Location) - (GetCursorAddress<int64_t>());
     if (IsADRRange(Imm)) {
       // If the range is in ADR range then we can just use ADR.
-      return adr(rd, Label);
+      adr(rd, Label);
     } else if (IsADRPRange(Imm)) {
       int64_t ADRPImm = (reinterpret_cast<int64_t>(Label->Location) & ~0xFFFLL) - (GetCursorAddress<int64_t>() & ~0xFFFLL);
 
@@ -121,28 +102,23 @@ public:
         // Now even an add
         add(ARMEmitter::Size::i64Bit, rd, rd, AlignedOffset);
       }
-
-      return BranchEncodeSucceeded::Success;
+    } else {
+      LOGMAN_MSG_A_FMT("Unscaled offset too large");
+      FEX_UNREACHABLE;
     }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
   }
-  [[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, ForwardLabel* Label) {
+  void LongAddressGen(ARMEmitter::Register rd, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::LONG_ADDRESS_GEN});
     // Emit a register index and a nop. These will be backpatched.
     dc32(rd.Idx());
     nop();
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
+  void LongAddressGen(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return LongAddressGen(rd, &Label->Backward);
+      LongAddressGen(rd, &Label->Backward);
     } else {
-      return LongAddressGen(rd, &Label->Forward);
+      LongAddressGen(rd, &Label->Forward);
     }
   }
 
@@ -198,7 +174,7 @@ public:
   // Logical immediate
   void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
     uint32_t n, immr, imms;
-    const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
+    [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
     LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
     and_(s, rd, rn, n, immr, imms);
   }
@@ -209,7 +185,7 @@ public:
 
   void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
     uint32_t n, immr, imms;
-    const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
+    [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
     LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
     ands(s, rd, rn, n, immr, imms);
   }
@@ -220,14 +196,14 @@ public:
 
   void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
     uint32_t n, immr, imms;
-    const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
+    [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
     LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
     orr(s, rd, rn, n, immr, imms);
   }
 
   void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
     uint32_t n, immr, imms;
-    const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
+    [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
     LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
     eor(s, rd, rn, n, immr, imms);
   }
@@ -357,7 +333,7 @@ public:
     bfi(s, rd, Reg::zr, lsb, width);
   }
   void bfxil(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
-    const auto reg_size_bits = RegSizeInBits(s);
+    [[maybe_unused]] const auto reg_size_bits = RegSizeInBits(s);
     const auto lsb_p_width = lsb + width;
 
     LOGMAN_THROW_A_FMT(width >= 1, "bfxil needs width >= 1");
@@ -886,6 +862,12 @@ public:
   }
 
 private:
+  static constexpr Condition InvertCondition(Condition cond) {
+    // These behave as always, so it makes no sense to allow inverting these.
+    LOGMAN_THROW_A_FMT(cond != Condition::CC_AL && cond != Condition::CC_NV, "Cannot invert CC_AL or CC_NV");
+    return static_cast<Condition>(FEXCore::ToUnderlying(cond) ^ 1);
+  }
+
   void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
     constexpr uint32_t Op = 0b001'0010'00 << 22;
     DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
@@ -995,7 +977,7 @@ private:
   }
 
   void xbfiz_helper(bool is_signed, ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
-    const auto lsb_p_width = lsb + width;
+    [[maybe_unused]] const auto lsb_p_width = lsb + width;
     const auto reg_size_bits = RegSizeInBits(s);
 
     LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "lsb + width ({}) must be <= {}. lsb={}, width={}", lsb_p_width, reg_size_bits, lsb, width);

CodeEmitter/CodeEmitter/ASIMDOps.inl

@@ -2244,7 +2244,8 @@ public:
 
   template<IsQOrDRegister T>
   void movi(SubRegSize size, T rd, uint64_t Imm, uint16_t Shift = 0) {
-    LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
+    LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit ||
+                        size == SubRegSize::i64Bit,
                        "Unsupported movi size");
 
     uint32_t cmode;

CodeEmitter/CodeEmitter/BranchOps.inl

@@ -20,31 +20,23 @@ public:
     constexpr uint32_t Op = 0b0101'010 << 25;
     Branch_Conditional(Op, 0, 0, Cond, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded b(ARMEmitter::Condition Cond, const BackwardLabel* Label) {
+  void b(ARMEmitter::Condition Cond, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
-    if (Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0101'010 << 25;
-      Branch_Conditional(Op, 0, 0, Cond, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+    constexpr uint32_t Op = 0b0101'010 << 25;
+    Branch_Conditional(Op, 0, 0, Cond, Imm >> 2);
   }
-  [[nodiscard]] BranchEncodeSucceeded b(ARMEmitter::Condition Cond, ForwardLabel* Label) {
+  void b(ARMEmitter::Condition Cond, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::BC});
     constexpr uint32_t Op = 0b0101'010 << 25;
     Branch_Conditional(Op, 0, 0, Cond, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded b(ARMEmitter::Condition Cond, BiDirectionalLabel* Label) {
+  void b(ARMEmitter::Condition Cond, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return b(Cond, &Label->Backward);
+      b(Cond, &Label->Backward);
     } else {
-      return b(Cond, &Label->Forward);
+      b(Cond, &Label->Forward);
     }
   }
 
@@ -53,32 +45,24 @@ public:
     constexpr uint32_t Op = 0b0101'010 << 25;
     Branch_Conditional(Op, 0, 1, Cond, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded bc(ARMEmitter::Condition Cond, const BackwardLabel* Label) {
+  void bc(ARMEmitter::Condition Cond, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
-    if (Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0101'010 << 25;
-      Branch_Conditional(Op, 0, 1, Cond, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+    constexpr uint32_t Op = 0b0101'010 << 25;
+    Branch_Conditional(Op, 0, 1, Cond, Imm >> 2);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded bc(ARMEmitter::Condition Cond, ForwardLabel* Label) {
+  void bc(ARMEmitter::Condition Cond, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::BC});
     constexpr uint32_t Op = 0b0101'010 << 25;
     Branch_Conditional(Op, 0, 1, Cond, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded bc(ARMEmitter::Condition Cond, BiDirectionalLabel* Label) {
+  void bc(ARMEmitter::Condition Cond, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return bc(Cond, &Label->Backward);
+      bc(Cond, &Label->Backward);
     } else {
-      return bc(Cond, &Label->Forward);
+      bc(Cond, &Label->Forward);
     }
   }
 
@@ -114,32 +98,25 @@ public:
 
     UnconditionalBranch(Op, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded b(const BackwardLabel* Label) {
+  void b(const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
-    if (Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0001'01 << 26;
-      UnconditionalBranch(Op, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
+    LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+    constexpr uint32_t Op = 0b0001'01 << 26;
 
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    UnconditionalBranch(Op, Imm >> 2);
   }
-  [[nodiscard]] BranchEncodeSucceeded b(ForwardLabel* Label) {
+  void b(ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::B});
     constexpr uint32_t Op = 0b0001'01 << 26;
 
     UnconditionalBranch(Op, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded b(BiDirectionalLabel* Label) {
+  void b(BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return b(&Label->Backward);
+      b(&Label->Backward);
     } else {
-      return b(&Label->Forward);
+      b(&Label->Forward);
     }
   }
 
@@ -149,33 +126,25 @@ public:
     UnconditionalBranch(Op, Imm);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded bl(const BackwardLabel* Label) {
+  void bl(const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
-    if (Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b1001'01 << 26;
-      UnconditionalBranch(Op, Imm >> 2);
+    LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+    constexpr uint32_t Op = 0b1001'01 << 26;
 
-      return BranchEncodeSucceeded::Success;
-    }
-
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    UnconditionalBranch(Op, Imm >> 2);
   }
-  [[nodiscard]] BranchEncodeSucceeded bl(ForwardLabel* Label) {
+  void bl(ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::B});
     constexpr uint32_t Op = 0b1001'01 << 26;
 
     UnconditionalBranch(Op, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded bl(BiDirectionalLabel* Label) {
+  void bl(BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return bl(&Label->Backward);
+      bl(&Label->Backward);
     } else {
-      return bl(&Label->Forward);
+      bl(&Label->Forward);
     }
   }
 
@@ -186,35 +155,28 @@ public:
     CompareAndBranch(Op, s, rt, Imm);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbz(ARMEmitter::Size s, ARMEmitter::Register rt, const BackwardLabel* Label) {
+  void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+    LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
 
-    if (Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0011'0100 << 24;
-      CompareAndBranch(Op, s, rt, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
+    constexpr uint32_t Op = 0b0011'0100 << 24;
 
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    CompareAndBranch(Op, s, rt, Imm >> 2);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbz(ARMEmitter::Size s, ARMEmitter::Register rt, ForwardLabel* Label) {
+  void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::BC});
 
     constexpr uint32_t Op = 0b0011'0100 << 24;
 
     CompareAndBranch(Op, s, rt, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel* Label) {
+  void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return cbz(s, rt, &Label->Backward);
+      cbz(s, rt, &Label->Backward);
     } else {
-      return cbz(s, rt, &Label->Forward);
+      cbz(s, rt, &Label->Forward);
     }
   }
 
@@ -224,35 +186,28 @@ public:
     CompareAndBranch(Op, s, rt, Imm);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, const BackwardLabel* Label) {
+  void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+    LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
 
-    if (Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0011'0101 << 24;
-      CompareAndBranch(Op, s, rt, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
+    constexpr uint32_t Op = 0b0011'0101 << 24;
 
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    CompareAndBranch(Op, s, rt, Imm >> 2);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, ForwardLabel* Label) {
+  void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::BC});
 
     constexpr uint32_t Op = 0b0011'0101 << 24;
 
     CompareAndBranch(Op, s, rt, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel* Label) {
+  void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return cbnz(s, rt, &Label->Backward);
+      cbnz(s, rt, &Label->Backward);
     } else {
-      return cbnz(s, rt, &Label->Forward);
+      cbnz(s, rt, &Label->Forward);
     }
   }
 
@@ -262,35 +217,28 @@ public:
 
     TestAndBranch(Op, rt, Bit, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded tbz(ARMEmitter::Register rt, uint32_t Bit, const BackwardLabel* Label) {
+  void tbz(ARMEmitter::Register rt, uint32_t Bit, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
+    LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
 
-    if (Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0011'0110 << 24;
-      TestAndBranch(Op, rt, Bit, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
+    constexpr uint32_t Op = 0b0011'0110 << 24;
 
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    TestAndBranch(Op, rt, Bit, Imm >> 2);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded tbz(ARMEmitter::Register rt, uint32_t Bit, ForwardLabel* Label) {
+  void tbz(ARMEmitter::Register rt, uint32_t Bit, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::TEST_BRANCH});
 
     constexpr uint32_t Op = 0b0011'0110 << 24;
 
     TestAndBranch(Op, rt, Bit, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded tbz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel* Label) {
+  void tbz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return tbz(rt, Bit, &Label->Backward);
+      tbz(rt, Bit, &Label->Backward);
     } else {
-      return tbz(rt, Bit, &Label->Forward);
+      tbz(rt, Bit, &Label->Forward);
     }
   }
 
@@ -299,35 +247,27 @@ public:
 
     TestAndBranch(Op, rt, Bit, Imm);
   }
-  [[nodiscard]] BranchEncodeSucceeded tbnz(ARMEmitter::Register rt, uint32_t Bit, const BackwardLabel* Label) {
+  void tbnz(ARMEmitter::Register rt, uint32_t Bit, const BackwardLabel* Label) {
     int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
     LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
 
-    if (Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0)) [[likely]] {
-      constexpr uint32_t Op = 0b0011'0111 << 24;
-      TestAndBranch(Op, rt, Bit, Imm >> 2);
-      return BranchEncodeSucceeded::Success;
-    }
+    constexpr uint32_t Op = 0b0011'0111 << 24;
 
-    // Can't encode.
-    return BranchEncodeSucceeded::Failure;
+    TestAndBranch(Op, rt, Bit, Imm >> 2);
   }
 
-  [[nodiscard]] BranchEncodeSucceeded tbnz(ARMEmitter::Register rt, uint32_t Bit, ForwardLabel* Label) {
+  void tbnz(ARMEmitter::Register rt, uint32_t Bit, ForwardLabel* Label) {
     AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::TEST_BRANCH});
     constexpr uint32_t Op = 0b0011'0111 << 24;
 
     TestAndBranch(Op, rt, Bit, 0);
-
-    // Forward label doesn't know if it can encode until Bind.
-    return BranchEncodeSucceeded::Success;
   }
 
-  [[nodiscard]] BranchEncodeSucceeded tbnz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel* Label) {
+  void tbnz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel* Label) {
     if (Label->Backward.Location) {
-      return tbnz(rt, Bit, &Label->Backward);
+      tbnz(rt, Bit, &Label->Backward);
     } else {
-      return tbnz(rt, Bit, &Label->Forward);
+      tbnz(rt, Bit, &Label->Forward);
     }
   }
 

CodeEmitter/CodeEmitter/Emitter.h

@@ -12,7 +12,6 @@
 #include <CodeEmitter/Registers.h>
 
 #include <array>
-#include <bit>
 #include <cstdint>
 #include <utility>
 #include <type_traits>
@@ -586,11 +585,6 @@ concept IsXOrWRegister = std::is_same_v<T, XRegister> || std::is_same_v<T, WRegi
 template<typename T>
 concept IsQOrDRegister = std::is_same_v<T, QRegister> || std::is_same_v<T, DRegister>;
 
-enum class BranchEncodeSucceeded {
-  Success,
-  Failure,
-};
-
 // Whether or not a given set of vector registers are sequential
 // in increasing order as far as the register file is concerned (modulo its size)
 //
@@ -643,25 +637,19 @@ public:
 
   // Bind a backward label to an address.
   // Address that is bound is the current emitter location.
-  [[nodiscard]] bool Bind(BackwardLabel* Label) {
+  void Bind(BackwardLabel* Label) {
     LOGMAN_THROW_A_FMT(Label->Location == nullptr, "Trying to bind a label twice");
     Label->Location = GetCursorAddress<uint8_t*>();
-
-    // Always binds because it is only storing a location.
-    return true;
   }
 
-  [[nodiscard]] bool Bind(const ForwardLabel::Reference* Label) {
+  void Bind(const ForwardLabel::Reference* Label) {
     uint8_t* CurrentAddress = GetCursorAddress<uint8_t*>();
     // Patch up the instructions
     switch (Label->Type) {
     case ForwardLabel::InstType::ADR: {
       uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
       int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-      if (!IsADRRange(Imm)) [[unlikely]] {
-        // Can't bind.
-        return false;
-      }
+      LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
       uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
       uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
       uint32_t Inst = *Instruction & ~InstMask;
@@ -673,12 +661,7 @@ public:
     case ForwardLabel::InstType::ADRP: {
       uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
       int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-
-      if (!(IsADRPRange(Imm) && IsADRPAligned(Imm))) [[unlikely]] {
-        // Can't bind.
-        return false;
-      }
-
+      LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
       Imm >>= 12;
       uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
       uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
@@ -688,13 +671,11 @@ public:
       *Instruction = Inst;
       break;
     }
+
     case ForwardLabel::InstType::B: {
       uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
       int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-      if (!(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0))) [[unlikely]] {
-        // Can't bind.
-        return false;
-      }
+      LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
       Imm >>= 2;
       uint32_t InstMask = 0x3FF'FFFF;
       uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
@@ -704,13 +685,11 @@ public:
 
       break;
     }
+
     case ForwardLabel::InstType::TEST_BRANCH: {
       uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
       int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-      if (!(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0))) [[unlikely]] {
-        // Can't bind.
-        return false;
-      }
+      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
       Imm >>= 2;
       uint32_t InstMask = 0x3FFF;
       uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
@@ -724,10 +703,7 @@ public:
     case ForwardLabel::InstType::RELATIVE_LOAD: {
       uint32_t* Instruction = reinterpret_cast<uint32_t*>(Label->Location);
       int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-      if (!(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0))) [[unlikely]] {
-        // Can't bind.
-        return false;
-      }
+      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
       Imm >>= 2;
       uint32_t InstMask = 0x7'FFFF;
       uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
@@ -776,41 +752,27 @@ public:
     }
     default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
     }
-
-    return true;
   }
 
   // Bind a forward label to a location.
   // This walks all the instructions in the label's vector.
   // Then backpatching all instructions that have used the label.
-  [[nodiscard]] bool Bind(ForwardLabel* Label) {
-    bool Bound = true;
+  void Bind(ForwardLabel* Label) {
     if (Label->FirstInst.Location) {
-      Bound &= Bind(&Label->FirstInst);
+      Bind(&Label->FirstInst);
     }
     for (auto& Inst : Label->Insts) {
-      Bound &= Bind(&Inst);
+      Bind(&Inst);
     }
-
-    return Bound;
   }
 
   // Bind a bidirectional location to a location.
   // Binds both forwards and backwards depending on how the label was used.
-  [[nodiscard]] bool Bind(BiDirectionalLabel* Label) {
-    bool Bound = true;
+  void Bind(BiDirectionalLabel* Label) {
     if (!Label->Backward.Location) {
-      Bound &= Bind(&Label->Backward);
+      Bind(&Label->Backward);
     }
-    Bound &= Bind(&Label->Forward);
-
-    return Bound;
-  }
-
-  static constexpr Condition InvertCondition(Condition cond) {
-    // These behave as always, so it makes no sense to allow inverting these.
-    LOGMAN_THROW_A_FMT(cond != Condition::CC_AL && cond != Condition::CC_NV, "Cannot invert CC_AL or CC_NV");
-    return static_cast<Condition>(FEXCore::ToUnderlying(cond) ^ 1);
+    Bind(&Label->Forward);
   }
 
 #include <CodeEmitter/VixlUtils.inl>

CodeEmitter/CodeEmitter/SVEOps.inl

@@ -1541,7 +1541,7 @@ public:
   void sqincp(SubRegSize size, XRegister rdn, PRegister pm) {
     SVEIncDecPredicateCountScalar(0, 1, 0b10, 0b00, size, rdn, pm);
   }
-  void sqincp(SubRegSize size, XRegister rdn, PRegister pm, WRegister wn) {
+  void sqincp(SubRegSize size, XRegister rdn, PRegister pm, [[maybe_unused]] WRegister wn) {
     LOGMAN_THROW_A_FMT(rdn.Idx() == wn.Idx(), "rdn and wn must be the same");
     SVEIncDecPredicateCountScalar(0, 1, 0b00, 0b00, size, rdn, pm);
   }
@@ -1554,7 +1554,7 @@ public:
   void sqdecp(SubRegSize size, XRegister rdn, PRegister pm) {
     SVEIncDecPredicateCountScalar(0, 1, 0b10, 0b10, size, rdn, pm);
   }
-  void sqdecp(SubRegSize size, XRegister rdn, PRegister pm, WRegister wn) {
+  void sqdecp(SubRegSize size, XRegister rdn, PRegister pm, [[maybe_unused]] WRegister wn) {
     LOGMAN_THROW_A_FMT(rdn.Idx() == wn.Idx(), "rdn and wn must be the same");
     SVEIncDecPredicateCountScalar(0, 1, 0b00, 0b10, size, rdn, pm);
   }
@@ -3296,7 +3296,7 @@ private:
     const auto log2_size_bytes = FEXCore::ilog2(size_bytes);
 
     // We can index up to 512-bit registers with dup
-    const auto max_index = (64U >> log2_size_bytes) - 1;
+    [[maybe_unused]] const auto max_index = (64U >> log2_size_bytes) - 1;
     LOGMAN_THROW_A_FMT(Index <= max_index, "dup index ({}) too large. Must be within [0, {}].", Index, max_index);
 
     // imm2:tsz make up a 7 bit wide field, with each increasing element size
@@ -3326,7 +3326,7 @@ private:
 
     uint32_t shift = 0;
     if (!is_uint8_imm) {
-      const bool is_uint16_imm = (imm >> 16) == 0;
+      [[maybe_unused]] const bool is_uint16_imm = (imm >> 16) == 0;
 
       LOGMAN_THROW_A_FMT(is_uint16_imm, "Immediate ({}) must be a 16-bit value within [256, 65280]", imm);
       LOGMAN_THROW_A_FMT((imm % 256) == 0, "Immediate ({}) must be a multiple of 256", imm);
@@ -4152,7 +4152,7 @@ private:
 
     const auto& op_data = mem_op.MetaType.ScalarVectorType;
     const bool is_scaled = op_data.scale != 0;
-    const auto msize_value = FEXCore::ToUnderlying(msize);
+    [[maybe_unused]] const auto msize_value = FEXCore::ToUnderlying(msize);
 
     LOGMAN_THROW_A_FMT(op_data.scale == 0 || op_data.scale == msize_value, "scale may only be 0 or {}", msize_value);
 
@@ -4266,7 +4266,7 @@ private:
     const auto msize_value = FEXCore::ToUnderlying(msize);
     const auto msize_bytes = 1U << msize_value;
 
-    const auto imm_limit = (32U << msize_value) - msize_bytes;
+    [[maybe_unused]] const auto imm_limit = (32U << msize_value) - msize_bytes;
     const auto imm = mem_op.MetaType.VectorImmType.Imm;
     const auto imm_to_encode = imm >> msize_value;
 
@@ -4332,8 +4332,8 @@ private:
     LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
     LOGMAN_THROW_A_FMT((imm % num_regs) == 0, "Offset must be a multiple of {}", num_regs);
 
-    const auto min_offset = -8 * num_regs;
-    const auto max_offset = 7 * num_regs;
+    [[maybe_unused]] const auto min_offset = -8 * num_regs;
+    [[maybe_unused]] const auto max_offset = 7 * num_regs;
     LOGMAN_THROW_A_FMT(imm >= min_offset && imm <= max_offset,
                        "Invalid load/store offset ({}). Offset must be a multiple of {} and be within [{}, {}]", imm, num_regs, min_offset,
                        max_offset);
@@ -4440,8 +4440,8 @@ private:
     LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
 
     const auto esize = static_cast<int>(16 << ssz);
-    const auto max_imm = (esize << 3) - esize;
-    const auto min_imm = -(max_imm + esize);
+    [[maybe_unused]] const auto max_imm = (esize << 3) - esize;
+    [[maybe_unused]] const auto min_imm = -(max_imm + esize);
 
     LOGMAN_THROW_A_FMT((imm % esize) == 0, "imm ({}) must be a multiple of {}", imm, esize);
     LOGMAN_THROW_A_FMT(imm >= min_imm && imm <= max_imm, "imm ({}) must be within [{}, {}]", imm, min_imm, max_imm);
@@ -4485,7 +4485,7 @@ private:
     const auto msize_value = FEXCore::ToUnderlying(msize);
 
     const auto data_size_bytes = 1U << msize_value;
-    const auto max_imm = (64U << msize_value) - data_size_bytes;
+    [[maybe_unused]] const auto max_imm = (64U << msize_value) - data_size_bytes;
     LOGMAN_THROW_A_FMT((imm % data_size_bytes) == 0 && imm <= max_imm, "imm must be a multiple of {} and be within [0, {}]",
                        data_size_bytes, max_imm);
 
@@ -4861,7 +4861,7 @@ private:
                        "64-bit variants may only use Zm between z0-z15");
 
     const auto Underlying = FEXCore::ToUnderlying(size);
-    const uint32_t IndexMax = (16 / (1U << Underlying)) - 1;
+    [[maybe_unused]] const uint32_t IndexMax = (16 / (1U << Underlying)) - 1;
     LOGMAN_THROW_A_FMT(index <= IndexMax, "Index must be within 0-{}", IndexMax);
 
     // Can be bit 20 or 19 depending on whether or not the element size is 64-bit.
@@ -5117,13 +5117,12 @@ private:
   requires (std::is_same_v<T, float> || std::is_same_v<T, double>)
   using FloatToEquivalentUInt = std::conditional_t<std::is_same_v<T, float>, uint32_t, uint64_t>;
 
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
   // Determines if a floating-point value is capable of being converted
   // into an 8-bit immediate. See pseudocode definition of VFPExpandImm
   // in ARM A-profile reference manual for a general overview of how this was derived.
   template<typename T>
   requires (std::is_same_v<T, float> || std::is_same_v<T, double>)
-  [[nodiscard]]
+  [[nodiscard, maybe_unused]]
   static bool IsValidFPValueForImm8(T value) {
     const uint64_t bits = FEXCore::BitCast<FloatToEquivalentUInt<T>>(value);
     const uint64_t datasize_idx = FEXCore::ilog2(sizeof(T)) - 1;
@@ -5163,13 +5162,10 @@ private:
 
     return true;
   }
-#endif
 
 protected:
   static uint32_t FP32ToImm8(float value) {
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
     LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value), "Value ({}) cannot be encoded into an 8-bit immediate", value);
-#endif
 
     const auto bits = FEXCore::BitCast<uint32_t>(value);
     const auto sign = (bits & 0x80000000) >> 24;
@@ -5180,9 +5176,7 @@ protected:
   }
 
   static uint32_t FP64ToImm8(double value) {
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
     LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value), "Value ({}) cannot be encoded into an 8-bit immediate", value);
-#endif
 
     const auto bits = FEXCore::BitCast<uint64_t>(value);
     const auto sign = (bits & 0x80000000'00000000) >> 56;
@@ -5208,7 +5202,7 @@ private:
     uint32_t shift = 0;
     if (!is_int8_imm) {
       const int32_t imm16_limit = 32768;
-      const bool is_int16_imm = -imm16_limit <= imm && imm < imm16_limit;
+      [[maybe_unused]] const bool is_int16_imm = -imm16_limit <= imm && imm < imm16_limit;
 
       LOGMAN_THROW_A_FMT(is_int16_imm, "Immediate ({}) must be a 16-bit value within [-32768, 32512]", imm);
       LOGMAN_THROW_A_FMT((imm % 256) == 0, "Immediate ({}) must be a multiple of 256", imm);

CodeEmitter/CodeEmitter/ScalarOps.inl

@@ -30,7 +30,7 @@ public:
     const uint32_t SizeImm = FEXCore::ToUnderlying(size);
     const uint32_t IndexShift = SizeImm + 1;
     const uint32_t ElementSize = 1U << SizeImm;
-    const uint32_t MaxIndex = 128U / (ElementSize * 8);
+    [[maybe_unused]] const uint32_t MaxIndex = 128U / (ElementSize * 8);
 
     LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
 
@@ -1381,7 +1381,7 @@ private:
   void ASIMDScalarXIndexedElement(uint32_t U, ScalarRegSize size, uint32_t opcode, VRegister rm, VRegister rn, VRegister rd, uint32_t index) {
     LOGMAN_THROW_A_FMT(size != ScalarRegSize::i8Bit, "Scalar size must not be 8-bit");
 
-    const auto invalid_bound = 16U >> FEXCore::ToUnderlying(size);
+    [[maybe_unused]] const auto invalid_bound = 16U >> FEXCore::ToUnderlying(size);
     LOGMAN_THROW_A_FMT(index < invalid_bound, "Index ({}) must be within [0-{}]", index, invalid_bound - 1);
 
     uint32_t Instr = 0b0101'1111'0000'0000'0000'0000'0000'0000;

CodeEmitter/CodeEmitter/VixlUtils.inl

@@ -41,6 +41,7 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
   [[maybe_unused]] constexpr auto kDRegSize = 64;
 
   constexpr auto kWRegSize = 32;
+  constexpr auto kXRegSize = 64;
 
   LOGMAN_THROW_A_FMT((width == kBRegSize) || (width == kHRegSize) || (width == kSRegSize) || (width == kDRegSize), "Unexpected imm size");
 
@@ -128,8 +129,8 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
     // Compute the repeat distance d, and set up a bitmask covering the basic
     // unit of repetition (i.e. a word with the bottom d bits set). Also, in all
     // of these cases the N bit of the output will be zero.
-    clz_a = std::countl_zero(a);
-    int clz_c = std::countl_zero(c);
+    clz_a = CountLeadingZeros(a, kXRegSize);
+    int clz_c = CountLeadingZeros(c, kXRegSize);
     d = clz_a - clz_c;
     mask = ((UINT64_C(1) << d) - 1);
     out_n = 0;
@@ -150,7 +151,7 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
       // of set bits in our word, meaning that we have the trivial case of
       // d == 64 and only one 'repetition'. Set up all the same variables as in
       // the general case above, and set the N bit in the output.
-      clz_a = std::countl_zero(a);
+      clz_a = CountLeadingZeros(a, kXRegSize);
       d = 64;
       mask = ~UINT64_C(0);
       out_n = 1;
@@ -158,7 +159,7 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
   }
 
   // If the repeat period d is not a power of two, it can't be encoded.
-  if (!std::has_single_bit(uint32_t(d))) {
+  if (!IsPowerOf2(d)) {
     return false;
   }
 
@@ -178,7 +179,7 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
   static const uint64_t multipliers[] = {
     0x0000000000000001UL, 0x0000000100000001UL, 0x0001000100010001UL, 0x0101010101010101UL, 0x1111111111111111UL, 0x5555555555555555UL,
   };
-  uint64_t multiplier = multipliers[std::countl_zero(uint64_t(d)) - 57];
+  uint64_t multiplier = multipliers[CountLeadingZeros(d, kXRegSize) - 57];
   uint64_t candidate = (b - a) * multiplier;
 
   if (value != candidate) {
@@ -193,7 +194,7 @@ static bool IsImmLogical(uint64_t value, unsigned width, unsigned* n = nullptr,
   // Count the set bits in our basic stretch. The special case of clz(0) == -1
   // makes the answer come out right for stretches that reach the very top of
   // the word (e.g. numbers like 0xffffc00000000000).
-  int clz_b = (b == 0) ? -1 : std::countl_zero(b);
+  int clz_b = (b == 0) ? -1 : CountLeadingZeros(b, kXRegSize);
   int s = clz_a - clz_b;
 
   // Decide how many bits to rotate right by, to put the low bit of that basic
@@ -284,6 +285,11 @@ INT_1_TO_63_LIST(DECLARE_IS_UINT_N)
 
 private:
 
+template<typename V>
+static inline bool IsPowerOf2(V value) {
+  return (value != 0) && ((value & (value - 1)) == 0);
+}
+
 // Some compilers dislike negating unsigned integers,
 // so we provide an equivalent.
 template<typename T>
@@ -296,4 +302,50 @@ static inline uint64_t LowestSetBit(uint64_t value) {
   return value & UnsignedNegate(value);
 }
 
+template<typename V>
+static inline int CountLeadingZeros(V value, int width = (sizeof(V) * 8)) {
+#if COMPILER_HAS_BUILTIN_CLZ
+  if (width == 32) {
+    return (value == 0) ? 32 : __builtin_clz(static_cast<unsigned>(value));
+  } else if (width == 64) {
+    return (value == 0) ? 64 : __builtin_clzll(value);
+  }
+#endif
+  return CountLeadingZerosFallBack(value, width);
+}
+
+static inline int CountLeadingZerosFallBack(uint64_t value, int width) {
+  LOGMAN_THROW_A_FMT(IsPowerOf2(width) && (width <= 64), "Invalid width");
+  if (value == 0) {
+    return width;
+  }
+  int count = 0;
+  value = value << (64 - width);
+  if ((value & UINT64_C(0xffffffff00000000)) == 0) {
+    count += 32;
+    value = value << 32;
+  }
+  if ((value & UINT64_C(0xffff000000000000)) == 0) {
+    count += 16;
+    value = value << 16;
+  }
+  if ((value & UINT64_C(0xff00000000000000)) == 0) {
+    count += 8;
+    value = value << 8;
+  }
+  if ((value & UINT64_C(0xf000000000000000)) == 0) {
+    count += 4;
+    value = value << 4;
+  }
+  if ((value & UINT64_C(0xc000000000000000)) == 0) {
+    count += 2;
+    value = value << 2;
+  }
+  if ((value & UINT64_C(0x8000000000000000)) == 0) {
+    count += 1;
+  }
+  count += (value == 0);
+  return count;
+}
+
 public:

Data/AppConfig/CMakeLists.txt

@@ -4,8 +4,7 @@ file(GLOB GEN_CONFIG_SOURCES CONFIGURE_DEPENDS *.json.in)
 # Any application configuration json file gets installed
 foreach(CONFIG_SRC ${CONFIG_SOURCES})
   install(FILES ${CONFIG_SRC}
-    DESTINATION ${DATA_DIRECTORY}/AppConfig/
-    COMPONENT Runtime)
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
 endforeach()
 
 # Any configuration file json file that needs to be generated
@@ -22,6 +21,5 @@ foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
   # Then install the configured json
   install(
     FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}
-    DESTINATION ${DATA_DIRECTORY}/AppConfig/
-    COMPONENT Runtime)
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
 endforeach()

Data/CMake/CPack/Description.txt

@@ -0,0 +1,3 @@
+x86 and x86-64 Linux emulator
+
+FEX allows you to run x86 applications on ARM64 Linux devices. It offers broad compatibility with both 32-bit and 64-bit binaries, and it can be used alongside Wine/Proton to play Windows games.

Data/CMake/CPack/postinst

@@ -0,0 +1,18 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Setup binfmt_misc
+  update-binfmts --import FEX-x86
+  update-binfmts --import FEX-x86_64
+}
+
+# Install FEXInterpreter hardlink
+# Needs to be done before setting up binfmt_misc
+ln -f /usr/bin/FEXLoader /usr/bin/FEXInterpreter
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi

Data/CMake/CPack/prerm

@@ -0,0 +1,17 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Uninstall
+  update-binfmts --unimport FEX-x86
+  update-binfmts --unimport FEX-x86_64
+}
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi
+
+# Remove FEXInterpreter hardlink
+unlink /usr/bin/FEXInterpreter

Data/CMake/CPack/triggers

@@ -0,0 +1 @@
+activate-noawait ldconfig

Data/Dockerfile

@@ -14,7 +14,7 @@ RUN mkdir build
 
 ARG CC=clang-13
 ARG CXX=clang++-13
-RUN cmake -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_BUILD_TYPE=Release -DUSE_LINKER=lld -DENABLE_LTO=True -DBUILD_TESTING=False -DENABLE_ASSERTIONS=False -G Ninja .
+RUN cmake -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_BUILD_TYPE=Release -DUSE_LINKER=lld -DENABLE_LTO=True -DBUILD_TESTS=False -DENABLE_ASSERTIONS=False -G Ninja .
 RUN ninja
 
 WORKDIR /FEX/build

Data/binfmts/CMakeLists.txt

@@ -10,8 +10,7 @@ function(GenBinFmt Name)
   # Then install the configured binfmt
   install(
     FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
-    DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/
-    COMPONENT Runtime)
+    DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
 endfunction()
 
 if (NOT USE_LEGACY_BINFMTMISC)
@@ -20,8 +19,7 @@ if (NOT USE_LEGACY_BINFMTMISC)
 
   install(
     FILES ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86.conf ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86_64.conf
-    DESTINATION ${CMAKE_INSTALL_PREFIX}/lib/binfmt.d/
-    COMPONENT Runtime)
+    DESTINATION ${CMAKE_INSTALL_PREFIX}/lib/binfmt.d/)
 else()
   GenBinFmt(FEX-x86.in)
   GenBinFmt(FEX-x86_64.in)

Data/binfmts/FEX-x86.conf.in

@@ -1 +1 @@
-:FEX-x86:M:0:\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00:\xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff:@CMAKE_INSTALL_PREFIX@/bin/FEX:POCF
+:FEX-x86:M:0:\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00:\xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff:@CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter:POCF

Data/binfmts/FEX-x86.in

@@ -1,5 +1,5 @@
 package fex
-interpreter @CMAKE_INSTALL_PREFIX@/bin/FEX
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
 magic \x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00
 offset 0
 mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff

Data/binfmts/FEX-x86_64.conf.in

@@ -1 +1 @@
-:FEX-x86_64:M:0:\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00:\xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff:@CMAKE_INSTALL_PREFIX@/bin/FEX:POCF
+:FEX-x86_64:M:0:\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00:\xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff:@CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter:POCF

Data/binfmts/FEX-x86_64.in

@@ -1,5 +1,5 @@
 package fex
-interpreter @CMAKE_INSTALL_PREFIX@/bin/FEX
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
 magic \x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00
 offset 0
 mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff

Data/nix/WineOnArm/shell.nix

@@ -45,7 +45,7 @@ pkgs.mkShell {
     fi
   '';
 
-  # E.g. cmake $FEX_CMAKE_TOOLCHAIN_ARM64EC -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTING=False
+  # E.g. cmake $FEX_CMAKE_TOOLCHAIN_ARM64EC -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTS=False
   FEX_CMAKE_TOOLCHAIN_ARM64EC = "--toolchain ${cmakeToolchainFile} -DMINGW_TRIPLE=arm64ec-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows";
   FEX_CMAKE_TOOLCHAIN_WOW64 = "--toolchain ${cmakeToolchainFile} -DMINGW_TRIPLE=aarch64-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows";
   FEX_MESON_CROSSFILE = "--cross-file ${mesonCrossFile}";

Data/nix/cmake_configure_woa32.sh

@@ -18,4 +18,4 @@ then
 fi
 
 set -o xtrace
-cmake $FEX_CMAKE_TOOLCHAIN_WOW64 -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTING=False $@
+cmake $FEX_CMAKE_TOOLCHAIN_WOW64 -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTS=False $@

Data/nix/cmake_configure_woa64.sh

@@ -18,4 +18,4 @@ then
 fi
 
 set -o xtrace
-cmake $FEX_CMAKE_TOOLCHAIN_ARM64EC -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTING=False $@
+cmake $FEX_CMAKE_TOOLCHAIN_ARM64EC -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_LTO=False -DBUILD_TESTS=False $@

Data/nix/cmake_enable_flt.sh

@@ -14,4 +14,4 @@ fi
 rm -rf unittests/FEXLinuxTests
 
 set -o xtrace
-cmake . $FEX_CMAKE_TOOLCHAINS -DBUILD_TESTING=ON -DBUILD_FEX_LINUX_TESTS=ON
+cmake . $FEX_CMAKE_TOOLCHAINS -DBUILD_TESTS=ON -DBUILD_FEX_LINUX_TESTS=ON

External/code-format-helper/code-format-helper.py

@@ -214,6 +214,7 @@ class ClangFormatHelper(FormatHelper):
             self.clang_fmt_path,
             "--binary=clang-format-19",
             "--diff",
+            "--diff_from_common_commit",
         ]
 
         if args.start_rev and args.end_rev:

FEXCore/CMakeLists.txt

@@ -78,6 +78,6 @@ install (DIRECTORY include/FEXCore ${CMAKE_BINARY_DIR}/include/FEXCore
   DESTINATION include
   COMPONENT Development)
 
-if (BUILD_TESTING)
+if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()

FEXCore/Scripts/config_generator.py

@@ -118,6 +118,41 @@ def print_man_env_option(name, desc, default, no_json_key):
     output_man.write("\\fBdefault:\\fR {0}\n".format(default))
     output_man.write(".Pp\n\n")
 
+def print_man_options(options):
+    output_man.write(".Sh OPTIONS\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+
+            default = op_vals["Default"]
+            value_type = op_vals["Type"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (value_type == "str" or value_type == "strarray" or value_type == "strenum"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_option(
+                short,
+                long,
+                op_vals["Desc"],
+                default
+            )
+            if (value_type == "strenum"):
+                Enums = op_vals["Enums"]
+                output_man.write("\\fBAvailable Options:\\fR\n")
+                output_man.write(", ".join(f"{enum_op_val}" for [_, enum_op_val] in Enums.items()))
+                output_man.write("\n.sp\n")
+
+    output_man.write(".El\n")
+
 def print_man_environment(options):
     output_man.write(".Sh ENVIRONMENT\n")
     output_man.write(".Bl -tag -width -indent\n")
@@ -159,7 +194,7 @@ def print_man_environment_tail():
     "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/",
     "This will override the full path",
     "If FEX_PORTABLE is declared then relative paths are also supported",
-    "For FEX: Relative to the FEX binary",
+    "For FEXInterpreter: Relative to the FEXInterpreter binary",
     "For WINE: Relative to %LOCALAPPDATA%"
     ],
     "''", True)
@@ -173,7 +208,7 @@ def print_man_environment_tail():
     "One must be careful with this option as it will override any applications that load with execve as well"
     "If you need to support applications that execve then use FEX_APP_CONFIG_LOCATION instead"
     "If FEX_PORTABLE is declared then relative paths are also supported",
-    "For FEX: Relative to the FEX binary",
+    "For FEXInterpreter: Relative to the FEXInterpreter binary",
     "For WINE: Relative to %LOCALAPPDATA%"
     ],
     "''", True)
@@ -192,8 +227,8 @@ def print_man_environment_tail():
     "PORTABLE",
     [
     "Allows FEX to run without installation. Global locations for configuration and binfmt_misc are ignored.",
-    "For FEX on Linux:",
-    "These files are instead read from <FEXPath>/fex-emu/ by default.",
+    "For FEXInterpreter on Linux:",
+    "These files are instead read from <FEXInterpreterPath>/fex-emu/ by default.",
     "For Arm64ec/Wow64 WINE builds:",
     "These files are instead read from $LOCALAPPDATA/fex-emu/ by default.",
     "For further customization, see FEX_APP_CONFIG_LOCATION and FEX_APP_DATA_LOCATION."
@@ -205,12 +240,20 @@ def print_man_header():
 .Dt FEX
 .Os Linux
 .Sh NAME
-.Nm FEX
+.Nm FEXLoader
+.Nm FEXInterpreter
 .Nm FEXBash
 .Nd Fast x86-64 and x86 emulation.
 .Sh SYNOPSIS
 .Nm
-.Ar <args> ...
+.Op options
+.Op Ar --
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXInterpreter
+.Ar Application
+<args> ...
 .Pp
 .Nm FEXBash
 .Ar <args> ...
@@ -318,6 +361,82 @@ def print_config_option(type, group_name, json_name, default_value, short, choic
 
     output_argloader.write("\n");
 
+def print_argloader_options(options):
+    output_argloader.write("#ifdef BEFORE_PARSE\n")
+    output_argloader.write("#undef BEFORE_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray" or op_vals["Type"] == "strenum"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = "\"" + op_vals["TextDefault"] + "\""
+
+            short = None
+            choices = None
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if ("Choices" in op_vals):
+                choices = op_vals["Choices"]
+
+            print_config_option(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default,
+                short,
+                choices,
+                op_vals["Desc"])
+
+        output_argloader.write("\n")
+    output_argloader.write("#endif\n")
+
+def print_parse_argloader_options(options):
+    output_argloader.write("#ifdef AFTER_PARSE\n")
+    output_argloader.write("#undef AFTER_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            output_argloader.write("if (Options.is_set_by_user(\"{0}\")) {{\n".format(op_key))
+
+            value_type = op_vals["Type"]
+            NeedsString = False
+            conversion_func = "fextl::fmt::format(\"{}\", "
+            if ("ArgumentHandler" in op_vals):
+                NeedsString = True
+                conversion_func = "FEXCore::Config::Handler::{0}(".format(op_vals["ArgumentHandler"])
+            if (value_type == "str"):
+                NeedsString = True
+                conversion_func = "std::move("
+            if (value_type == "bool"):
+                # boolean values need a decimal specifier. Otherwise fmt prints strings.
+                conversion_func = "fextl::fmt::format(\"{:d}\", "
+
+            if (value_type == "strenum"):
+                output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{}, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, UserValue));\n".format(op_key.upper(), op_key, op_key, op_key))
+            elif (value_type == "strarray"):
+                # these need a bit more help
+                output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
+                output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
+                output_argloader.write("\t\tAppendStrArrayValue(FEXCore::Config::ConfigOption::CONFIG_{0}, *iter);\n".format(op_key.upper()))
+                output_argloader.write("\t}\n")
+            else:
+                if (NeedsString):
+                    output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                else:
+                    output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
+
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}UserValue));\n".format(op_key.upper(), conversion_func))
+            output_argloader.write("}\n")
+
+    output_argloader.write("#endif\n")
+
+
 def print_parse_envloader_options(options):
     output_argloader.write("#ifdef ENVLOADER\n")
     output_argloader.write("#undef ENVLOADER\n")
@@ -328,13 +447,13 @@ def print_parse_envloader_options(options):
             value_type = op_vals["Type"]
             if (value_type == "strenum"):
                 output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
-                output_argloader.write("\tValue = FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View);\n".format(op_key, op_key))
+                output_argloader.write("Value = FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View);\n".format(op_key, op_key, op_key))
                 output_argloader.write("}\n")
 
             if ("ArgumentHandler" in op_vals):
                 conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
                 output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
-                output_argloader.write("\tValue = {0}(Value_View);\n".format(conversion_func))
+                output_argloader.write("Value = {0}(Value_View);\n".format(conversion_func))
                 output_argloader.write("}\n")
     output_argloader.write("#endif\n")
 
@@ -348,15 +467,15 @@ def print_parse_jsonloader_options(options):
             value_type = op_vals["Type"]
             if (value_type == "strenum"):
                 output_argloader.write("else if (KeyName == \"{0}\") {{\n".format(op_key))
-                output_argloader.write("\tSet(KeyOption, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View));\n".format(op_key, op_key))
+                output_argloader.write("\tSet(KeyOption, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View));\n".format(op_key, op_key, op_key))
                 output_argloader.write("}\n")
             elif (value_type == "strarray"):
                 output_argloader.write("else if (KeyName == \"{0}\") {{\n".format(op_key))
                 output_argloader.write("\tAppendStrArrayValue(KeyOption, ConfigString);\n")
                 output_argloader.write("}\n")
     assert op_key is not None, "No options found in JSONLOADER"
-    output_argloader.write("else {\n")
-    output_argloader.write("\tSet(KeyOption, ConfigString);\n")
+    output_argloader.write("else {{\n".format(op_key))
+    output_argloader.write("Set(KeyOption, ConfigString);\n")
     output_argloader.write("}\n")
 
     output_argloader.write("#endif\n")
@@ -398,6 +517,41 @@ def print_parse_enum_options(options):
 
     output_argloader.write("#endif\n")
 
+def check_for_duplicate_options(options):
+    short_map = []
+    long_map = []
+
+    # Spin through all the items and see if we have a duplicate option
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+            long_invert = None
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if (op_vals["Type"] == "bool"):
+                long_invert = "no-" + long
+
+            # Check for short key duplication
+            if (short != None):
+                if (short in short_map):
+                    raise Exception("Short config '{0}' for option '{1}' has duplicate entry!".format(short, op_key))
+                else:
+                    short_map.append(short)
+
+            # Check for long key duplication
+            if (long in long_map):
+                raise Exception("Long config '{0}' has duplicate entry!".format(long))
+            else:
+                long_map.append(long)
+
+            # Check for long key duplication
+            if (long_invert != None):
+                if (long_invert in long_map):
+                    raise Exception("Long config '{0}' has duplicate entry!".format(long_invert))
+                else:
+                    long_map.append(long_invert)
+
 if (len(sys.argv) < 5):
     sys.exit()
 
@@ -414,6 +568,8 @@ json_object = json.loads(json_text)
 options = json_object["Options"]
 unnamed_options = json_object["UnnamedOptions"]
 
+check_for_duplicate_options(options)
+
 # Generate config include file
 output_file = open(output_filename, "w")
 print_header()
@@ -425,6 +581,7 @@ output_file.close()
 # Generate man file
 output_man = open(output_man_page, "w")
 print_man_header()
+print_man_options(options)
 print_man_environment(options)
 print_man_tail()
 
@@ -432,6 +589,8 @@ output_man.close()
 
 # Generate argument loader code
 output_argloader = open(output_argumentloader_filename, "w")
+print_argloader_options(options);
+print_parse_argloader_options(options);
 
 # Generate environment loader code
 print_parse_envloader_options(options);

FEXCore/Scripts/json_ir_generator.py

@@ -58,7 +58,6 @@ class OpDefinition:
     JITDispatch: bool
     JITDispatchOverride: str
     TiedSource: int
-    Inline: list
     Arguments: list
     EmitValidation: list
     Desc: list
@@ -279,12 +278,6 @@ def parse_ops(ops):
             if "TiedSource" in op_val:
                 OpDef.TiedSource = op_val["TiedSource"]
 
-            # Pad Inline out to the argument count
-            OpDef.Inline = [''] * len(OpDef.Arguments)
-            if "Inline" in op_val:
-                Value = op_val["Inline"]
-                OpDef.Inline[0:len(Value)] = Value
-
             # Do some fixups of the data here
             if len(OpDef.EmitValidation) != 0:
                 for i in range(len(OpDef.EmitValidation)):
@@ -404,16 +397,16 @@ def print_ir_sizes():
     // Make sure our array maps directly to the IROps enum
     static_assert(IRSizes[IROps::OP_LAST] == -1ULL);
 
-    [[nodiscard]] inline size_t GetSize(IROps Op) { return IRSizes[Op]; }
-    [[nodiscard, gnu::const]] std::string_view const& GetName(IROps Op);
-    [[nodiscard, gnu::const]] uint8_t GetArgs(IROps Op);
-    [[nodiscard, gnu::const]] uint8_t GetRAArgs(IROps Op);
-    [[nodiscard, gnu::const]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);
-    [[nodiscard, gnu::const]] bool HasSideEffects(IROps Op);
-    [[nodiscard, gnu::const]] bool ImplicitFlagClobber(IROps Op);
-    [[nodiscard, gnu::const]] bool GetHasDest(IROps Op);
-    [[nodiscard, gnu::const]] bool LoweredX87(IROps Op);
-    [[nodiscard, gnu::const]] int8_t TiedSource(IROps Op);
+    [[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }
+    [[nodiscard, gnu::const, gnu::visibility("default")]] std::string_view const& GetName(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetRAArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool HasSideEffects(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool ImplicitFlagClobber(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool GetHasDest(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool LoweredX87(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] int8_t TiedSource(IROps Op);
 
     #undef IROP_SIZES
     #endif
@@ -595,13 +588,13 @@ def print_ir_arg_printer():
     output_file.write("#endif\n")
 
 def print_validation(op):
-    if len(op.EmitValidation) != 0:
-        output_file.write("#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")
+    if op.EmitValidation != None:
+        output_file.write("\t\t#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")
 
         for Validation in op.EmitValidation:
             Sanitized = Validation.replace("\"", "\\\"")
-            output_file.write("\t\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
-        output_file.write("#endif\n")
+            output_file.write("\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
+        output_file.write("\t\t#endif\n")
 
 # Print out IR allocator helpers
 def print_ir_allocator_helpers():
@@ -780,29 +773,9 @@ def print_ir_allocator_helpers():
                 output_file.write(") {\n")
                 output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
 
-                idx = 0
                 for arg in op.Arguments:
                     if arg.IsSSA:
-                        # Inline an immediate if we can
-                        inline = op.Inline[idx]
-                        idx += 1
-
-                        if inline != '':
-                            Sized = "Size" in [x.Name for x in op.Arguments]
-                            P = ["Size" if Sized else "OpSize::i64Bit", arg.Name]
-
-                            # A few cases need extra info plumbed.
-                            if inline == "SubtractZero":
-                                P += ["Src2"]
-                            elif inline == "Mem":
-                                P += ["OffsetType", "OffsetScale"]
-                            elif inline == "Memtso":
-                                P += ["OffsetType", "OffsetScale", "true /* TSO */"]
-                                inline = "Mem"
-
-                            output_file.write(f"\t\t{arg.Name} = Inline{inline}({', '.join(P)});\n")
-
-                        output_file.write(f"\t\t{arg.Name}->AddUse();\n")
+                        output_file.write("\t\t{}->AddUse();\n".format(arg.Name))
 
                 # Insert validation here. This is skipped for the
                 # OrderedNodeWrapper version because validation can depend on

FEXCore/Source/CMakeLists.txt

@@ -18,12 +18,14 @@ set (SRCS
   Common/JitSymbols.cpp
   Interface/Context/Context.cpp
   Interface/Core/LookupCache.cpp
-  Interface/Core/CodeCache.cpp
   Interface/Core/Core.cpp
   Interface/Core/CPUBackend.cpp
   Interface/Core/Addressing.cpp
   Interface/Core/CPUID.cpp
   Interface/Core/Frontend.cpp
+  Interface/Core/ObjectCache/JobHandling.cpp
+  Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp
+  Interface/Core/ObjectCache/ObjectCacheService.cpp
   Interface/Core/OpcodeDispatcher/AVX_128.cpp
   Interface/Core/OpcodeDispatcher/Crypto.cpp
   Interface/Core/OpcodeDispatcher/Flags.cpp
@@ -31,6 +33,7 @@ set (SRCS
   Interface/Core/OpcodeDispatcher/X87.cpp
   Interface/Core/OpcodeDispatcher/X87F64.cpp
   Interface/Core/OpcodeDispatcher.cpp
+  Interface/Core/X86Tables.cpp
   Interface/Core/X86HelperGen.cpp
   Interface/Core/ArchHelpers/Arm64Emitter.cpp
   Interface/Core/Dispatcher/Dispatcher.cpp
@@ -58,15 +61,16 @@ set (SRCS
   Interface/Core/X86Tables/VEXTables.cpp
   Interface/Core/X86Tables/X87Tables.cpp
   Interface/GDBJIT/GDBJIT.cpp
+  Interface/IR/AOTIR.cpp
   Interface/IR/IRDumper.cpp
   Interface/IR/IREmitter.cpp
   Interface/IR/PassManager.cpp
+  Interface/IR/Passes/ConstProp.cpp
   Interface/IR/Passes/IRDumperPass.cpp
   Interface/IR/Passes/IRValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/x87StackOptimizationPass.cpp
-  Utils/LongJump.cpp
   Utils/Telemetry.cpp
   Utils/Threads.cpp
   Utils/Profiler.cpp
@@ -203,7 +207,7 @@ add_custom_target(CONFIG_INC
   DEPENDS "${OUTPUT_MAN_NAME_COMPRESS}")
 
 # Install the compressed man page
-install(FILES ${OUTPUT_MAN_NAME_COMPRESS} COMPONENT Runtime DESTINATION ${MAN_DIR}/man1)
+install(FILES ${OUTPUT_MAN_NAME_COMPRESS} DESTINATION ${MAN_DIR}/man1)
 
 # Add in diagnostic colours if the option is available.
 # Ninja code generator will kill colours if this isn't here

FEXCore/Source/Common/JitSymbols.h

@@ -2,10 +2,12 @@
 #pragma once
 
 #include <FEXCore/fextl/memory.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 
 #include <chrono>
-#include <cstddef>
 #include <cstdint>
+#include <cstdio>
+#include <memory>
 #include <string_view>
 
 namespace FEXCore {

FEXCore/Source/Common/SoftFloat.h

@@ -294,11 +294,7 @@ struct FEX_PACKED X80SoftFloat {
   FCMP(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs, bool* eq, bool* lt, bool* nan) {
     *eq = extF80_eq(state, lhs, rhs);
     *lt = extF80_lt(state, lhs, rhs);
-
-    // Use IEEE 754 semantics: unordered if neither <, =, nor > is true
-    // This is more reliable than custom NaN detection
-    bool gt = !(*eq) && !(*lt) && extF80_le(state, rhs, lhs);
-    *nan = !(*eq) && !(*lt) && !gt;
+    *nan = IsNan(lhs) || IsNan(rhs);
   }
 
   FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {

FEXCore/Source/Common/StringConv.h

@@ -7,58 +7,69 @@
 #include <optional>
 
 namespace FEXCore::StrConv {
-inline bool Conv(std::string_view Value, bool* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, bool* Result) {
   *Result = std::strtoull(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, uint8_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint8_t* Result) {
   *Result = std::strtoul(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, int8_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, int8_t* Result) {
   *Result = std::strtol(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, uint16_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint16_t* Result) {
   *Result = std::strtoul(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, int16_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, int16_t* Result) {
   *Result = std::strtol(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, uint32_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint32_t* Result) {
   *Result = std::strtoul(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, int32_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, int32_t* Result) {
   *Result = std::strtol(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, uint64_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, uint64_t* Result) {
   *Result = std::strtoull(Value.data(), nullptr, 0);
   return true;
 }
 
-inline bool Conv(std::string_view Value, int64_t* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, int64_t* Result) {
   *Result = std::strtoll(Value.data(), nullptr, 0);
   return true;
 }
 
 template<typename T, typename = std::enable_if<std::is_enum<T>::value, T>>
-inline bool Conv(std::string_view Value, T* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, T* Result) {
   *Result = static_cast<T>(std::stoull(Value.data(), nullptr, 0));
   return true;
 }
 
-inline bool Conv(std::string_view Value, fextl::string* Result) {
+[[maybe_unused]]
+static bool Conv(std::string_view Value, fextl::string* Result) {
   *Result = Value;
   return true;
 }

FEXCore/Source/Common/VectorRegType.h

@@ -4,8 +4,6 @@
 #ifdef _M_X86_64
 #include <xmmintrin.h>
 #include <immintrin.h>
-#else
-#include <cstdint>
 #endif
 
 namespace FEXCore {

FEXCore/Source/Interface/Config/Config.json.in

@@ -4,6 +4,7 @@
       "Multiblock": {
         "Type": "bool",
         "Default": "true",
+        "ShortArg": "m",
         "Desc": [
           "Controls multiblock code compilation",
           "Can cause long JIT compilation times and stutter"
@@ -12,10 +13,22 @@
       "MaxInst": {
         "Type": "int32",
         "Default": "5000",
+        "ShortArg": "n",
         "Desc": [
           "Maximum number of instruction to store in a block"
         ]
       },
+      "CacheObjectCodeCompilation": {
+        "Type": "uint32",
+        "Default": "FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE",
+        "TextDefault": "none",
+        "Choices": [ "none", "read", "readwrite" ],
+        "ArgumentHandler": "CacheObjectCodeHandler",
+        "Desc": [
+          "Cache JIT object code to drive.",
+          "Allows JIT code to be shared between applications"
+        ]
+      },
       "HostFeatures": {
         "Type": "strenum",
         "Default": "FEXCore::Config::HostFeatures::OFF",
@@ -57,9 +70,7 @@
           "ENABLEPRESERVEALLABI": "enablepreserveallabi",
           "DISABLEPRESERVEALLABI": "disablepreserveallabi",
           "ENABLEWFXT": "enablewfxt",
-          "DISABLEWFXT": "disablewfxt",
-          "ENABLE3DNOW": "enable3dnow",
-          "DISABLE3DNOW": "disable3dnow"
+          "DISABLEWFXT": "disablewfxt"
         },
         "Desc": [
           "Allows controlling of the CPU features in the JIT.",
@@ -81,8 +92,7 @@
           "\t{enable,disable}rpres: Will force enable or disable rpres even if the host doesn't support it",
           "\t{enable,disable}svebitperm: Will force enable or disable svebitperm even if the host doesn't support it",
           "\t{enable,disable}preserveallabi: Will force enable or disable preserve_all abi even if the host doesn't support it",
-          "\t{enable,disable}wfxt: Will force enable or disable wfxt even if the host doesn't support it",
-          "\t{enable,disable}3dnow: Will force enable or disable 3DNow even if the host doesn't support it"
+          "\t{enable,disable}wfxt: Will force enable or disable wfxt even if the host doesn't support it"
         ]
       },
       "SmallTSCScale": {
@@ -97,6 +107,7 @@
       "RootFS": {
         "Type": "str",
         "Default": "",
+        "ShortArg": "R",
         "Desc": [
           "Which Root filesystem prefix to use",
           "This can be a filesystem path",
@@ -111,6 +122,7 @@
       "ThunkHostLibs": {
         "Type": "str",
         "Default": "@CMAKE_INSTALL_FULL_LIBDIR@/fex-emu/HostThunks",
+        "ShortArg": "t",
         "Desc": [
           "Folder to find the host-side thunking libraries."
         ]
@@ -118,6 +130,7 @@
       "ThunkGuestLibs": {
         "Type": "str",
         "Default": "@CMAKE_INSTALL_PREFIX@/share/fex-emu/GuestThunks",
+        "ShortArg": "j",
         "Desc": [
           "Folder to find the guest-side thunking libraries."
         ]
@@ -125,6 +138,7 @@
       "ThunkConfig": {
         "Type": "str",
         "Default": "",
+        "ShortArg": "k",
         "Desc": [
           "A json file specifying where to overlay the thunks.",
           "This can be a filesystem path",
@@ -139,6 +153,7 @@
       "Env": {
         "Type": "strarray",
         "Default": "",
+        "ShortArg": "E",
         "Desc": [
           "Adds an environment variable to the emulated environment."
         ]
@@ -146,6 +161,7 @@
       "HostEnv": {
         "Type": "strarray",
         "Default": "",
+        "ShortArg": "H",
         "Desc": [
           "Adds an environment variable to the host environment.",
           "This can be useful for setting environment variables that thunks can pick up.",
@@ -164,6 +180,7 @@
       "SingleStep": {
         "Type": "bool",
         "Default": "false",
+        "ShortArg": "S",
         "Desc": [
           "Single stepping configuration."
         ]
@@ -171,6 +188,7 @@
       "GdbServer": {
         "Type": "bool",
         "Default": "false",
+        "ShortArg": "G",
         "Desc": [
           "Enables the GDB server."
         ]
@@ -204,6 +222,7 @@
       "DumpGPRs": {
         "Type": "bool",
         "Default": "false",
+        "ShortArg": "g",
         "Desc": [
           "When the test harness ends, print the GPR state."
         ]
@@ -211,6 +230,7 @@
       "O0": {
         "Type": "bool",
         "Default": "false",
+        "ShortArg": "O0",
         "Desc": [
           "Disables optimizations passes for debugging."
         ]
@@ -300,6 +320,7 @@
       "SilentLog": {
         "Type": "bool",
         "Default": "true",
+        "ShortArg": "s",
         "Desc": [
           "Disables logging"
         ]
@@ -307,6 +328,7 @@
       "OutputLog": {
         "Type": "str",
         "Default": "server",
+        "ShortArg": "o",
         "Desc": [
           "File to write FEX output to.",
           "[stdout, stderr, server, <Filename>]"
@@ -327,13 +349,6 @@
           "Enables FEX's low-overhead sampling profile statistics.",
           "Requires a supported version of Mangohud to see the results"
         ]
-      },
-      "TraceProfiler": {
-        "Type": "bool",
-        "Default": "false",
-        "Desc": [
-          "Enables FEX's trace profiler. Using gpuvis or tracy"
-        ]
       }
     },
     "Hacks": {
@@ -388,6 +403,14 @@
           "This is required to ensure a split-lock doesn't tear inside the process"
         ]
       },
+      "TSOAutoMigration": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Automatically enables TSO when shared memory is used.",
+          "Should work without issues in most cases."
+        ]
+      },
       "VolatileMetadata": {
         "Type": "bool",
         "Default": "true",
@@ -450,16 +473,32 @@
         "Desc": [
           "Contrains the startup sleep to only apply to processes that match this name."
         ]
-      },
-      "MonoHacks": {
-        "Type": "bool",
-        "Default": "true",
-        "Desc": [
-          "Permits a hook-based SMC approach and smaller JIT blocks when mono is detected."
-        ]
       }
     },
     "Misc": {
+      "AOTIRCapture": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Captures IR and generates an AOT IR cache.",
+          "Captures both the loaded executable and libraries it loads."
+        ]
+      },
+      "AOTIRGenerate": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Scans file for executable code and generates an AOT IR cache.",
+          "Does not run the executable."
+        ]
+      },
+      "AOTIRLoad": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Loads an AOT IR cache for the loaded executable."
+        ]
+      },
       "ServerSocketPath": {
         "Type": "str",
         "Default": "",
@@ -473,32 +512,15 @@
         "Desc": [
           "Disables inline syscalls in order to support seccomp handling"
         ]
-      },
-      "ExtendedVolatileMetadata": {
-        "Type": "str",
-        "Default": "",
-        "Desc": [
-          "Configuration provided volatile metadata. Only implemented for WoW64/arm64ec.",
-          "Limited in its use but can be handy.",
-          "Extends on top of what Microsoft has for volatile metadata, but also supported for WoW64.",
-          "Colon delimited modules, then semi-colon delimited instructions, then comma delimited ranges",
-          "Default disables TSO in the module, unless instructions overlap the range",
-          "<module>;<offset begin>-<offset-end>,...;<instruction offset to force TSO>,...:<another>",
-          "examples:",
-          "  * Disable TSO for a full module: Just provide the module name:",
-          "      `hl2_linux`",
-          "  * Disable TSO for a part of the module:",
-          "      `hl2_linux;<offset begin>-<offset-end>`",
-          "  * Disable TSO for a part of the module, but enable TSO for some instructions within the module",
-          "      `hl2_linux;<offset begin>-<offset-end>;<instruction offset>,<instruction offset>`",
-          "  * Disable TSO for multiple modules",
-          "      `hl2_linux:libsdl2.so`"
-        ]
       }
     }
   },
   "UnnamedOptions": {
     "Misc": {
+      "IS_INTERPRETER": {
+        "Type": "bool",
+        "Default": "false"
+      },
       "INTERPRETER_INSTALLED": {
         "Type": "bool",
         "Default": "false"

FEXCore/Source/Interface/Context/Context.cpp

@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: MIT
 #include "Interface/Context/Context.h"
 #include "Interface/Core/OpcodeDispatcher.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/CoreState.h>
@@ -9,12 +8,18 @@
 #include <FEXCore/Core/CPUID.h>
 #include <FEXCore/Core/HostFeatures.h>
 #include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-
 #include <FEXCore/Core/Thunks.h>
 #include "FEXCore/Debug/InternalThreadState.h"
 
+#include <string.h>
+#include <utility>
+
 namespace FEXCore::Context {
+void InitializeStaticTables(OperatingMode Mode) {
+  X86Tables::InitializeInfoTables(Mode);
+  IR::InstallOpcodeHandlers(Mode);
+}
+
 fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext(const FEXCore::HostFeatures& Features) {
   return fextl::make_unique<FEXCore::Context::ContextImpl>(Features);
 }

FEXCore/Source/Interface/Context/Context.h

@@ -2,49 +2,61 @@
 #pragma once
 
 #include "Common/JitSymbols.h"
-#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/X86HelperGen.h"
-#include <Interface/IR/IntrusiveIRList.h>
+#include "Interface/Core/ObjectCache/ObjectCacheService.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/IR/AOTIR.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/HostFeatures.h>
+#include <FEXCore/Core/SignalDelegator.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/SignalScopeGuards.h>
 #include <FEXCore/fextl/memory.h>
 #include <FEXCore/fextl/set.h>
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/unordered_map.h>
 #include <FEXCore/fextl/vector.h>
+#include <FEXHeaderUtils/Syscalls.h>
+#include <stdint.h>
 
 #include <atomic>
-#include <cstddef>
-#include <cstdint>
 #include <mutex>
-#include <optional>
 #include <shared_mutex>
 
 namespace FEXCore {
-class SignalDelegator;
+class CodeLoader;
 class ThunkHandler;
 
-namespace Core {
-  struct DebugData;
-  struct InternalThreadState;
-} // namespace Core
+namespace CodeSerialize {
+  class CodeObjectSerializeService;
+}
 
 namespace CPU {
+  class Arm64JITCore;
   class Dispatcher;
 } // namespace CPU
-
 namespace HLE {
-  class SourcecodeResolver;
+  struct SyscallArguments;
   class SyscallHandler;
+  class SourcecodeResolver;
+  struct SourcecodeMap;
 } // namespace HLE
 } // namespace FEXCore
 
+namespace FEXCore::IR {
+struct IRListCopy;
+class IRListView;
+namespace Validation {
+  class IRValidation;
+}
+} // namespace FEXCore::IR
+
 namespace FEXCore::Context {
 struct FEX_PACKED ExitFunctionLinkData {
   uint64_t HostCode;
@@ -64,23 +76,7 @@ struct CustomIRResult {
 using BlockDelinkerFunc = void (*)(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record);
 constexpr uint32_t TSC_SCALE_MAXIMUM = 1'000'000'000; ///< 1Ghz
 
-class CodeCache : public AbstractCodeCache {
-public:
-  CodeCache(ContextImpl&);
-  ~CodeCache();
-
-  ContextImpl& CTX;
-  bool IsGeneratingCache = false;
-
-  void LoadData(Core::InternalThreadState&, std::byte* MappedCacheFile, const ExecutableFileSectionInfo&) override;
-  bool SaveData(Core::InternalThreadState&, int TargetFD, const ExecutableFileSectionInfo&, uint64_t SerializedBaseAddress) override;
-
-  void InitiateCacheGeneration() override {
-    IsGeneratingCache = true;
-  }
-};
-
-class ContextImpl final : public FEXCore::Context::Context, public CPU::CodeBufferManager {
+class ContextImpl final : public FEXCore::Context::Context, CPU::CodeBufferManager {
 public:
   // Context base class implementation.
   bool InitCore() override;
@@ -94,7 +90,6 @@ public:
 
   bool IsAddressInCurrentBlock(FEXCore::Core::InternalThreadState* Thread, uint64_t Address, uint64_t Size) override;
   bool IsCurrentBlockSingleInst(FEXCore::Core::InternalThreadState* Thread) override;
-  uint64_t GetGuestBlockEntry(FEXCore::Core::InternalThreadState* Thread) override;
 
   uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState* Thread, uint64_t HostPC) override;
   uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, bool WasInJIT, const uint64_t* HostGPRs, uint64_t PSTATE) override;
@@ -150,8 +145,24 @@ public:
   FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) override;
   FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) override;
 
-  CodeCache& GetCodeCache() override {
-    return CodeCache;
+  FEXCore::IR::AOTIRCacheEntry* LoadAOTIRCacheEntry(const fextl::string& Name) override;
+  void UnloadAOTIRCacheEntry(FEXCore::IR::AOTIRCacheEntry* Entry) override;
+
+  void SetAOTIRLoader(AOTIRLoaderCBFn CacheReader) override {
+    IRCaptureCache.SetAOTIRLoader(std::move(CacheReader));
+  }
+  void SetAOTIRWriter(AOTIRWriterCBFn CacheWriter) override {
+    IRCaptureCache.SetAOTIRWriter(std::move(CacheWriter));
+  }
+  void SetAOTIRRenamer(AOTIRRenamerCBFn CacheRenamer) override {
+    IRCaptureCache.SetAOTIRRenamer(std::move(CacheRenamer));
+  }
+
+  void FinalizeAOTIRCache() override {
+    IRCaptureCache.FinalizeAOTIRCache();
+  }
+  void WriteFilesWithCode(AOTIRCodeFileWriterFn Writer) override {
+    IRCaptureCache.WriteFilesWithCode(Writer);
   }
 
   void OnCodeBufferAllocated(CPU::CodeBuffer&) override;
@@ -162,6 +173,8 @@ public:
     return CodeInvalidationMutex;
   }
 
+  void MarkMemoryShared(FEXCore::Core::InternalThreadState* Thread) override;
+
   void ConfigureAOTGen(FEXCore::Core::InternalThreadState* Thread, fextl::set<uint64_t>* ExternalBranches, uint64_t SectionMaxAddress) override;
 
   bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState* Thread, uintptr_t Address) const override;
@@ -176,13 +189,14 @@ public:
 
   void RemoveForceTSOInformation(uint64_t Address, uint64_t Size) override;
 
-  void MarkMonoDetected() override {
-    MonoDetected = true;
-  }
-
-  void MarkMonoBackpatcherBlock(uint64_t BlockEntry) override;
-
 public:
+  friend class FEXCore::HLE::SyscallHandler;
+#ifdef JIT_ARM64
+  friend class FEXCore::CPU::Arm64JITCore;
+#endif
+
+  friend class FEXCore::IR::Validation::IRValidation;
+
   struct {
     uint64_t VirtualMemSize {1ULL << 36};
     uint64_t TSCScale = 0;
@@ -195,9 +209,13 @@ public:
     FEX_CONFIG_OPT(GdbServer, GDBSERVER);
     FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
     FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
+    FEX_CONFIG_OPT(TSOAutoMigration, TSOAUTOMIGRATION);
     FEX_CONFIG_OPT(VectorTSOEnabled, VECTORTSOENABLED);
     FEX_CONFIG_OPT(MemcpySetTSOEnabled, MEMCPYSETTSOENABLED);
     FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
+    FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
+    FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
+    FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
     FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
     FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
     FEX_CONFIG_OPT(RootFSPath, ROOTFS);
@@ -206,12 +224,12 @@ public:
     FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
     FEX_CONFIG_OPT(GDBSymbols, GDBSYMBOLS);
     FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+    FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
     FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
     FEX_CONFIG_OPT(DisableTelemetry, DISABLETELEMETRY);
     FEX_CONFIG_OPT(DisableVixlIndirectCalls, DISABLE_VIXL_INDIRECT_RUNTIME_CALLS);
     FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
     FEX_CONFIG_OPT(StrictInProcessSplitLocks, STRICTINPROCESSSPLITLOCKS);
-    FEX_CONFIG_OPT(MonoHacks, MONOHACKS);
   } Config;
 
   FEXCore::ForkableSharedMutex CodeInvalidationMutex;
@@ -225,23 +243,29 @@ public:
   FEXCore::HLE::SourcecodeResolver* SourcecodeResolver {};
   FEXCore::ThunkHandler* ThunkHandler {};
   fextl::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
-  CodeCache CodeCache;
 
   SignalDelegator* SignalDelegation {};
   X86GeneratedCode X86CodeGen;
 
   ContextImpl(const FEXCore::HostFeatures& Features);
+  ~ContextImpl();
 
   static bool ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP);
 
-  static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP);
+  // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
+  // Must be called from owning thread
+  static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP) {
+    auto Thread = Frame->Thread;
+    auto lk = GuardSignalDeferringSection(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
-  // This is used as a replacement for the SMC writes in the mono callsite backpatcher that avoids atomic operations
-  // (safe as the invalidation mutex is locked) and manually invalidates the modified range. Allowing SMC to be detected
-  // even if faulting is disabled.
-  static void MonoBackpatcherWrite(FEXCore::Core::CpuStateFrame* Frame, uint8_t Size, uint64_t Address, uint64_t Value);
+    // NOTE: Other threads sharing the same CodeBuffer may reference
+    //       invalidated data ranges through their L1/L2 caches. This is
+    //       not currently a problem since FEX does not repurpose the
+    //       invalidated CodeBuffer memory range currently.
+    ThreadRemoveCodeEntry(Thread, GuestRIP);
+  }
 
-  void RemoveCustomIREntrypoint(FEXCore::Core::InternalThreadState* Thread, uintptr_t Entrypoint);
+  void RemoveCustomIREntrypoint(uintptr_t Entrypoint);
 
   struct GenerateIRResult {
     std::optional<IR::IRListView> IRView;
@@ -300,10 +324,6 @@ public:
     return ExitOnHLT;
   }
 
-  bool AreMonoHacksActive() const {
-    return Config.MonoHacks && MonoDetected;
-  }
-
 protected:
   void UpdateAtomicTSOEmulationConfig() {
     if (SupportsHardwareTSO) {
@@ -316,9 +336,12 @@ protected:
       VectorAtomicTSOEmulationEnabled = true;
       MemcpyAtomicTSOEmulationEnabled = true;
     } else {
-      AtomicTSOEmulationEnabled = Config.TSOEnabled;
-      VectorAtomicTSOEmulationEnabled = Config.TSOEnabled && Config.VectorTSOEnabled;
-      MemcpyAtomicTSOEmulationEnabled = Config.TSOEnabled && Config.MemcpySetTSOEnabled;
+      // Atomic TSO emulation only enabled if the config option is enabled.
+      AtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled;
+      // Atomic vector TSO emulation only enabled if TSO emulation is enabled and also vector TSO is enabled.
+      VectorAtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled && Config.VectorTSOEnabled;
+      // Atomic memcpy TSO emulation only enabled if TSO emulation is enabled and also memcpy TSO is enabled.
+      MemcpyAtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled && Config.MemcpySetTSOEnabled;
     }
   }
 
@@ -332,6 +355,10 @@ private:
    */
   void InitializeCompiler(FEXCore::Core::InternalThreadState* Thread);
 
+  IR::AOTIRCaptureCache IRCaptureCache;
+  fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
+
+  bool IsMemoryShared = false;
   bool SupportsHardwareTSO = false;
   bool AtomicTSOEmulationEnabled = true;
   bool VectorAtomicTSOEmulationEnabled = false;
@@ -344,14 +371,11 @@ private:
   std::atomic<bool> HasCustomIRHandlers {};
   struct CustomIRHandlerEntry final {
     CustomIREntrypointHandler Handler;
-    void* Creator;
-    void* Data;
+    void *Creator;
+    void *Data;
   };
   fextl::unordered_map<uint64_t, CustomIRHandlerEntry> CustomIRHandlers;
   IntervalList<uint64_t> ForceTSOValidRanges; // The ranges for which ForceTSOInstructions has populated data
   fextl::set<uint64_t> ForceTSOInstructions;
-
-  bool MonoDetected = false;
-  std::atomic<uint64_t> MonoBackpatcherBlock;
 };
 } // namespace FEXCore::Context

FEXCore/Source/Interface/Core/Addressing.cpp

@@ -11,7 +11,8 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b
   Ref Tmp = A.Base;
 
   if (A.Offset) {
-    Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Offset) : IREmit->Constant(A.Offset);
+    Ref Offset = IREmit->Constant(A.Offset);
+    Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, Offset) : Offset;
   }
 
   if (A.Index) {
@@ -24,7 +25,7 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b
         Tmp = IREmit->_Lshl(GPRSize, A.Index, IREmit->Constant(Log2));
       }
     } else {
-      Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Index) : A.Index;
+      Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, A.Index) : A.Index;
     }
   }
 
@@ -45,7 +46,7 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b
   }
 
   if (A.Segment && AddSegmentBase) {
-    Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Segment) : A.Segment;
+    Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, A.Segment) : A.Segment;
   }
 
   return Tmp ?: IREmit->Constant(0);
@@ -53,15 +54,19 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b
 
 AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, bool HostSupportsTSOImm9, bool AtomicTSO, bool Vector,
                               IR::OpSize AccessSize) {
+  auto SoftwareAddressCalculation = [IREmit, &A, GPRSize]() -> AddressMode {
+    return {
+      .Base = LoadEffectiveAddress(IREmit, A, GPRSize, true),
+      .Index = IREmit->Invalid(),
+    };
+  };
+
   const auto Is32Bit = GPRSize == OpSize::i32Bit;
   const auto GPRSizeMatchesAddrSize = A.AddrSize == GPRSize;
   const auto OffsetIndexToLargeFor32Bit = Is32Bit && (A.Offset <= -16384 || A.Offset >= 16384);
   if (!GPRSizeMatchesAddrSize || OffsetIndexToLargeFor32Bit) {
     // If address size doesn't match GPR size then no optimizations can occur.
-    return {
-      .Base = LoadEffectiveAddress(IREmit, A, GPRSize, true),
-      .Index = IREmit->Invalid(),
-    };
+    return SoftwareAddressCalculation();
   }
 
   // Loadstore rules:
@@ -95,7 +100,7 @@ AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSi
   const bool OffsetIsSIMM9 = A.Offset && A.Offset >= -256 && A.Offset <= 255;
   const bool OffsetIsUnsignedScaled = A.Offset > 0 && (A.Offset & (AccessSizeAsImm - 1)) == 0 && (A.Offset / AccessSizeAsImm) <= 4095;
 
-  if ((AtomicTSO && !Vector && HostSupportsTSOImm9 && OffsetIsSIMM9) || (!AtomicTSO && (OffsetIsSIMM9 || OffsetIsUnsignedScaled))) {
+  auto InlineImmOffsetLoadstore = [IREmit, &GPRSize](AddressMode A) -> AddressMode {
     // Peel off the offset
     AddressMode B = A;
     B.Offset = 0;
@@ -106,20 +111,32 @@ AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSi
       .IndexType = MEM_OFFSET_SXTX,
       .IndexScale = 1,
     };
-  }
+  };
 
-  if (AtomicTSO) {
-    // TODO: LRCPC3 support for vector Imm9.
-  } else if (!Is32Bit && A.Base && (A.Index || A.Segment) && !A.Offset && (A.IndexScale == 1 || A.IndexScale == AccessSizeAsImm)) {
-    // ScaledRegisterLoadstore
+  auto ScaledRegisterLoadstore = [IREmit, GPRSize](AddressMode A) -> AddressMode {
     if (A.Index && A.Segment) {
-      A.Base = IREmit->Add(GPRSize, A.Base, A.Segment);
+      A.Base = IREmit->_Add(GPRSize, A.Base, A.Segment);
     } else if (A.Segment) {
       A.Index = A.Segment;
       A.IndexScale = 1;
     }
-
     return A;
+  };
+
+  if (AtomicTSO) {
+    if (!Vector) {
+      if (HostSupportsTSOImm9 && OffsetIsSIMM9) {
+        return InlineImmOffsetLoadstore(A);
+      }
+    } else {
+      // TODO: LRCPC3 support for vector Imm9.
+    }
+  } else {
+    if (OffsetIsSIMM9 || OffsetIsUnsignedScaled) {
+      return InlineImmOffsetLoadstore(A);
+    } else if (!Is32Bit && A.Base && (A.Index || A.Segment) && !A.Offset && (A.IndexScale == 1 || A.IndexScale == AccessSizeAsImm)) {
+      return ScaledRegisterLoadstore(A);
+    }
   }
 
   if (Vector || !AtomicTSO) {
@@ -142,10 +159,7 @@ AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSi
   }
 
   // Fallback on software address calculation
-  return {
-    .Base = LoadEffectiveAddress(IREmit, A, GPRSize, true),
-    .Index = IREmit->Invalid(),
-  };
+  return SoftwareAddressCalculation();
 }
 
 

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -712,7 +712,7 @@ void Arm64Emitter::SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs, uint3
   // Now handle PF/AF
   if (PFAFSpillMask) {
     auto PFOffset = offsetof(FEXCore::Core::CpuStateFrame, State.pf_raw);
-    auto AFOffset = offsetof(FEXCore::Core::CpuStateFrame, State.af_raw);
+    [[maybe_unused]] auto AFOffset = offsetof(FEXCore::Core::CpuStateFrame, State.af_raw);
     LOGMAN_THROW_A_FMT(PFAFSpillMask == PFAFMask, "PF/AF not spilled together");
     LOGMAN_THROW_A_FMT(AFOffset == PFOffset + 4, "PF/AF are together");
 

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -2,7 +2,7 @@
 #pragma once
 
 #include "FEXCore/Utils/EnumUtils.h"
-#include "Interface/Core/JIT/Relocations.h"
+#include "Interface/Core/ObjectCache/Relocations.h"
 
 #ifdef VIXL_DISASSEMBLER
 #include <aarch64/disasm-aarch64.h>

FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -317,7 +317,7 @@ namespace CPU {
     // Resize the code buffer and reallocate our code size
     CurrentCodeBuffer = CodeBuffers.StartLargerCodeBuffer();
 
-    RegisterForSignalHandler(std::move(PrevCodeBuffer));
+    RegisterForSignalHandler(PrevCodeBuffer);
     return CurrentCodeBuffer.get();
   }
 
@@ -326,13 +326,14 @@ namespace CPU {
       // We have signal handlers that have generated code
       // This means that we can not safely clear the code at this point in time
       // Keep a reference to the old code buffer to delay deallocation
-      SignalHandlerCodeBuffers.push_back(std::move(CodeBuffer));
+      SignalHandlerCodeBuffers.push_back(CodeBuffer);
     } else {
       SignalHandlerCodeBuffers.clear();
     }
   }
 
   fextl::shared_ptr<CodeBuffer> CPUBackend::CheckCodeBufferUpdate() {
+    fextl::shared_ptr<CodeBuffer> OldCodeBuffer;
     auto NewCodeBuffer = CodeBuffers.GetLatest();
     if (CurrentCodeBuffer != NewCodeBuffer) {
       RegisterForSignalHandler(CurrentCodeBuffer);

FEXCore/Source/Interface/Core/CPUBackend.h

@@ -17,10 +17,6 @@ $end_info$
 
 #include <cstdint>
 
-namespace FEXCore::CPU {
-union Relocation;
-}
-
 namespace FEXCore {
 
 namespace IR {
@@ -161,7 +157,18 @@ namespace CPU {
     virtual CompiledCode CompileCode(uint64_t Entry, uint64_t Size, bool SingleInst, const FEXCore::IR::IRListView* IR,
                                      FEXCore::Core::DebugData* DebugData, bool CheckTF) = 0;
 
-    virtual fextl::vector<FEXCore::CPU::Relocation> TakeRelocations() = 0;
+    /**
+     * @brief Relocates a block of code from the JIT code object cache
+     *
+     * @param Entry - RIP of the entry
+     * @param SerializationData - Serialization data referring to the object cache for `Entry`
+     *
+     * @return An executable function pointer relocated from the cache object
+     */
+    [[nodiscard]]
+    virtual void* RelocateJITObjectCode(uint64_t /* Entry */, const CodeSerialize::CodeObjectFileSection* /* SerializationData */) {
+      return nullptr;
+    }
 
     virtual void ClearCache() {}
 

FEXCore/Source/Interface/Core/CPUID.cpp

@@ -43,15 +43,12 @@ namespace ProductNames {
   static const char ARM_A715[] = "Cortex-A715";
   static const char ARM_A720[] = "Cortex-A720";
   static const char ARM_A725[] = "Cortex-A725";
-  static const char ARM_C1Pro[] = "C1-Pro";
-  static const char ARM_C1Premium[] = "C1-Premium";
   static const char ARM_X1[] = "Cortex-X1";
   static const char ARM_X1C[] = "Cortex-X1C";
   static const char ARM_X2[] = "Cortex-X2";
   static const char ARM_X3[] = "Cortex-X3";
   static const char ARM_X4[] = "Cortex-X4";
   static const char ARM_X925[] = "Cortex-X925";
-  static const char ARM_C1Ultra[] = "C1-Ultra";
   static const char ARM_N1[] = "Neoverse N1";
   static const char ARM_N2[] = "Neoverse N2";
   static const char ARM_N3[] = "Neoverse N3";
@@ -62,7 +59,6 @@ namespace ProductNames {
   static const char ARM_A65[] = "Cortex-A65";
   static const char ARM_A510[] = "Cortex-A510";
   static const char ARM_A520[] = "Cortex-A520";
-  static const char ARM_C1Nano[] = "C1-Nano";
 
   static const char ARM_Kryo200[] = "Kryo 2xx";
   static const char ARM_Kryo300[] = "Kryo 3xx";
@@ -74,7 +70,6 @@ namespace ProductNames {
 
   static const char ARM_Denver[] = "Nvidia Denver";
   static const char ARM_Carmel[] = "Nvidia Carmel";
-  static const char ARM_Olympus[] = "Nvidia Olympus";
 
   static const char ARM_Firestorm_M1[] = "Apple Firestorm (M1)";
   static const char ARM_Icestorm_M1[] = "Apple Icestorm (M1)";
@@ -90,9 +85,6 @@ namespace ProductNames {
   static const char ARM_Blizzard_M2Max[] = "Apple Blizzard (M2 Max)";
 
   static const char ARM_ORYON_1[] = "Oryon-1";
-  static const char ARM_Ampere_1[] = "AmpereOne";
-  static const char ARM_Ampere_1A[] = "AmpereOneA";
-  static const char ARM_Ampere_1B[] = "AmpereOneB";
 #else
 #endif
 } // namespace ProductNames
@@ -178,7 +170,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
   // CPU priority order
   // This is mostly arbitrary but will sort by some sort of CPU priority by performance
   // Relative list so things they will commonly end up in big.little configurations sort of relate
-  static constexpr std::array<CPUMIDR, 66> CPUMIDRs = {{
+  static constexpr std::array<CPUMIDR, 58> CPUMIDRs = {{
     // Typically big CPU cores
     {0x51, 0x001, 1, ProductNames::ARM_ORYON_1}, // Qualcomm Oryon-1
 
@@ -189,46 +181,38 @@ void CPUIDEmu::SetupHostHybridFlag() {
     {0x61, 0x025, 1, ProductNames::ARM_Firestorm_M1Pro}, // Apple Firestorm (M1 Pro)
     {0x61, 0x023, 1, ProductNames::ARM_Firestorm_M1},    // Apple Firestorm (M1)
 
-    {0x41, 0xd8c, 1, ProductNames::ARM_C1Ultra},   // C1-Ultra
-    {0x41, 0xd90, 1, ProductNames::ARM_C1Premium}, // C1-Premium
-    {0x41, 0xd8b, 1, ProductNames::ARM_C1Pro},     // C1-Pro
-    {0x41, 0xd85, 1, ProductNames::ARM_X925},      // X925
-    {0x41, 0xd87, 1, ProductNames::ARM_A725},      // A725
-    {0x41, 0xd84, 1, ProductNames::ARM_V3},        // V3
-    {0x41, 0xd83, 1, ProductNames::ARM_V3AE},      // V3AE
-    {0x41, 0xd8e, 1, ProductNames::ARM_N3},        // N3
-    {0x41, 0xd82, 1, ProductNames::ARM_X4},        // X4
-    {0x41, 0xd81, 1, ProductNames::ARM_A720},      // A720
-    {0x41, 0xd4e, 1, ProductNames::ARM_X3},        // X3
-    {0x41, 0xd4d, 1, ProductNames::ARM_A715},      // A715
-    {0x41, 0xd4f, 1, ProductNames::ARM_V2},        // V2
-    {0x41, 0xd4b, 1, ProductNames::ARM_A78C},      // A78C
-    {0x41, 0xd4a, 1, ProductNames::ARM_E1},        // E1
-    {0x41, 0xd49, 1, ProductNames::ARM_N2},        // N2
-    {0x41, 0xd48, 1, ProductNames::ARM_X2},        // X2
-    {0x41, 0xd47, 1, ProductNames::ARM_A710},      // A710
-    {0x41, 0xd4C, 1, ProductNames::ARM_X1C},       // X1C
-    {0x41, 0xd44, 1, ProductNames::ARM_X1},        // X1
-    {0x41, 0xd42, 1, ProductNames::ARM_A78AE},     // A78AE
-    {0x41, 0xd41, 1, ProductNames::ARM_A78},       // A78
-    {0x41, 0xd40, 1, ProductNames::ARM_V1},        // V1
-    {0x41, 0xd0e, 1, ProductNames::ARM_A76AE},     // A76AE
-    {0x41, 0xd0d, 1, ProductNames::ARM_A77},       // A77
-    {0x41, 0xd0c, 1, ProductNames::ARM_N1},        // N1
-    {0x41, 0xd0b, 1, ProductNames::ARM_A76},       // A76
-    {0x51, 0x804, 1, ProductNames::ARM_Kryo400},   // Kryo 4xx Gold (A76 based)
-    {0x41, 0xd0a, 1, ProductNames::ARM_A75},       // A75
-    {0x51, 0x802, 1, ProductNames::ARM_Kryo300},   // Kryo 3xx Gold (A75 based)
-    {0x41, 0xd09, 1, ProductNames::ARM_A73},       // A73
-    {0x51, 0x800, 1, ProductNames::ARM_Kryo200},   // Kryo 2xx Gold (A73 based)
-    {0x41, 0xd08, 1, ProductNames::ARM_A72},       // A72
+    {0x41, 0xd85, 1, ProductNames::ARM_X925},    // X925
+    {0x41, 0xd87, 1, ProductNames::ARM_A725},    // A725
+    {0x41, 0xd84, 1, ProductNames::ARM_V3},      // V3
+    {0x41, 0xd83, 1, ProductNames::ARM_V3AE},    // V3AE
+    {0x41, 0xd8e, 1, ProductNames::ARM_N3},      // N3
+    {0x41, 0xd82, 1, ProductNames::ARM_X4},      // X4
+    {0x41, 0xd81, 1, ProductNames::ARM_A720},    // A720
+    {0x41, 0xd4e, 1, ProductNames::ARM_X3},      // X3
+    {0x41, 0xd4d, 1, ProductNames::ARM_A715},    // A715
+    {0x41, 0xd4f, 1, ProductNames::ARM_V2},      // V2
+    {0x41, 0xd4b, 1, ProductNames::ARM_A78C},    // A78C
+    {0x41, 0xd4a, 1, ProductNames::ARM_E1},      // E1
+    {0x41, 0xd49, 1, ProductNames::ARM_N2},      // N2
+    {0x41, 0xd48, 1, ProductNames::ARM_X2},      // X2
+    {0x41, 0xd47, 1, ProductNames::ARM_A710},    // A710
+    {0x41, 0xd4C, 1, ProductNames::ARM_X1C},     // X1C
+    {0x41, 0xd44, 1, ProductNames::ARM_X1},      // X1
+    {0x41, 0xd42, 1, ProductNames::ARM_A78AE},   // A78AE
+    {0x41, 0xd41, 1, ProductNames::ARM_A78},     // A78
+    {0x41, 0xd40, 1, ProductNames::ARM_V1},      // V1
+    {0x41, 0xd0e, 1, ProductNames::ARM_A76AE},   // A76AE
+    {0x41, 0xd0d, 1, ProductNames::ARM_A77},     // A77
+    {0x41, 0xd0c, 1, ProductNames::ARM_N1},      // N1
+    {0x41, 0xd0b, 1, ProductNames::ARM_A76},     // A76
+    {0x51, 0x804, 1, ProductNames::ARM_Kryo400}, // Kryo 4xx Gold (A76 based)
+    {0x41, 0xd0a, 1, ProductNames::ARM_A75},     // A75
+    {0x51, 0x802, 1, ProductNames::ARM_Kryo300}, // Kryo 3xx Gold (A75 based)
+    {0x41, 0xd09, 1, ProductNames::ARM_A73},     // A73
+    {0x51, 0x800, 1, ProductNames::ARM_Kryo200}, // Kryo 2xx Gold (A73 based)
+    {0x41, 0xd08, 1, ProductNames::ARM_A72},     // A72
 
-    {0xc0, 0xac3, 1, ProductNames::ARM_Ampere_1},  // AmpereOne
-    {0xc0, 0xac4, 1, ProductNames::ARM_Ampere_1A}, // AmpereOneA
-    {0xc0, 0xac5, 1, ProductNames::ARM_Ampere_1B}, // AmpereOneB
-
-    {0x4e, 0x010, 1, ProductNames::ARM_Olympus}, // Olympus
-    {0x4e, 0x004, 1, ProductNames::ARM_Carmel},  // Carmel
+    {0x4e, 0x004, 1, ProductNames::ARM_Carmel}, // Carmel
 
     // Denver rated above A57 to match TX2 weirdness
     {0x4e, 0x003, 1, ProductNames::ARM_Denver}, // Denver
@@ -243,7 +227,6 @@ void CPUIDEmu::SetupHostHybridFlag() {
     {0x61, 0x024, 0, ProductNames::ARM_Icestorm_M1Pro}, // Apple Icestorm (M1 Pro)
     {0x61, 0x022, 0, ProductNames::ARM_Icestorm_M1},    // Apple Icestorm (M1)
 
-    {0x41, 0xd8a, 1, ProductNames::ARM_C1Nano},   // C1-Nano
     {0x41, 0xd80, 0, ProductNames::ARM_A520},     // A520
     {0x41, 0xd46, 0, ProductNames::ARM_A510},     // A510
     {0x41, 0xd06, 0, ProductNames::ARM_A65},      // A65
@@ -942,38 +925,38 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) con
             (0 << 30) | // Reserved
             (0 << 31);  // Reserved
 
-  Res.edx = (1 << 0) |                                // FPU
-            (1 << 1) |                                // Virtual mode extensions
-            (1 << 2) |                                // Debugging extensions
-            (1 << 3) |                                // Page size extensions
-            (1 << 4) |                                // TSC
-            (1 << 5) |                                // MSR support
-            (1 << 6) |                                // PAE
-            (1 << 7) |                                // Machine Check Exception
-            (1 << 8) |                                // CMPXCHG8B
-            (1 << 9) |                                // APIC
-            (0 << 10) |                               // Reserved
-            (1 << 11) |                               // SYSCALL/SYSRET
-            (1 << 12) |                               // MTRR
-            (1 << 13) |                               // Page global extension
-            (1 << 14) |                               // Machine Check architecture
-            (1 << 15) |                               // CMOV
-            (1 << 16) |                               // Page attribute table
-            (1 << 17) |                               // Page-size extensions
-            (0 << 18) |                               // Reserved
-            (0 << 19) |                               // Reserved
-            (1 << 20) |                               // NX
-            (0 << 21) |                               // Reserved
-            (1 << 22) |                               // MMXExt
-            (1 << 23) |                               // MMX
-            (1 << 24) |                               // FXSAVE/FXRSTOR
-            (1 << 25) |                               // FXSAVE/FXRSTOR Optimizations
-            (0 << 26) |                               // 1 gigabit pages
-            (SUPPORTS_RDTSCP << 27) |                 // RDTSCP
-            (0 << 28) |                               // Reserved
-            (1 << 29) |                               // Long Mode
-            (CTX->HostFeatures.Supports3DNow << 30) | // 3DNow! Extensions
-            (CTX->HostFeatures.Supports3DNow << 31);  // 3DNow!
+  Res.edx = (1 << 0) |                // FPU
+            (1 << 1) |                // Virtual mode extensions
+            (1 << 2) |                // Debugging extensions
+            (1 << 3) |                // Page size extensions
+            (1 << 4) |                // TSC
+            (1 << 5) |                // MSR support
+            (1 << 6) |                // PAE
+            (1 << 7) |                // Machine Check Exception
+            (1 << 8) |                // CMPXCHG8B
+            (1 << 9) |                // APIC
+            (0 << 10) |               // Reserved
+            (1 << 11) |               // SYSCALL/SYSRET
+            (1 << 12) |               // MTRR
+            (1 << 13) |               // Page global extension
+            (1 << 14) |               // Machine Check architecture
+            (1 << 15) |               // CMOV
+            (1 << 16) |               // Page attribute table
+            (1 << 17) |               // Page-size extensions
+            (0 << 18) |               // Reserved
+            (0 << 19) |               // Reserved
+            (1 << 20) |               // NX
+            (0 << 21) |               // Reserved
+            (1 << 22) |               // MMXExt
+            (1 << 23) |               // MMX
+            (1 << 24) |               // FXSAVE/FXRSTOR
+            (1 << 25) |               // FXSAVE/FXRSTOR Optimizations
+            (0 << 26) |               // 1 gigabit pages
+            (SUPPORTS_RDTSCP << 27) | // RDTSCP
+            (0 << 28) |               // Reserved
+            (1 << 29) |               // Long Mode
+            (1 << 30) |               // 3DNow! Extensions
+            (1 << 31);                // 3DNow!
   return Res;
 }
 

FEXCore/Source/Interface/Core/CodeCache.cpp

@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: MIT
-#include <Interface/Context/Context.h>
-
-#include <FEXCore/HLE/SourcecodeResolver.h>
-
-namespace FEXCore {
-
-ExecutableFileInfo::~ExecutableFileInfo() = default;
-
-} // namespace FEXCore
-
-namespace FEXCore::Context {
-
-CodeCache::CodeCache(ContextImpl& CTX_)
-  : CTX(CTX_) {}
-CodeCache::~CodeCache() = default;
-
-void CodeCache::LoadData(Core::InternalThreadState& Thread, std::byte* MappedCacheFile, const ExecutableFileSectionInfo& GuestRIPLookup) {
-  // TODO
-}
-
-bool CodeCache::SaveData(Core::InternalThreadState& Thread, int fd, const ExecutableFileSectionInfo& SourceBinary, uint64_t SerializedBaseAddress) {
-  // TODO
-  return true;
-}
-
-} // namespace FEXCore::Context

FEXCore/Source/Interface/Core/Core.cpp

@@ -14,11 +14,11 @@ $end_info$
 #include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
+#include "Interface/Core/ObjectCache/ObjectCacheService.h"
 #include "Interface/Core/OpcodeDispatcher.h"
 #include "Interface/Core/JIT/JITClass.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/X86Tables/X86Tables.h"
-#include <Interface/GDBJIT/GDBJIT.h>
 #include "Interface/IR/IR.h"
 #include "Interface/IR/IREmitter.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
@@ -78,7 +78,10 @@ namespace FEXCore::Context {
 ContextImpl::ContextImpl(const FEXCore::HostFeatures& Features)
   : HostFeatures {Features}
   , CPUID {this}
-  , CodeCache {*this} {
+  , IRCaptureCache {this} {
+  if (Config.CacheObjectCodeCompilation() != FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE) {
+    CodeObjectCacheService = fextl::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
+  }
   if (!Config.Is64BitMode()) {
     // When operating in 32-bit mode, the virtual memory we care about is only the lower 32-bits.
     Config.VirtualMemSize = 1ULL << 32;
@@ -102,6 +105,14 @@ ContextImpl::ContextImpl(const FEXCore::HostFeatures& Features)
   UpdateAtomicTSOEmulationConfig();
 }
 
+ContextImpl::~ContextImpl() {
+  {
+    if (CodeObjectCacheService) {
+      CodeObjectCacheService->Shutdown();
+    }
+  }
+}
+
 struct GetFrameBlockInfoResult {
   const CPU::CPUBackend::JITCodeHeader* InlineHeader;
   const CPU::CPUBackend::JITCodeTail* InlineTail;
@@ -128,11 +139,6 @@ bool ContextImpl::IsCurrentBlockSingleInst(FEXCore::Core::InternalThreadState* T
   return InlineTail && InlineTail->SingleInst;
 }
 
-uint64_t ContextImpl::GetGuestBlockEntry(FEXCore::Core::InternalThreadState* Thread) {
-  auto [_, InlineTail] = GetFrameBlockInfo(Thread->CurrentFrame);
-  return InlineTail ? InlineTail->RIP : 0;
-}
-
 uint64_t ContextImpl::RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState* Thread, uint64_t HostPC) {
   const auto Frame = Thread->CurrentFrame;
   const uint64_t BlockBegin = Frame->State.InlineJITBlockHeader;
@@ -343,9 +349,36 @@ bool ContextImpl::InitCore() {
   Dispatcher = FEXCore::CPU::Dispatcher::Create(this);
 
   // Set up the SignalDelegator config since core is initialized.
-  SignalDelegation->SetConfig(Dispatcher->MakeSignalDelegatorConfig());
+  FEXCore::SignalDelegator::SignalDelegatorConfig SignalConfig {
+    .DispatcherBegin = Dispatcher->Start,
+    .DispatcherEnd = Dispatcher->End,
 
-#if defined(_WIN32) && !defined(_M_ARM_64EC)
+    .AbsoluteLoopTopAddress = Dispatcher->AbsoluteLoopTopAddress,
+    .AbsoluteLoopTopAddressFillSRA = Dispatcher->AbsoluteLoopTopAddressFillSRA,
+    .SignalHandlerReturnAddress = Dispatcher->SignalHandlerReturnAddress,
+    .SignalHandlerReturnAddressRT = Dispatcher->SignalHandlerReturnAddressRT,
+
+    .PauseReturnInstruction = Dispatcher->PauseReturnInstruction,
+    .ThreadPauseHandlerAddressSpillSRA = Dispatcher->ThreadPauseHandlerAddressSpillSRA,
+    .ThreadPauseHandlerAddress = Dispatcher->ThreadPauseHandlerAddress,
+
+    // Stop handlers.
+    .ThreadStopHandlerAddressSpillSRA = Dispatcher->ThreadStopHandlerAddressSpillSRA,
+    .ThreadStopHandlerAddress = Dispatcher->ThreadStopHandlerAddress,
+
+    // SRA information.
+    .SRAGPRCount = Dispatcher->GetSRAGPRCount(),
+    .SRAFPRCount = Dispatcher->GetSRAFPRCount(),
+  };
+
+  Dispatcher->GetSRAGPRMapping(SignalConfig.SRAGPRMapping);
+  Dispatcher->GetSRAFPRMapping(SignalConfig.SRAFPRMapping);
+
+  // Give this configuration to the SignalDelegator.
+  SignalDelegation->SetConfig(SignalConfig);
+
+#ifndef _WIN32
+#elif !defined(_M_ARM_64EC)
   // WOW64 always needs the interrupt fault check to be enabled.
   Config.NeedsPendingInterruptFaultCheck = true;
 #endif
@@ -365,6 +398,12 @@ void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState* Thread, uin
 void ContextImpl::ExecuteThread(FEXCore::Core::InternalThreadState* Thread) {
   Dispatcher->ExecuteDispatch(Thread->CurrentFrame);
 
+  if (CodeObjectCacheService) {
+    // Ensure the Code Object Serialization service has fully serialized this thread's data before clearing the cache
+    // Use the thread's object cache ref counter for this
+    CodeSerialize::CodeObjectSerializeService::WaitForEmptyJobQueue(&Thread->ObjectCacheRefCounter);
+  }
+
   // If it is the parent thread that died then just leave
   // TODO: This doesn't make sense when the parent thread doesn't outlive its children
 }
@@ -402,6 +441,22 @@ ContextImpl::CreateThread(uint64_t InitialRIP, uint64_t StackPointer, const FEXC
   Thread->CurrentFrame->State.gregs[X86State::REG_RSP] = StackPointer;
   Thread->CurrentFrame->State.rip = InitialRIP;
 
+  // Set up default code segment.
+  // Default code segment indexes match the numbers that the Linux kernel uses.
+  Thread->CurrentFrame->State.cs_idx = 6 << 3;
+  auto &GDT = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3];
+  Thread->CurrentFrame->State.SetGDTBase(&GDT, 0);
+  Thread->CurrentFrame->State.SetGDTLimit(&GDT, 0xF'FFFFU);
+
+  if (Config.Is64BitMode) {
+    GDT.L = 1; // L = Long Mode = 64-bit
+    GDT.D = 0; // D = Default Operand SIze = Reserved
+  }
+  else {
+    GDT.L = 0; // L = Long Mode = 32-bit
+    GDT.D = 1; // D = Default Operand Size = 32-bit
+  }
+
   // Copy over the new thread state to the new object
   if (NewThreadState) {
     memcpy(&Thread->CurrentFrame->State, NewThreadState, sizeof(FEXCore::Core::CPUState));
@@ -465,6 +520,12 @@ void ContextImpl::OnCodeBufferAllocated(CPU::CodeBuffer& Buffer) {
 void ContextImpl::ClearCodeCache(FEXCore::Core::InternalThreadState* Thread, bool NewCodeBuffer) {
   FEXCORE_PROFILE_INSTANT("ClearCodeCache");
 
+  if (CodeObjectCacheService) {
+    // Ensure the Code Object Serialization service has fully serialized this thread's data before clearing the cache
+    // Use the thread's object cache ref counter for this
+    CodeSerialize::CodeObjectSerializeService::WaitForEmptyJobQueue(&Thread->ObjectCacheRefCounter);
+  }
+
   if (NewCodeBuffer) {
     // Allocate new CodeBuffer + L3 LookupCache and clear L1+L2 caches
     Thread->CPUBackend->ClearCache();
@@ -518,8 +579,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
     auto BlockInfo = Thread->FrontendDecoder->GetDecodedBlockInfo();
     auto CodeBlocks = &BlockInfo->Blocks;
 
-    Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount, BlockInfo->Is64BitMode,
-                                        AreMonoHacksActive() && MonoBackpatcherBlock.load(std::memory_order_relaxed) == GuestRIP);
+    Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount, BlockInfo->Is64BitMode);
 
     const auto GPRSize = Thread->OpDispatcher->GetGPROpSize();
 
@@ -547,7 +607,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 
       if (InstsInBlock == 0) {
         // Special case for an empty instruction block.
-        Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, Block.Entry - GuestRIP));
+        Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, Block.Entry - GuestRIP));
       }
 
       for (size_t i = 0; i < InstsInBlock; ++i) {
@@ -577,12 +637,11 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
           Thread->OpDispatcher->_GuestOpcode(InstAddress - GuestRIP);
         }
 
-        if (Config.SMCChecks == FEXCore::Config::CONFIG_SMC_FULL || Block.ForceFullSMCDetection) {
-          auto ExistingCodePtr = reinterpret_cast<uint8_t*>(Block.Entry + BlockInstructionsLength);
-          auto InstAddressReg = Thread->OpDispatcher->_EntrypointOffset(GPRSize, InstAddress - GuestRIP);
-          std::array<uint8_t, 0x10> CodeOriginal;
-          memcpy(CodeOriginal.data(), ExistingCodePtr, DecodedInfo->InstSize);
-          auto CodeChanged = Thread->OpDispatcher->_ValidateCode(CodeOriginal, InstAddressReg, DecodedInfo->InstSize);
+        if (Config.SMCChecks == FEXCore::Config::CONFIG_SMC_FULL) {
+          auto ExistingCodePtr = reinterpret_cast<uint64_t*>(Block.Entry + BlockInstructionsLength);
+
+          auto CodeChanged = Thread->OpDispatcher->_ValidateCode(ExistingCodePtr[0], ExistingCodePtr[1],
+                                                                 (uintptr_t)ExistingCodePtr - GuestRIP, DecodedInfo->InstSize);
 
           auto InvalidateCodeCond = Thread->OpDispatcher->CondJump(CodeChanged);
 
@@ -592,7 +651,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 
           Thread->OpDispatcher->SetCurrentCodeBlock(CodeWasChangedBlock);
           Thread->OpDispatcher->_ThreadRemoveCodeEntry();
-          Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, InstAddress - GuestRIP));
+          Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, InstAddress - GuestRIP));
 
           auto NextOpBlock = Thread->OpDispatcher->CreateNewCodeBlockAfter(CurrentBlock);
 
@@ -600,21 +659,15 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
           Thread->OpDispatcher->SetCurrentCodeBlock(NextOpBlock);
         }
 
-        if (TableInfo && TableInfo->OpcodeDispatcher.OpDispatch) {
-          auto Fn = TableInfo->OpcodeDispatcher.OpDispatch;
+        if (TableInfo && TableInfo->OpcodeDispatcher) {
+          auto Fn = TableInfo->OpcodeDispatcher;
           Thread->OpDispatcher->ResetHandledLock();
           Thread->OpDispatcher->ResetDecodeFailure();
-          IR::ForceTSOMode ForceTSO = IR::ForceTSOMode::NoOverride;
-          if (BlockInForceTSOValidRange) {
-            if (InstForceTSOIt != ForceTSOInstructions.end() && *InstForceTSOIt == InstAddress) {
-              ForceTSO = IR::ForceTSOMode::ForceEnabled;
-            } else {
-              ForceTSO = IR::ForceTSOMode::ForceDisabled;
-            }
-          } else if (DecodedInfo->Flags & X86Tables::DecodeFlags::FLAG_FORCE_TSO) {
-            ForceTSO = IR::ForceTSOMode::ForceEnabled;
-          }
-
+          IR::ForceTSOMode ForceTSO =
+            BlockInForceTSOValidRange ?
+              (InstForceTSOIt != ForceTSOInstructions.end() && *InstForceTSOIt == InstAddress ? IR::ForceTSOMode::ForceEnabled :
+                                                                                                IR::ForceTSOMode::ForceDisabled) :
+              IR::ForceTSOMode::NoOverride;
           Thread->OpDispatcher->SetForceTSO(ForceTSO);
           std::invoke(Fn, Thread->OpDispatcher, DecodedInfo);
           if (Thread->OpDispatcher->HadDecodeFailure()) {
@@ -664,8 +717,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 
         if (NeedsBlockEnd) {
           // We had some instructions. Early exit
-          Thread->OpDispatcher->ExitFunction(
-            Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, Block.Entry + BlockInstructionsLength - GuestRIP));
+          Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, Block.Entry + BlockInstructionsLength - GuestRIP));
           break;
         }
 
@@ -708,10 +760,27 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 }
 
 ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst) {
+  // JIT Code object cache lookup
+  if (CodeObjectCacheService) {
+    auto CodeCacheEntry = CodeObjectCacheService->FetchCodeObjectFromCache(GuestRIP);
+    if (CodeCacheEntry) {
+      auto CompiledCode = Thread->CPUBackend->RelocateJITObjectCode(GuestRIP, CodeCacheEntry);
+      if (CompiledCode) {
+        return {
+          .CompiledCode = {},
+          .DebugData = nullptr, // nullptr here ensures that code serialization doesn't occur on from cache read
+          .StartAddr = 0,       // Unused
+          .Length = 0,          // Unused
+          .NeedsAddGuestCodeRanges = false,
+        };
+      }
+    }
+  }
+
   if (SourcecodeResolver && Config.GDBSymbols()) {
-    auto MappedSection = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
-    if (MappedSection) {
-      MappedSection->FileInfo.SourcecodeMap = SourcecodeResolver->GenerateMap(MappedSection->FileInfo.Filename, MappedSection->FileInfo.FileId);
+    auto AOTIRCacheEntry = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
+    if (AOTIRCacheEntry.Entry && !AOTIRCacheEntry.Entry->ContainsCode) {
+      AOTIRCacheEntry.Entry->SourcecodeMap = SourcecodeResolver->GenerateMap(AOTIRCacheEntry.Entry->Filename, AOTIRCacheEntry.Entry->FileId);
     }
   }
 
@@ -786,44 +855,51 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
   if (Config.BlockJITNaming()) {
     auto FragmentBasePtr = CompiledCode.BlockBegin;
 
-    auto GuestRIPLookup = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
+    if (DebugData) {
+      auto GuestRIPLookup = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
 
-    if (DebugData->Subblocks.size()) {
-      for (auto& Subblock : DebugData->Subblocks) {
-        auto BlockBasePtr = FragmentBasePtr + Subblock.HostCodeOffset;
-        if (GuestRIPLookup) {
-          Symbols.Register(Thread->SymbolBuffer.get(), BlockBasePtr, CompiledCode.Size, GuestRIPLookup->FileInfo.Filename,
-                           GuestRIP - GuestRIPLookup->FileStartVA);
-        } else {
-          Symbols.Register(Thread->SymbolBuffer.get(), BlockBasePtr, GuestRIP, Subblock.HostCodeSize);
+      if (DebugData->Subblocks.size()) {
+        for (auto& Subblock : DebugData->Subblocks) {
+          auto BlockBasePtr = FragmentBasePtr + Subblock.HostCodeOffset;
+          if (GuestRIPLookup.Entry) {
+            Symbols.Register(Thread->SymbolBuffer.get(), BlockBasePtr, CompiledCode.Size, GuestRIPLookup.Entry->Filename,
+                             GuestRIP - GuestRIPLookup.VAFileStart);
+          } else {
+            Symbols.Register(Thread->SymbolBuffer.get(), BlockBasePtr, GuestRIP, Subblock.HostCodeSize);
+          }
         }
-      }
-    } else {
-      if (GuestRIPLookup) {
-        Symbols.Register(Thread->SymbolBuffer.get(), FragmentBasePtr, CompiledCode.Size, GuestRIPLookup->FileInfo.Filename,
-                         GuestRIP - GuestRIPLookup->FileStartVA);
       } else {
-        Symbols.Register(Thread->SymbolBuffer.get(), FragmentBasePtr, GuestRIP, CompiledCode.Size);
+        if (GuestRIPLookup.Entry) {
+          Symbols.Register(Thread->SymbolBuffer.get(), FragmentBasePtr, CompiledCode.Size, GuestRIPLookup.Entry->Filename,
+                           GuestRIP - GuestRIPLookup.VAFileStart);
+        } else {
+          Symbols.Register(Thread->SymbolBuffer.get(), FragmentBasePtr, GuestRIP, CompiledCode.Size);
+        }
       }
     }
   }
 
-  if (Config.LibraryJITNaming() || Config.GDBSymbols()) {
-    auto MappedSection = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
-    if (MappedSection) {
-      if (Config.LibraryJITNaming()) {
-        Symbols.RegisterNamedRegion(Thread->SymbolBuffer.get(), CodePtr, DebugData->HostCodeSize, MappedSection->FileInfo.Filename);
-      }
-
-      if (Config.GDBSymbols()) {
-        GDBJITRegister(MappedSection->FileInfo, MappedSection->FileStartVA, GuestRIP, (uintptr_t)CodePtr, *DebugData);
-      }
-    }
+  // Tell the object cache service to serialize the code if enabled
+  if (CodeObjectCacheService && Config.CacheObjectCodeCompilation == FEXCore::Config::ConfigObjectCodeHandler::CONFIG_READWRITE && DebugData) {
+    CodeObjectCacheService->AsyncAddSerializationJob(
+      fextl::make_unique<CodeSerialize::AsyncJobHandler::SerializationJobData>(CodeSerialize::AsyncJobHandler::SerializationJobData {
+        .GuestRIP = GuestRIP,
+        .GuestCodeLength = Length,
+        .GuestCodeHash = 0,
+        .HostCodeBegin = CompiledCode.BlockBegin,
+        .HostCodeLength = CompiledCode.Size,
+        .HostCodeHash = 0,
+        .ThreadJobRefCount = &Thread->ObjectCacheRefCounter,
+        .Relocations = std::move(*DebugData->Relocations),
+      }));
   }
 
   // Clear any relocations that might have been generated
-  if (!CodeCache.IsGeneratingCache) {
-    Thread->CPUBackend->ClearRelocations();
+  Thread->CPUBackend->ClearRelocations();
+
+  if (IRCaptureCache.PostCompileCode(Thread, CompiledCode.BlockBegin, GuestRIP, StartAddr, Length, {}, DebugData.get(), false)) {
+    // Early exit
+    return (uintptr_t)CodePtr;
   }
 
   if (NeedsAddGuestCodeRanges) {
@@ -902,6 +978,23 @@ void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState* T
   InvalidateGuestThreadCodeRange(Thread, Accumulator, Start, Length);
 }
 
+void ContextImpl::MarkMemoryShared(FEXCore::Core::InternalThreadState* Thread) {
+  if (!Thread) {
+    return;
+  }
+
+  if (!IsMemoryShared) {
+    IsMemoryShared = true;
+    UpdateAtomicTSOEmulationConfig();
+
+    if (Config.TSOAutoMigration) {
+      // Only the lookup cache is cleared here, so that old code can keep running until next compilation.
+      // This will leak previously compiled blocks until the CodeBuffer is cleared for some other reason.
+      Thread->LookupCache->ClearCache();
+    }
+  }
+}
+
 bool ContextImpl::ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP) {
   LogMan::Throw::AFmt(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex.try_lock() == false, "CodeInvalidationMutex needs to "
                                                                                                          "be unique_locked here");
@@ -909,10 +1002,6 @@ bool ContextImpl::ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState* Thre
   return Thread->LookupCache->Erase(Thread->CurrentFrame, GuestRIP);
 }
 
-void ContextImpl::ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP) {
-  static_cast<ContextImpl*>(Frame->Thread->CTX)->SyscallHandler->InvalidateGuestCodeRange(Frame->Thread, GuestRIP, 1);
-}
-
 std::optional<CustomIRResult>
 ContextImpl::AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void* Creator, void* Data) {
   LOGMAN_THROW_A_FMT(Config.Is64BitMode || !(Entrypoint >> 32), "64-bit Entrypoint in 32-bit mode {:x}", Entrypoint);
@@ -986,36 +1075,25 @@ void ContextImpl::RemoveForceTSOInformation(uint64_t Address, uint64_t Size) {
   ForceTSOInstructions.erase(ForceTSOInstructions.lower_bound(Address), ForceTSOInstructions.upper_bound(Address + Size));
 }
 
-void ContextImpl::MarkMonoBackpatcherBlock(uint64_t BlockEntry) {
-  MonoBackpatcherBlock.store(BlockEntry, std::memory_order_relaxed);
-}
-
-void ContextImpl::RemoveCustomIREntrypoint(FEXCore::Core::InternalThreadState* Thread, uintptr_t Entrypoint) {
+void ContextImpl::RemoveCustomIREntrypoint(uintptr_t Entrypoint) {
   LOGMAN_THROW_A_FMT(Config.Is64BitMode || !(Entrypoint >> 32), "64-bit Entrypoint in 32-bit mode {:x}", Entrypoint);
 
   std::scoped_lock lk(CustomIRMutex);
 
+  InvalidatedEntryAccumulator Accumulator;
+  InvalidateGuestCodeRange(nullptr, Accumulator, Entrypoint, 1);
   CustomIRHandlers.erase(Entrypoint);
+
   HasCustomIRHandlers = !CustomIRHandlers.empty();
-  SyscallHandler->InvalidateGuestCodeRange(Thread, Entrypoint, 1);
 }
 
-void ContextImpl::MonoBackpatcherWrite(FEXCore::Core::CpuStateFrame* Frame, uint8_t Size, uint64_t Address, uint64_t Value) {
-  auto Thread = Frame->Thread;
-  auto CTX = static_cast<ContextImpl*>(Thread->CTX);
-  {
-    auto lk = GuardSignalDeferringSection(CTX->CodeInvalidationMutex, Thread);
+IR::AOTIRCacheEntry* ContextImpl::LoadAOTIRCacheEntry(const fextl::string& filename) {
+  auto rv = IRCaptureCache.LoadAOTIRCacheEntry(filename);
+  return rv;
+}
 
-    if (Size == 8) {
-      *reinterpret_cast<uint64_t*>(Address) = Value;
-    } else if (Size == 4) {
-      *reinterpret_cast<uint32_t*>(Address) = Value;
-    } else {
-      ERROR_AND_DIE_FMT("Unexpected write size for backpatcher: {}", Size);
-    }
-  }
-
-  CTX->SyscallHandler->InvalidateGuestCodeRange(Thread, Address, Size);
+void ContextImpl::UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry* Entry) {
+  IRCaptureCache.UnloadAOTIRCacheEntry(Entry);
 }
 
 void ContextImpl::ConfigureAOTGen(FEXCore::Core::InternalThreadState* Thread, fextl::set<uint64_t>* ExternalBranches, uint64_t SectionMaxAddress) {

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -1,8 +1,7 @@
 // SPDX-License-Identifier: MIT
 
-#include "Common/VectorRegType.h"
+#include "Common/SoftFloat.h"
 #include "Interface/Context/Context.h"
-#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/X86HelperGen.h"
@@ -17,18 +16,14 @@
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
-#include <FEXHeaderUtils/Syscalls.h>
 
 #include <CodeEmitter/Emitter.h>
 
-#ifdef VIXL_SIMULATOR
-#include <aarch64/simulator-aarch64.h>
-#endif
-
-#include <array>
-#include <bit>
+#include <atomic>
+#include <condition_variable>
 #include <csignal>
 #include <cstring>
+#include <signal.h>
 
 namespace FEXCore::CPU {
 
@@ -91,7 +86,7 @@ void Dispatcher::EmitDispatcher() {
 
   FillStaticRegs();
   ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
-  (void)cbnz(ARMEmitter::Size::i32Bit, ENTRY_FILL_SRA_SINGLE_INST_REG, &CompileSingleStep);
+  cbnz(ARMEmitter::Size::i32Bit, ENTRY_FILL_SRA_SINGLE_INST_REG, &CompileSingleStep);
 
   ARMEmitter::BiDirectionalLabel LoopTop {};
 
@@ -139,39 +134,31 @@ void Dispatcher::EmitDispatcher() {
 
   // We want to ensure that we are 16 byte aligned at the top of this loop
   Align16B();
+  ARMEmitter::BiDirectionalLabel FullLookup {};
+  ARMEmitter::BiDirectionalLabel CallBlock {};
 
-  (void)Bind(&LoopTop);
+  Bind(&LoopTop);
   AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();
 
   // Load in our RIP
   ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
 
-#ifdef _M_ARM_64EC
-  // Clobbers TMP1/2
-  // Check the EC code bitmap incase we need to exit the JIT to call into native code.
-  ARMEmitter::ForwardLabel l_NotECCode;
-  ldr(TMP1, ARMEmitter::XReg::x18, TEB_PEB_OFFSET);
-  ldr(TMP1, TMP1, PEB_EC_CODE_BITMAP_OFFSET);
-
-  lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 15);
-  and_(ARMEmitter::Size::i64Bit, TMP2, TMP2, 0x1fffffffffff8);
-  ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
-  lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
-  lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
-  tbz(TMP1, 0, &l_NotECCode);
-
-  str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp));
-
-  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
-  mov(EC_CALL_CHECKER_PC_REG, RipReg);
-  ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
-  br(TMP2);
-
-  (void)!Bind(&l_NotECCode);
-#endif
-
   ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
-  (void)cbnz(ARMEmitter::Size::i32Bit, TMP1, &CompileSingleStep);
+  cbnz(ARMEmitter::Size::i32Bit, TMP1, &CompileSingleStep);
+
+  // L1 Cache
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
+
+  and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
+  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP4, ARMEmitter::ShiftType::LSL, 4);
+  ldp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP1, TMP1, 0);
+  sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, RipReg);
+  cbnz(ARMEmitter::Size::i64Bit, TMP1, &FullLookup);
+
+  br(TMP4);
+
+  // L1C check failed, do a full lookup
+  Bind(&FullLookup);
 
   // This is the block cache lookup routine
   // It matches what is going on it LookupCache.h::FindBlock
@@ -196,7 +183,7 @@ void Dispatcher::EmitDispatcher() {
     ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 3);
 
     // If page pointer is zero then we have no block
-    (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &NoBlock);
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &NoBlock);
 
     // Steal the page offset
     and_(ARMEmitter::Size::i64Bit, TMP2, TMP4, 0x0FFF);
@@ -211,11 +198,10 @@ void Dispatcher::EmitDispatcher() {
 
     // If the guest address doesn't match, Compile the block.
     sub(TMP2, TMP2, RipReg);
-    (void)cbnz(ARMEmitter::Size::i64Bit, TMP2, &NoBlock);
-
+    cbnz(ARMEmitter::Size::i64Bit, TMP2, &NoBlock);
 
     // Check the host address to see if it matches, else compile the block.
-    (void)cbz(ARMEmitter::Size::i64Bit, TMP4, &NoBlock);
+    cbz(ARMEmitter::Size::i64Bit, TMP4, &NoBlock);
 
     // If we've made it here then we have a real compiled block
     {
@@ -301,9 +287,39 @@ void Dispatcher::EmitDispatcher() {
     br(TMP1);
   }
 
+#ifdef _M_ARM_64EC
+  // Clobbers TMP1/2
+  auto EmitECExitCheck = [&]() {
+    // Check the EC code bitmap incase we need to exit the JIT to call into native code.
+    ARMEmitter::ForwardLabel l_NotECCode;
+    ldr(TMP1, ARMEmitter::XReg::x18, TEB_PEB_OFFSET);
+    ldr(TMP1, TMP1, PEB_EC_CODE_BITMAP_OFFSET);
+
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 15);
+    and_(ARMEmitter::Size::i64Bit, TMP2, TMP2, 0x1fffffffffff8);
+    ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
+    lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
+    tbz(TMP1, 0, &l_NotECCode);
+
+    str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp));
+
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
+    mov(EC_CALL_CHECKER_PC_REG, RipReg);
+    ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+    br(TMP2);
+
+    Bind(&l_NotECCode);
+  };
+#endif
+
   // Need to create the block
   {
-    (void)Bind(&NoBlock);
+    Bind(&NoBlock);
+
+#ifdef _M_ARM_64EC
+    EmitECExitCheck();
+#endif
 
     EmitSignalGuardedRegion([&]() {
       SpillStaticRegs(TMP1);
@@ -337,7 +353,11 @@ void Dispatcher::EmitDispatcher() {
   }
 
   {
-    (void)Bind(&CompileSingleStep);
+    Bind(&CompileSingleStep);
+
+#ifdef _M_ARM_64EC
+    EmitECExitCheck();
+#endif
 
     EmitSignalGuardedRegion([&]() {
       SpillStaticRegs(TMP1);
@@ -499,7 +519,7 @@ void Dispatcher::EmitDispatcher() {
     stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10);
 
     // Now go back to the regular dispatcher loop
-    (void)b(&LoopTop);
+    b(&LoopTop);
   }
 
   auto EmitLongALUOpHandler = [&](auto R, auto Offset) {
@@ -549,8 +569,8 @@ void Dispatcher::EmitDispatcher() {
       FABI_F80_I16_I32_PTR,
       FABI_F32_I16_F80_PTR,
       FABI_F64_I16_F80_PTR,
-      FABI_F64_F64_PTR,
-      FABI_F64_F64_F64_PTR,
+      FABI_F64_I16_F64_PTR,
+      FABI_F64_I16_F64_F64_PTR,
       FABI_I16_I16_F80_PTR,
       FABI_I32_I16_F80_PTR,
       FABI_I64_I16_F80_PTR,
@@ -558,7 +578,7 @@ void Dispatcher::EmitDispatcher() {
       FABI_F80_I16_F80_PTR,
       FABI_F80_I16_F80_F80_PTR,
       FABI_F80x2_I16_F80_PTR,
-      FABI_F64x2_F64_PTR,
+      FABI_F64x2_I16_F64_PTR,
       FABI_I32_I64_I64_V128_V128_I16,
       FABI_I32_V128_V128_I16,
     }};
@@ -568,15 +588,14 @@ void Dispatcher::EmitDispatcher() {
     }
   }
 
-  (void)Bind(&l_CTX);
+  Bind(&l_CTX);
   dc64(reinterpret_cast<uintptr_t>(CTX));
-  (void)Bind(&l_Sleep);
+  Bind(&l_Sleep);
   dc64(reinterpret_cast<uint64_t>(SleepThread));
-  (void)Bind(&l_CompileBlock);
+  Bind(&l_CompileBlock);
   FEXCore::Utils::MemberFunctionToPointerCast PMFCompileBlock(&FEXCore::Context::ContextImpl::CompileBlock);
   dc64(PMFCompileBlock.GetConvertedPointer());
-  (void)Bind(&l_CompileSingleStep);
-
+  Bind(&l_CompileSingleStep);
   FEXCore::Utils::MemberFunctionToPointerCast PMFCompileSingleStep(&FEXCore::Context::ContextImpl::CompileSingleStep);
   dc64(PMFCompileSingleStep.GetConvertedPointer());
 
@@ -758,7 +777,7 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 
     ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
     if (!TMP_ABIARGS) {
-      mov(VABI1.Q(), VTMP1.Q());
+      fmov(VABI1.D(), VTMP1.D());
     }
 
     mov(ARMEmitter::XReg::x1, STATE);
@@ -791,7 +810,7 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 
     FillF64Result();
   } break;
-  case FABI_F64_F64_PTR: {
+  case FABI_F64_I16_F64_PTR: {
     // Linux Reg/Win32 Reg:
     // tmp4 (x4/x13): FallbackHandler
     // x30: return
@@ -801,17 +820,18 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
     if (!TMP_ABIARGS) {
       fmov(VABI1.D(), VTMP1.D());
     }
-    mov(ARMEmitter::XReg::x0, STATE);
+    ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
+    mov(ARMEmitter::XReg::x1, STATE);
 
     if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<double, double, uint64_t>(FallbackPointerReg);
+      GenerateIndirectRuntimeCall<double, uint16_t, double, uint64_t>(FallbackPointerReg);
     } else {
       blr(FallbackPointerReg);
     }
 
     FillF64Result();
   } break;
-  case FABI_F64_F64_F64_PTR: {
+  case FABI_F64_I16_F64_F64_PTR: {
     // Linux Reg/Win32 Reg:
     // tmp4 (x4/x13): FallbackHandler
     // x30: return
@@ -824,9 +844,10 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
       fmov(VABI2.D(), VTMP2.D());
     }
 
-    mov(ARMEmitter::XReg::x0, STATE);
+    ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
+    mov(ARMEmitter::XReg::x1, STATE);
     if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<double, double, double, uint64_t>(FallbackPointerReg);
+      GenerateIndirectRuntimeCall<double, uint16_t, double, double, uint64_t>(FallbackPointerReg);
     } else {
       blr(FallbackPointerReg);
     }
@@ -986,7 +1007,7 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 
     FillF80x2Result();
   } break;
-  case FABI_F64x2_F64_PTR: {
+  case FABI_F64x2_I16_F64_PTR: {
     // Linux Reg/Win32 Reg:
     // tmp4 (x4/x13): FallbackHandler
     // x30: return
@@ -995,13 +1016,14 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 
     SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
 
-    mov(ARMEmitter::XReg::x0, STATE);
+    ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
+    mov(ARMEmitter::XReg::x1, STATE);
     if (!TMP_ABIARGS) {
       fmov(VABI1.D(), VTMP1.D());
     }
 
     if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      // GenerateIndirectRuntimeCall<FEXCore::VectorScalarF64Pair, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
+      // GenerateIndirectRuntimeCall<FEXCore::VectorScalarF64Pair, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
     } else {
       blr(FallbackPointerReg);
     }
@@ -1103,53 +1125,6 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
   }
 }
 
-SignalDelegatorConfig Dispatcher::MakeSignalDelegatorConfig() const {
-  // PF/AF are the final two SRA registers. We only want GPRs
-  const auto GPRCount = uint16_t(StaticRegisters.size() - 2);
-  const auto FPRCount = uint16_t(StaticFPRegisters.size());
-
-  const auto GetSRAGPRMapping = [GPRCount, this] {
-    SignalDelegatorConfig::SRAIndexMapping Mapping {};
-    for (size_t i = 0; i < GPRCount; ++i) {
-      Mapping[i] = StaticRegisters[i].Idx();
-    }
-    return Mapping;
-  };
-
-  const auto GetSRAFPRMapping = [FPRCount, this] {
-    SignalDelegatorConfig::SRAIndexMapping Mapping {};
-    for (size_t i = 0; i < FPRCount; ++i) {
-      Mapping[i] = StaticFPRegisters[i].Idx();
-    }
-    return Mapping;
-  };
-
-  return FEXCore::SignalDelegatorConfig {
-    .DispatcherBegin = Start,
-    .DispatcherEnd = End,
-
-    .AbsoluteLoopTopAddress = AbsoluteLoopTopAddress,
-    .AbsoluteLoopTopAddressFillSRA = AbsoluteLoopTopAddressFillSRA,
-    .SignalHandlerReturnAddress = SignalHandlerReturnAddress,
-    .SignalHandlerReturnAddressRT = SignalHandlerReturnAddressRT,
-
-    .PauseReturnInstruction = PauseReturnInstruction,
-    .ThreadPauseHandlerAddressSpillSRA = ThreadPauseHandlerAddressSpillSRA,
-    .ThreadPauseHandlerAddress = ThreadPauseHandlerAddress,
-
-    // Stop handlers.
-    .ThreadStopHandlerAddressSpillSRA = ThreadStopHandlerAddressSpillSRA,
-    .ThreadStopHandlerAddress = ThreadStopHandlerAddress,
-
-    // SRA information.
-    .SRAGPRCount = GPRCount,
-    .SRAFPRCount = FPRCount,
-
-    .SRAGPRMapping = GetSRAGPRMapping(),
-    .SRAFPRMapping = GetSRAFPRMapping(),
-  };
-}
-
 fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl* CTX) {
   return fextl::make_unique<Dispatcher>(CTX);
 }

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -2,18 +2,25 @@
 #pragma once
 
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/fextl/memory.h>
 
-#include <array>
-#include <cstddef>
+#ifdef VIXL_SIMULATOR
+#include <aarch64/simulator-aarch64.h>
+#endif
+
 #include <cstdint>
+#include <signal.h>
+#include <stddef.h>
+#include <stack>
+#include <tuple>
 
 namespace FEXCore {
 struct GuestSigAction;
-struct SignalDelegatorConfig;
-} // namespace FEXCore
+}
 
 namespace FEXCore::Core {
 struct CpuStateFrame;
@@ -35,32 +42,6 @@ public:
   Dispatcher(FEXCore::Context::ContextImpl* ctx);
   ~Dispatcher();
 
-  void InitThreadPointers(FEXCore::Core::InternalThreadState* Thread);
-
-#ifdef VIXL_SIMULATOR
-  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame);
-  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);
-#else
-  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame) {
-    DispatchPtr(Frame, false);
-  }
-
-  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP) {
-    CallbackPtr(Frame, RIP);
-  }
-#endif
-
-  SignalDelegatorConfig MakeSignalDelegatorConfig() const;
-
-protected:
-  FEXCore::Context::ContextImpl* CTX;
-
-  using AsmDispatch = void (*)(FEXCore::Core::CpuStateFrame* Frame, bool SingleInst);
-  using JITCallback = void (*)(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);
-
-  AsmDispatch DispatchPtr;
-  JITCallback CallbackPtr;
-private:
   /**
    * @name Dispatch Helper functions
    * @{ */
@@ -78,14 +59,62 @@ private:
   uint64_t GuestSignal_SIGILL {};
   uint64_t GuestSignal_SIGTRAP {};
   uint64_t GuestSignal_SIGSEGV {};
+  uint64_t IntCallbackReturnAddress {};
 
   uint64_t PauseReturnInstruction {};
   std::array<uint64_t, FallbackABI::FABI_UNKNOWN> ABIPointers {};
+
   /**  @} */
 
   uint64_t Start {};
   uint64_t End {};
 
+  void InitThreadPointers(FEXCore::Core::InternalThreadState* Thread);
+
+#ifdef VIXL_SIMULATOR
+  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame);
+  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);
+#else
+  void ExecuteDispatch(FEXCore::Core::CpuStateFrame* Frame) {
+    DispatchPtr(Frame, false);
+  }
+
+  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP) {
+    CallbackPtr(Frame, RIP);
+  }
+#endif
+
+  uint16_t GetSRAGPRCount() const {
+    // PF/AF are the final two SRA registers.
+    // Only return the SRA for GPRs.
+    return StaticRegisters.size() - 2;
+  }
+
+  uint16_t GetSRAFPRCount() const {
+    return StaticFPRegisters.size();
+  }
+
+  void GetSRAGPRMapping(uint8_t Mapping[16]) const {
+    for (size_t i = 0; i < StaticRegisters.size() - 2; ++i) {
+      Mapping[i] = StaticRegisters[i].Idx();
+    }
+  }
+
+  void GetSRAFPRMapping(uint8_t Mapping[16]) const {
+    for (size_t i = 0; i < StaticFPRegisters.size(); ++i) {
+      Mapping[i] = StaticFPRegisters[i].Idx();
+    }
+  }
+
+protected:
+  FEXCore::Context::ContextImpl* CTX;
+
+  using AsmDispatch = void (*)(FEXCore::Core::CpuStateFrame* Frame, bool SingleInst);
+  using JITCallback = void (*)(FEXCore::Core::CpuStateFrame* Frame, uint64_t RIP);
+
+  AsmDispatch DispatchPtr;
+  JITCallback CallbackPtr;
+private:
   // Long division helpers
   uint64_t LUDIVHandlerAddress {};
   uint64_t LDIVHandlerAddress {};

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -71,23 +71,7 @@ Decoder::Decoder(FEXCore::Core::InternalThreadState* Thread)
   : Thread {Thread}
   , CTX {static_cast<FEXCore::Context::ContextImpl*>(Thread->CTX)}
   , OSABI {CTX->SyscallHandler ? CTX->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN}
-  , PoolObject {CTX->FrontendAllocator, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize} {
-
-  FEX_CONFIG_OPT(ReducedPrecision, X87REDUCEDPRECISION);
-  if (ReducedPrecision) {
-    X87Table = &FEXCore::X86Tables::X87F64Ops;
-  } else {
-    X87Table = &FEXCore::X86Tables::X87F80Ops;
-  }
-
-  if (CTX->HostFeatures.SupportsAVX && CTX->HostFeatures.SupportsSVE256) {
-    VEXTable = &FEXCore::X86Tables::VEXTableOps;
-    VEXTableGroup = &FEXCore::X86Tables::VEXTableGroupOps;
-  } else if (CTX->HostFeatures.SupportsAVX) {
-    VEXTable = &FEXCore::X86Tables::VEXTableOps_AVX128;
-    VEXTableGroup = &FEXCore::X86Tables::VEXTableGroupOps_AVX128;
-  }
-}
+  , PoolObject {CTX->FrontendAllocator, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize} {}
 
 bool Decoder::CheckRangeExecutable(uint64_t Address, uint64_t Size) {
   // Treat FEX-internal X86 callbacks as always executable
@@ -99,7 +83,6 @@ bool Decoder::CheckRangeExecutable(uint64_t Address, uint64_t Size) {
     auto RangeInfo = CTX->SyscallHandler->QueryGuestExecutableRange(Thread, Address);
     ExecutableRangeBase = RangeInfo.Base;
     ExecutableRangeEnd = RangeInfo.Base + RangeInfo.Size;
-    ExecutableRangeWritable = RangeInfo.Writable;
 
     if (RangeInfo.Size == 0) {
       return false;
@@ -259,13 +242,13 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
 
   if (HasSIB) {
     FEXCore::X86Tables::SIBDecoded SIB;
-    if (DecodeInst->Flags & DecodeFlags::FLAG_DECODED_SIB) {
+    if (DecodeInst->DecodedSIB) {
       SIB.Hex = DecodeInst->SIB;
     } else {
       // Haven't yet grabbed SIB, pull it now
       DecodeInst->SIB = ReadByte();
       SIB.Hex = DecodeInst->SIB;
-      DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_SIB;
+      DecodeInst->DecodedSIB = true;
     }
 
     // If the SIB base is 0b101, aka BP or R13 then we have a 32bit displacement
@@ -331,13 +314,6 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
 }
 
 bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op, DecodedHeader Options) {
-  if (Info->Type == FEXCore::X86Tables::TYPE_ARCH_DISPATCHER) [[unlikely]] {
-    // Dispatcher Op.
-    // TODO: Move this in to `NormalOpHeader`, Dispatch tables have a bug currently where some subtables don't inherit flags correctly.
-    // Can be seen by running FEX asm tests if this is removed.
-    return NormalOp(&Info->OpcodeDispatcher.Indirect[BlockInfo.Is64BitMode ? 1 : 0], Op);
-  }
-
   DecodeInst->OP = Op;
   DecodeInst->TableInfo = Info;
 
@@ -401,9 +377,9 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
 
   // If we require ModRM and haven't decoded it yet, do it now
   // Some instructions have to read modrm upfront, others do it later
-  if (HasMODRM && !(DecodeInst->Flags & DecodeFlags::FLAG_DECODED_MODRM)) {
+  if (HasMODRM && !DecodeInst->DecodedModRM) {
     DecodeInst->ModRM = ReadByte();
-    DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+    DecodeInst->DecodedModRM = true;
   }
 
   // New instruction size decoding
@@ -436,8 +412,9 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
       // If the default operating mode is 32bit and we have the operand size flag then the operating size drops to 16bit
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_16BIT);
       DestSize = 2;
-    } else if ((HasXMMDst || HasMMDst || BlockInfo.Is64BitMode) && (HasWideningDisplacement || DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
-                                                                    DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
+    } else if ((HasXMMDst || HasMMDst || BlockInfo.Is64BitMode) &&
+               (HasWideningDisplacement || DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
+                DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_64BIT);
       DestSize = 8;
     } else {
@@ -464,8 +441,9 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
       // See table 1-2. Operand-Size Overrides for this decoding
       // If the default operating mode is 32bit and we have the operand size flag then the operating size drops to 16bit
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_16BIT);
-    } else if ((HasXMMSrc || HasMMSrc || BlockInfo.Is64BitMode) && (HasWideningDisplacement || SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
-                                                                    SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
+    } else if ((HasXMMSrc || HasMMSrc || BlockInfo.Is64BitMode) &&
+               (HasWideningDisplacement || SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
+                SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_64BIT);
     } else {
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_32BIT);
@@ -634,20 +612,11 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
         Literal = static_cast<int32_t>(Literal);
       }
       DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
-      DecodeInst->Src[CurrentSrc].Data.Literal.SignExtend = true;
-    }
-
-    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
-    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
-    ++CurrentSrc;
-
-    if (Bytes == 8) [[unlikely]] {
-      DecodeInst->Src[CurrentSrc].Data.Literal.Size = 4;
-      DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
-      DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal >> 32;
     }
 
     Bytes = 0;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
   }
 
   LOGMAN_THROW_A_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining", DecodeInst->PC,
@@ -657,7 +626,7 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
 }
 
 bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op) {
-  DecodeInst->OPRaw = DecodeInst->OP = Op;
+  DecodeInst->OP = Op;
   DecodeInst->TableInfo = Info;
 
   if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
@@ -673,13 +642,10 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
   // A normal instruction is the most likely.
   if (Info->Type == FEXCore::X86Tables::TYPE_INST) [[likely]] {
     return NormalOp(Info, Op);
-  } else if (Info->Type == FEXCore::X86Tables::TYPE_ARCH_DISPATCHER) [[unlikely]] {
-    // Dispatcher Op.
-    return NormalOp(&Info->OpcodeDispatcher.Indirect[BlockInfo.Is64BitMode ? 1 : 0], Op);
   } else if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
     uint8_t ModRMByte = ReadByte();
     DecodeInst->ModRM = ModRMByte;
-    DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+    DecodeInst->DecodedModRM = true;
 
     FEXCore::X86Tables::ModRMDecoded ModRM;
     ModRM.Hex = DecodeInst->ModRM;
@@ -696,24 +662,24 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     constexpr uint16_t PF_F2 = 3;
 
     uint16_t PrefixType = PF_NONE;
-    if (LastEscapePrefix == 0xF3) {
+    if (DecodeInst->LastEscapePrefix == 0xF3) {
       PrefixType = PF_F3;
-    } else if (LastEscapePrefix == 0xF2) {
+    } else if (DecodeInst->LastEscapePrefix == 0xF2) {
       PrefixType = PF_F2;
-    } else if (LastEscapePrefix == 0x66) {
+    } else if (DecodeInst->LastEscapePrefix == 0x66) {
       PrefixType = PF_66;
     }
 
     // We have ModRM
     uint8_t ModRMByte = ReadByte();
     DecodeInst->ModRM = ModRMByte;
-    DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+    DecodeInst->DecodedModRM = true;
 
     FEXCore::X86Tables::ModRMDecoded ModRM;
     ModRM.Hex = DecodeInst->ModRM;
 
     uint16_t LocalOp = OPD(Info->Type, PrefixType, ModRM.reg);
-    const FEXCore::X86Tables::X86InstInfo* LocalInfo = &SecondInstGroupOps[LocalOp];
+    FEXCore::X86Tables::X86InstInfo* LocalInfo = &SecondInstGroupOps[LocalOp];
 #undef OPD
     if (LocalInfo->Type == FEXCore::X86Tables::TYPE_SECOND_GROUP_MODRM && ModRM.mod == 0b11) {
       // Everything in this group is privileged instructions aside from XGETBV
@@ -734,16 +700,11 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     // We have ModRM
     uint8_t ModRMByte = ReadByte();
     DecodeInst->ModRM = ModRMByte;
-    DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+    DecodeInst->DecodedModRM = true;
 
     uint16_t X87Op = ((Op - 0xD8) << 8) | ModRMByte;
-    return NormalOp(&(*X87Table)[X87Op], X87Op);
+    return NormalOp(&X87Ops[X87Op], X87Op);
   } else if (Info->Type == FEXCore::X86Tables::TYPE_VEX_TABLE_PREFIX) {
-    if (!VEXTable) {
-      // AVX not enabled.
-      return false;
-    }
-
     uint16_t map_select = 1;
     uint16_t pp = 0;
     const uint8_t Byte1 = ReadByte();
@@ -781,6 +742,7 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
         DecodeInst->Flags |= DecodeFlags::FLAG_OPTION_AVX_W;
       }
       if (!(map_select >= 1 && map_select <= 3)) {
+        LogMan::Msg::EFmt("We don't understand a map_select of: {}", map_select);
         return false;
       }
     }
@@ -790,13 +752,13 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     Op = OPD(map_select, pp, VEXOp);
 #undef OPD
 
-    const FEXCore::X86Tables::X86InstInfo* LocalInfo = &(*VEXTable)[Op];
+    FEXCore::X86Tables::X86InstInfo* LocalInfo = &VEXTableOps[Op];
 
     if (LocalInfo->Type >= FEXCore::X86Tables::TYPE_VEX_GROUP_12 && LocalInfo->Type <= FEXCore::X86Tables::TYPE_VEX_GROUP_17) {
       // We have ModRM
       uint8_t ModRMByte = ReadByte();
       DecodeInst->ModRM = ModRMByte;
-      DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+      DecodeInst->DecodedModRM = true;
 
       FEXCore::X86Tables::ModRMDecoded ModRM;
       ModRM.Hex = DecodeInst->ModRM;
@@ -804,7 +766,7 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
 #define OPD(group, pp, opcode) (((group - TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
       Op = OPD(LocalInfo->Type, pp, ModRM.reg);
 #undef OPD
-      return NormalOp(&(*VEXTableGroup)[Op], Op, options);
+      return NormalOp(&VEXTableGroupOps[Op], Op, options);
     } else {
       return NormalOp(LocalInfo, Op, options);
     }
@@ -820,7 +782,6 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
 
 bool Decoder::DecodeInstructionImpl(uint64_t PC) {
   InstructionSize = 0;
-  LastEscapePrefix = 0;
   Instruction.fill(0);
 
   DecodeInst = &DecodedBuffer[DecodedSize];
@@ -842,7 +803,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
           // Decode ModRM
           uint8_t ModRMByte = ReadByte();
           DecodeInst->ModRM = ModRMByte;
-          DecodeInst->Flags |= DecodeFlags::FLAG_DECODED_MODRM;
+          DecodeInst->DecodedModRM = true;
 
           FEXCore::X86Tables::ModRMDecoded ModRM;
           ModRM.Hex = DecodeInst->ModRM;
@@ -881,7 +842,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
         uint16_t LocalOp = (Prefix << 8) | ReadByte();
 
         bool NoOverlay66 = (FEXCore::X86Tables::H0F38TableOps[LocalOp].Flags & InstFlags::FLAGS_NO_OVERLAY66) != 0;
-        if (LastEscapePrefix == 0x66 && NoOverlay66) { // Operand Size
+        if (DecodeInst->LastEscapePrefix == 0x66 && NoOverlay66) { // Operand Size
           // Remove prefix so it doesn't effect calculations.
           // This is only an escape prefix rather than modifier now
           DecodeInst->Flags &= ~DecodeFlags::FLAG_OPERAND_SIZE;
@@ -897,7 +858,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
         constexpr uint16_t PF_3A_REX = (1 << 1);
 
         uint16_t Prefix = PF_3A_NONE;
-        if (LastEscapePrefix == 0x66) { // Operand Size
+        if (DecodeInst->LastEscapePrefix == 0x66) { // Operand Size
           Prefix = PF_3A_66;
         }
 
@@ -923,17 +884,17 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
 
           if (NoOverlay) { // This section of the table ignores prefix extention
             return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
-          } else if (LastEscapePrefix == 0xF3) { // REP
+          } else if (DecodeInst->LastEscapePrefix == 0xF3) { // REP
             // Remove prefix so it doesn't effect calculations.
             // This is only an escape prefix rather tan modifier now
             DecodeInst->Flags &= ~DecodeFlags::FLAG_REP_PREFIX;
             return NormalOpHeader(&FEXCore::X86Tables::RepModOps[EscapeOp], EscapeOp);
-          } else if (LastEscapePrefix == 0xF2) { // REPNE
+          } else if (DecodeInst->LastEscapePrefix == 0xF2) { // REPNE
             // Remove prefix so it doesn't effect calculations.
             // This is only an escape prefix rather tan modifier now
             DecodeInst->Flags &= ~DecodeFlags::FLAG_REPNE_PREFIX;
             return NormalOpHeader(&FEXCore::X86Tables::RepNEModOps[EscapeOp], EscapeOp);
-          } else if (LastEscapePrefix == 0x66 && !NoOverlay66) { // Operand Size
+          } else if (DecodeInst->LastEscapePrefix == 0x66 && !NoOverlay66) { // Operand Size
             // Remove prefix so it doesn't effect calculations.
             // This is only an escape prefix rather tan modifier now
             DecodeInst->Flags &= ~DecodeFlags::FLAG_OPERAND_SIZE;
@@ -949,7 +910,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
     }
     case 0x66: // Operand Size prefix
       DecodeInst->Flags |= DecodeFlags::FLAG_OPERAND_SIZE;
-      LastEscapePrefix = Op;
+      DecodeInst->LastEscapePrefix = Op;
       DecodeFlags::PushOpAddr(&DecodeInst->Flags, DecodeFlags::FLAG_OPERAND_SIZE_LAST);
       break;
     case 0x67: // Address Size override prefix
@@ -980,11 +941,11 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
       break;
     case 0xF2: // REPNE prefix
       DecodeInst->Flags |= DecodeFlags::FLAG_REPNE_PREFIX;
-      LastEscapePrefix = Op;
+      DecodeInst->LastEscapePrefix = Op;
       break;
     case 0xF3: // REP prefix
       DecodeInst->Flags |= DecodeFlags::FLAG_REP_PREFIX;
-      LastEscapePrefix = Op;
+      DecodeInst->LastEscapePrefix = Op;
       break;
     case 0x64: // FS prefix
       DecodeInst->Flags = (DecodeInst->Flags & ~FEXCore::X86Tables::DecodeFlags::FLAG_SEGMENTS) | DecodeFlags::FLAG_FS_PREFIX;
@@ -994,10 +955,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
       break;
     default:
       [[likely]] { // Default base table
-        const X86InstInfo* Info = &FEXCore::X86Tables::BaseOps[Op];
-        if (Info->Type == FEXCore::X86Tables::TYPE_ARCH_DISPATCHER) {
-          Info = &Info->OpcodeDispatcher.Indirect[BlockInfo.Is64BitMode ? 1 : 0];
-        }
+        auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
         if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
           DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
@@ -1049,27 +1007,11 @@ Decoder::DecodedBlockStatus Decoder::DecodeInstruction(uint64_t PC) {
     DecodeInst->TableInfo = nullptr;
     DecodeInst->InstSize = 0;
     return ErrorDuringDecoding ? DecodedBlockStatus::INVALID_INST : DecodedBlockStatus::NOEXEC_INST;
-  } else if (!DecodeInst->TableInfo || (DecodeInst->TableInfo->Type == TYPE_INST && !DecodeInst->TableInfo->OpcodeDispatcher.OpDispatch)) {
+  } else if (!DecodeInst->TableInfo || !DecodeInst->TableInfo->OpcodeDispatcher) {
     // If there wasn't an error during decoding but we have no dispatcher for the instruction then claim invalid instruction.
     return DecodedBlockStatus::INVALID_INST;
   }
 
-  if (CTX->AreMonoHacksActive()) {
-    // Unity uses a standard SPSC ringbuffer with cached read/write pointers and thread waiting flags at the following
-    // offsets, which are consistent between 32-bit and 64-bit Unity versions from 2015 onwards.
-    auto IsKnownAtomicDisplacement = [](uint64_t Displacement) {
-      return Displacement == 0x80 || Displacement == 0x84 || Displacement == 0xC0 || Displacement == 0xC4;
-    };
-
-    if (DecodeInst->OP == 0x8b && DecodeInst->Src[0].IsGPRIndirect() &&
-        IsKnownAtomicDisplacement(DecodeInst->Src[0].Data.GPRIndirect.Displacement)) {
-      DecodeInst->Flags |= X86Tables::DecodeFlags::FLAG_FORCE_TSO;
-    }
-    if (DecodeInst->OP == 0x89 && DecodeInst->Dest.IsGPRIndirect() && IsKnownAtomicDisplacement(DecodeInst->Dest.Data.GPRIndirect.Displacement)) {
-      DecodeInst->Flags |= X86Tables::DecodeFlags::FLAG_FORCE_TSO;
-    }
-  }
-
   return DecodedBlockStatus::SUCCESS;
 }
 
@@ -1085,13 +1027,6 @@ void Decoder::BranchTargetInMultiblockRange() {
   const auto InstEnd = DecodeInst->PC + DecodeInst->InstSize;
 
   if (DecodeInst->TableInfo->Flags & FEXCore::X86Tables::InstFlags::FLAGS_CALL) {
-    if (ExecutableRangeWritable && CTX->AreMonoHacksActive()) {
-      // Mono generated code often contains noreturn calls with garbage following them, and calls are always backpatched
-      // after CIL compilation leading to n recompiles for a multiblock with n calls. Choose to minimize stutters over
-      // raw performance and disable tracking past calls for mono generated code.
-      return;
-    }
-
     AddBranchTarget(InstEnd);
     BlockInfo.EntryPoints.emplace(InstEnd);
     return;
@@ -1123,16 +1058,10 @@ void Decoder::BranchTargetInMultiblockRange() {
     TargetRIP &= 0xFFFFFFFFU;
   }
 
-  if (Conditional) {
-    // If we are conditional then a target can be the instruction past the conditional instruction
-    AddBranchTarget(InstEnd);
-  }
-
   // If the target RIP is x86 code within the symbol ranges then we are golden
-  // Forbid distant branches to have the cost code better match the guest code layout, avoiding massive (range-wise) code
-  // blocks in highly fragmented guest code. Such branches are often not-taken branches to garbage in obfuscated code.
-  constexpr uint64_t MAX_FORWARD_BRANCH_DIST = FEXCore::Utils::FEX_PAGE_SIZE * 4;
-  bool ValidMultiblockMember = TargetRIP >= SymbolMinAddress && TargetRIP < std::min(InstEnd + MAX_FORWARD_BRANCH_DIST, SymbolMaxAddress);
+  // Forbid cross-page branches to both avoid massive (range-wise) code blocks in highly fragmented code and trying to decode unmapped branch targets
+  bool ValidMultiblockMember =
+    TargetRIP >= SymbolMinAddress && TargetRIP < std::min(FEXCore::AlignUp(InstEnd, FEXCore::Utils::FEX_PAGE_SIZE), SymbolMaxAddress);
 
 #ifdef _M_ARM_64EC
   ValidMultiblockMember = ValidMultiblockMember && !RtlIsEcCode(TargetRIP);
@@ -1143,6 +1072,9 @@ void Decoder::BranchTargetInMultiblockRange() {
     if (Conditional) {
       MaxCondBranchForward = std::max(MaxCondBranchForward, TargetRIP);
       MaxCondBranchBackwards = std::min(MaxCondBranchBackwards, TargetRIP);
+
+      // If we are conditional then a target can be the instruction past the conditional instruction
+      AddBranchTarget(InstEnd);
     }
 
     AddBranchTarget(TargetRIP);
@@ -1153,60 +1085,6 @@ void Decoder::BranchTargetInMultiblockRange() {
   }
 }
 
-bool Decoder::IsBranchMonoTailcall(uint64_t NumInstructions) const {
-  // While the mono call backpatching block can easily be detected due it being the only one to contain SMC-faulting
-  // atomics, that can't be said for the tailcall jump backpatcher which has changed several times across versions and
-  // can be partially inlined. To work around this, instead detect the tailcall site itself and force full non-signal-based
-  // SMC detection for that single block.
-  if (!ExecutableRangeWritable) {
-    // We only care about jitted code
-    return false;
-  }
-
-  // See mini-{amd64,x86}.c in the mono codebase, specifically where METHOD_JUMP patches are emitted.
-  if (GetGPROpSize() == IR::OpSize::i32Bit) {
-    // Matches:
-    // LEAVE
-    // <none> / NOP / MOV EAX, EAX / LEA EBP, [EBP+0]
-    // JMP imm32
-    if (DecodeInst->OP != 0xE9 || NumInstructions < 2) {
-      return false;
-    }
-
-    auto PrevInst = std::prev(DecodeInst);
-    if (PrevInst->OP == 0xC9) {
-      return true;
-    }
-
-    if (NumInstructions < 3 || std::prev(PrevInst)->OP != 0xC9) {
-      return false;
-    }
-
-    return PrevInst->OP == 0x90 || (PrevInst->OP == 0x8B && PrevInst->ModRM == 0xC0) ||
-           (PrevInst->OP == 0x8D && PrevInst->ModRM == 0x6D && PrevInst->Src[1].IsLiteral() && PrevInst->Src[1].Literal() == 0);
-  } else {
-    FEXCore::X86Tables::ModRMDecoded ModRM;
-    ModRM.Hex = DecodeInst->ModRM;
-    if (DecodeInst->OPRaw == 0xFF && ModRM.reg == 4 && DecodeInst->Src[0].IsGPR()) {
-      if (DecodeInst->Src[0].Data.GPR.GPR == FEXCore::X86State::REG_RAX) {
-        // Found in versions of mono from 2024 onwards - matches:
-        // REX.W JMP rax
-        return (DecodeInst->Flags & (DecodeFlags::FLAG_REX_PREFIX | DecodeFlags::FLAG_REX_WIDENING | DecodeFlags::FLAG_REX_XGPR_B |
-                                     DecodeFlags::FLAG_REX_XGPR_X | DecodeFlags::FLAG_REX_XGPR_R)) ==
-               (DecodeFlags::FLAG_REX_PREFIX | DecodeFlags::FLAG_REX_WIDENING);
-      } else if (NumInstructions > 1 && DecodeInst->Src[0].Data.GPR.GPR == FEXCore::X86State::REG_R11) {
-        // Found in older versions of mono - match:
-        // MOV r11, imm64
-        // JMP r11
-        auto PrevInst = std::prev(DecodeInst);
-        return PrevInst->OP == 0xBB && PrevInst->Dest.IsGPR() && PrevInst->Dest.Data.GPR.GPR == FEXCore::X86State::REG_R11;
-      }
-    }
-  }
-
-  return false;
-}
-
 bool Decoder::InstCanContinue() const {
   if (DecodeInst->PC + DecodeInst->InstSize == NextBlockStartAddress) {
     return false;
@@ -1309,7 +1187,7 @@ const uint8_t* Decoder::AdjustAddrForSpecialRegion(const uint8_t* _InstStream, u
   return _InstStream - EntryPoint + RIP;
 }
 
-void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thread, const uint8_t* _InstStream, uint64_t PC, uint64_t MaxInst) {
+void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, const uint8_t* _InstStream, uint64_t PC, uint64_t MaxInst) {
   FEXCORE_PROFILE_SCOPED("DecodeInstructions");
   BlockInfo.TotalInstructionCount = 0;
   BlockInfo.Blocks.clear();
@@ -1321,8 +1199,8 @@ void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thre
   DecodedBuffer = PoolObject.ReownOrClaimBuffer();
 
   // Decode operating mode from thread's CS segment.
-  const auto CSSegment = Core::CPUState::GetSegmentFromIndex(Thread->CurrentFrame->State, Thread->CurrentFrame->State.cs_idx);
-  BlockInfo.Is64BitMode = CSSegment->L == 1;
+  const auto CSSegment = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3];
+  BlockInfo.Is64BitMode = CSSegment.L == 1;
   LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!");
 
   // XXX: Load symbol data
@@ -1467,7 +1345,6 @@ void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thre
           // If the branch target is within our multiblock range then we can keep going on
           // We don't want to short circuit this since we want to calculate our ranges still
           // NOTE: This will invalidate BlockIt, this is fine as we immediately break from the loop and EraseBlock cannot be true
-          BlockIt->ForceFullSMCDetection = CTX->AreMonoHacksActive() && IsBranchMonoTailcall(BlockIt->NumInstructions);
           BranchTargetInMultiblockRange();
         }
 

FEXCore/Source/Interface/Core/Frontend.h

@@ -4,21 +4,18 @@
 #include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/IR/IR.h"
 
-#include <FEXCore/Utils/ThreadPoolAllocator.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+#include <FEXCore/Utils/Telemetry.h>
 #include <FEXCore/fextl/set.h>
 #include <FEXCore/fextl/vector.h>
 
 #include <array>
-#include <cstddef>
 #include <cstdint>
-#include <optional>
+#include <stddef.h>
 
 namespace FEXCore::Context {
 class ContextImpl;
 }
-namespace FEXCore::HLE {
-enum class SyscallOSABI;
-}
 
 namespace FEXCore::Frontend {
 class Decoder final {
@@ -37,7 +34,6 @@ public:
     FEXCore::X86Tables::DecodedInst* DecodedInstructions;
     DecodedBlockStatus BlockStatus;
     bool IsEntryPoint {};
-    bool ForceFullSMCDetection {};
   };
 
   struct DecodedBlockInformation final {
@@ -49,7 +45,7 @@ public:
   };
 
   Decoder(FEXCore::Core::InternalThreadState* Thread);
-  void DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thread, const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst);
+  void DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst);
 
   const DecodedBlockInformation* GetDecodedBlockInfo() const {
     return &BlockInfo;
@@ -90,7 +86,6 @@ private:
   DecodedBlockStatus DecodeInstruction(uint64_t PC);
 
   void BranchTargetInMultiblockRange();
-  bool IsBranchMonoTailcall(uint64_t NumInstructions) const;
   bool InstCanContinue() const;
 
   void AddBranchTarget(uint64_t Target);
@@ -114,7 +109,6 @@ private:
 
   uint64_t ExecutableRangeBase {};
   uint64_t ExecutableRangeEnd {};
-  bool ExecutableRangeWritable {};
   bool HitNonExecutableRange {};
 
   const uint8_t* InstStream {};
@@ -125,7 +119,6 @@ private:
   static constexpr size_t MAX_INST_SIZE = 15;
   uint8_t InstructionSize {};
   std::array<uint8_t, MAX_INST_SIZE> Instruction;
-  uint8_t LastEscapePrefix {};
   FEXCore::X86Tables::DecodedInst* DecodeInst;
 
   // This is for multiblock data tracking
@@ -154,11 +147,6 @@ private:
     &FEXCore::Frontend::Decoder::DecodeModRM_16,
   };
 
-  const std::array<X86Tables::X86InstInfo, X86Tables::MAX_X87_TABLE_SIZE>* X87Table;
-
-  const std::array<X86Tables::X86InstInfo, X86Tables::MAX_VEX_TABLE_SIZE>* VEXTable {};
-  const std::array<X86Tables::X86InstInfo, X86Tables::MAX_VEX_GROUP_TABLE_SIZE>* VEXTableGroup {};
-
   const uint8_t* AdjustAddrForSpecialRegion(const uint8_t* _InstStream, uint64_t EntryPoint, uint64_t RIP);
 };
 } // namespace FEXCore::Frontend

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h

@@ -340,7 +340,7 @@ struct OpHandlers<IR::OP_F80SCALE> {
 
 template<>
 struct OpHandlers<IR::OP_F64SIN> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return sin(src);
   }
@@ -348,7 +348,7 @@ struct OpHandlers<IR::OP_F64SIN> {
 
 template<>
 struct OpHandlers<IR::OP_F64COS> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return cos(src);
   }
@@ -356,7 +356,7 @@ struct OpHandlers<IR::OP_F64COS> {
 
 template<>
 struct OpHandlers<IR::OP_F64SINCOS> {
-  FEXCORE_PRESERVE_ALL_ATTR static VectorScalarF64Pair handle(double src, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static VectorScalarF64Pair handle(uint16_t FCW, double src, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     double sin, cos;
 #ifdef _WIN32
@@ -371,7 +371,7 @@ struct OpHandlers<IR::OP_F64SINCOS> {
 
 template<>
 struct OpHandlers<IR::OP_F64TAN> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return tan(src);
   }
@@ -379,7 +379,7 @@ struct OpHandlers<IR::OP_F64TAN> {
 
 template<>
 struct OpHandlers<IR::OP_F64F2XM1> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return exp2(src) - 1.0;
   }
@@ -387,7 +387,7 @@ struct OpHandlers<IR::OP_F64F2XM1> {
 
 template<>
 struct OpHandlers<IR::OP_F64ATAN> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return atan2(src1, src2);
   }
@@ -395,7 +395,7 @@ struct OpHandlers<IR::OP_F64ATAN> {
 
 template<>
 struct OpHandlers<IR::OP_F64FPREM> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return fmod(src1, src2);
   }
@@ -403,7 +403,7 @@ struct OpHandlers<IR::OP_F64FPREM> {
 
 template<>
 struct OpHandlers<IR::OP_F64FPREM1> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return remainder(src1, src2);
   }
@@ -411,7 +411,7 @@ struct OpHandlers<IR::OP_F64FPREM1> {
 
 template<>
 struct OpHandlers<IR::OP_F64FYL2X> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     return src2 * log2(src1);
   }
@@ -419,7 +419,7 @@ struct OpHandlers<IR::OP_F64FYL2X> {
 
 template<>
 struct OpHandlers<IR::OP_F64SCALE> {
-  FEXCORE_PRESERVE_ALL_ATTR static double handle(double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
+  FEXCORE_PRESERVE_ALL_ATTR static double handle(uint16_t FCW, double src1, double src2, FEXCore::Core::CpuStateFrame* Frame) {
     FEXCORE_PROFILE_INSTANT_INCREMENT(Frame->Thread, AccumulatedFloatFallbackCount, 1);
     if (src1 == 0.0) { // src1 might be +/- zero
       return src1;     // this will return negative or positive zero if when appropriate
@@ -445,6 +445,7 @@ struct OpHandlers<IR::OP_F80BCDSTORE> {
     uint64_t Tmp = Src1.ToI64(&State.State);
     X80SoftFloat Rv;
     uint8_t* BCD = reinterpret_cast<uint8_t*>(&Rv);
+    memset(BCD, 0, 10);
 
     for (size_t i = 0; i < 9; ++i) {
       if (Tmp == 0) {

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp

@@ -82,22 +82,24 @@ void InterpreterOps::FillFallbackIndexPointers(Core::FallbackABIInfo* Info, uint
                                   reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle)};
 
   // Double Precision Unary
-  Info[Core::OPINDEX_F64SIN] = {ABIHandlers[FABI_F64_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle)};
-  Info[Core::OPINDEX_F64COS] = {ABIHandlers[FABI_F64_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle)};
-  Info[Core::OPINDEX_F64SINCOS] = {ABIHandlers[FABI_F64x2_F64_PTR],
+  Info[Core::OPINDEX_F64SIN] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle)};
+  Info[Core::OPINDEX_F64COS] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle)};
+  Info[Core::OPINDEX_F64SINCOS] = {ABIHandlers[FABI_F64x2_I16_F64_PTR],
                                    reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SINCOS>::handle)};
-  Info[Core::OPINDEX_F64TAN] = {ABIHandlers[FABI_F64_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle)};
-  Info[Core::OPINDEX_F64F2XM1] = {ABIHandlers[FABI_F64_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle)};
+  Info[Core::OPINDEX_F64TAN] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle)};
+  Info[Core::OPINDEX_F64F2XM1] = {ABIHandlers[FABI_F64_I16_F64_PTR],
+                                  reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle)};
 
   // Double Precision Binary
-  Info[Core::OPINDEX_F64ATAN] = {ABIHandlers[FABI_F64_F64_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle)};
-  Info[Core::OPINDEX_F64FPREM] = {ABIHandlers[FABI_F64_F64_F64_PTR],
+  Info[Core::OPINDEX_F64ATAN] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
+                                 reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle)};
+  Info[Core::OPINDEX_F64FPREM] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
                                   reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle)};
-  Info[Core::OPINDEX_F64FPREM1] = {ABIHandlers[FABI_F64_F64_F64_PTR],
+  Info[Core::OPINDEX_F64FPREM1] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
                                    reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle)};
-  Info[Core::OPINDEX_F64FYL2X] = {ABIHandlers[FABI_F64_F64_F64_PTR],
+  Info[Core::OPINDEX_F64FYL2X] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
                                   reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle)};
-  Info[Core::OPINDEX_F64SCALE] = {ABIHandlers[FABI_F64_F64_F64_PTR],
+  Info[Core::OPINDEX_F64SCALE] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
                                   reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle)};
 
   // SSE4.2 string instructions
@@ -218,21 +220,21 @@ bool InterpreterOps::GetFallbackHandler(const IR::IROp_Header* IROp, FallbackInf
     return true;                                                                                       \
   }
 
-#define COMMON_UNARY_F64_OP(OP)                        \
-  case IR::OP_F64##OP: {                               \
-    *Info = {FABI_F64_F64_PTR, Core::OPINDEX_F64##OP}; \
-    return true;                                       \
+#define COMMON_UNARY_F64_OP(OP)                            \
+  case IR::OP_F64##OP: {                                   \
+    *Info = {FABI_F64_I16_F64_PTR, Core::OPINDEX_F64##OP}; \
+    return true;                                           \
   }
-#define COMMON_UNARYPAIR_F64_OP(OP)                      \
-  case IR::OP_F64##OP: {                                 \
-    *Info = {FABI_F64x2_F64_PTR, Core::OPINDEX_F64##OP}; \
-    return true;                                         \
+#define COMMON_UNARYPAIR_F64_OP(OP)                          \
+  case IR::OP_F64##OP: {                                     \
+    *Info = {FABI_F64x2_I16_F64_PTR, Core::OPINDEX_F64##OP}; \
+    return true;                                             \
   }
 
-#define COMMON_BINARY_F64_OP(OP)                           \
-  case IR::OP_F64##OP: {                                   \
-    *Info = {FABI_F64_F64_F64_PTR, Core::OPINDEX_F64##OP}; \
-    return true;                                           \
+#define COMMON_BINARY_F64_OP(OP)                               \
+  case IR::OP_F64##OP: {                                       \
+    *Info = {FABI_F64_I16_F64_F64_PTR, Core::OPINDEX_F64##OP}; \
+    return true;                                               \
   }
 
     // Unary

FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -19,8 +19,8 @@ enum FallbackABI {
   FABI_F80_I16_I32_PTR,
   FABI_F32_I16_F80_PTR,
   FABI_F64_I16_F80_PTR,
-  FABI_F64_F64_PTR,
-  FABI_F64_F64_F64_PTR,
+  FABI_F64_I16_F64_PTR,
+  FABI_F64_I16_F64_F64_PTR,
   FABI_I16_I16_F80_PTR,
   FABI_I32_I16_F80_PTR,
   FABI_I64_I16_F80_PTR,
@@ -28,7 +28,7 @@ enum FallbackABI {
   FABI_F80_I16_F80_PTR,
   FABI_F80_I16_F80_F80_PTR,
   FABI_F80x2_I16_F80_PTR,
-  FABI_F64x2_F64_PTR,
+  FABI_F64x2_I16_F64_PTR,
   FABI_I32_I64_I64_V128_V128_I16,
   FABI_I32_V128_V128_I16,
   FABI_UNKNOWN,

FEXCore/Source/Interface/Core/JIT/ALUOps.cpp

@@ -515,12 +515,6 @@ DEF_OP(AndWithFlags) {
   }
 }
 
-DEF_OP(AndShift) {
-  auto Op = IROp->C<IR::IROp_XorShift>();
-
-  and_(ConvertSize48(IROp), GetReg(Node), GetReg(Op->Src1), GetReg(Op->Src2), ConvertIRShiftType(Op->Shift), Op->ShiftAmount);
-}
-
 DEF_OP(XorShift) {
   auto Op = IROp->C<IR::IROp_XorShift>();
 
@@ -588,7 +582,7 @@ DEF_OP(ShiftFlags) {
   and_(ARMEmitter::Size::i32Bit, TMP1, Src2, OpSize == IR::OpSize::i64Bit ? 0x3f : 0x1f);
 
   ARMEmitter::ForwardLabel Done;
-  (void)cbz(EmitSize, TMP1, &Done);
+  cbz(EmitSize, TMP1, &Done);
   {
     // PF/SF/ZF/OF
     if (OpSize >= IR::OpSize::i32Bit) {
@@ -652,7 +646,7 @@ DEF_OP(ShiftFlags) {
       msr(ARMEmitter::SystemRegister::NZCV, TMP2);
     }
   }
-  (void)Bind(&Done);
+  Bind(&Done);
 
   // TODO: Make RA less dumb so this can't happen (e.g. with late-kill).
   if (PFOutput != PFTemp) {
@@ -669,7 +663,7 @@ DEF_OP(RotateFlags) {
 
   // If shift=0, flags are unaffected. Wrap the whole implementation in a cbz.
   ARMEmitter::ForwardLabel Done;
-  (void)cbz(EmitSize, Shift, &Done);
+  cbz(EmitSize, Shift, &Done);
   {
     // Extract the last bit shifted in to CF
     const auto BitSize = IR::OpSizeToSize(Op->Size) * 8;
@@ -701,7 +695,7 @@ DEF_OP(RotateFlags) {
       msr(ARMEmitter::SystemRegister::NZCV, TMP3);
     }
   }
-  (void)Bind(&Done);
+  Bind(&Done);
 }
 
 DEF_OP(Extr) {
@@ -767,14 +761,14 @@ DEF_OP(PDep) {
     // Now, they're copied, so we can start setting Dest (even if it overlaps with
     // one of them).  Handle early exit case
     mov(EmitSize, Dest, 0);
-    (void)cbz(EmitSize, OrigMask, &Done);
+    cbz(EmitSize, OrigMask, &Done);
 
     // Setup for first iteration
     neg(EmitSize, T0, Mask);
     and_(EmitSize, T0, T0, Mask);
 
     // Main loop
-    (void)Bind(&NextBit);
+    Bind(&NextBit);
     sbfx(EmitSize, T1, Input, 0, 1);
     eor(EmitSize, Mask, Mask, T0);
     and_(EmitSize, T0, T1, T0);
@@ -782,10 +776,10 @@ DEF_OP(PDep) {
     orr(EmitSize, Dest, Dest, T0);
     lsr(EmitSize, Input, Input, 1);
     and_(EmitSize, T0, Mask, T1);
-    (void)cbnz(EmitSize, T0, &NextBit);
+    cbnz(EmitSize, T0, &NextBit);
 
     // All done with nothing to do.
-    (void)Bind(&Done);
+    Bind(&Done);
   }
 }
 
@@ -821,27 +815,27 @@ DEF_OP(PExt) {
     ARMEmitter::BackwardLabel NextBit;
     ARMEmitter::ForwardLabel Done;
 
-    (void)cbz(EmitSize, Mask, &EarlyExit);
+    cbz(EmitSize, Mask, &EarlyExit);
     mov(EmitSize, MaskReg, Mask);
     mov(EmitSize, ValueReg, Input);
     mov(EmitSize, Dest, ARMEmitter::Reg::zr);
 
     // Main loop
-    (void)Bind(&NextBit);
-    (void)cbz(EmitSize, MaskReg, &Done);
+    Bind(&NextBit);
+    cbz(EmitSize, MaskReg, &Done);
     clz(EmitSize, BitReg, MaskReg);
     lslv(EmitSize, ValueReg, ValueReg, BitReg);
     lslv(EmitSize, MaskReg, MaskReg, BitReg);
     extr(EmitSize, Dest, Dest, ValueReg, OpSizeBitsM1);
     bfc(EmitSize, MaskReg, OpSizeBitsM1, 1);
-    (void)b(&NextBit);
+    b(&NextBit);
 
     // Early exit
-    (void)Bind(&EarlyExit);
+    Bind(&EarlyExit);
     mov(EmitSize, Dest, ARMEmitter::Reg::zr);
 
     // All done with nothing to do.
-    (void)Bind(&Done);
+    Bind(&Done);
   }
 }
 
@@ -909,7 +903,7 @@ DEF_OP(Div) {
     eor(EmitSize, TMP1, TMP1, Upper);
 
     // If the sign bit matches then the result is zero
-    (void)cbz(EmitSize, TMP1, &Only64Bit);
+    cbz(EmitSize, TMP1, &Only64Bit);
 
     // Long divide
     {
@@ -928,17 +922,17 @@ DEF_OP(Div) {
       mov(EmitSize, Remainder, TMP2);
 
       // Skip 64-bit path
-      (void)b(&LongDIVRet);
+      b(&LongDIVRet);
     }
 
-    (void)Bind(&Only64Bit);
+    Bind(&Only64Bit);
     // 64-Bit only
     {
       sdiv(EmitSize, Quotient, Lower, Divisor);
       msub(EmitSize, Remainder, Quotient, Divisor, Lower);
     }
 
-    (void)Bind(&LongDIVRet);
+    Bind(&LongDIVRet);
     break;
   }
   default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", OpSize); break;
@@ -992,7 +986,7 @@ DEF_OP(UDiv) {
 
     // Check the upper bits for zero
     // If the upper bits are zero then we can do a 64-bit divide
-    (void)cbz(EmitSize, Upper, &Only64Bit);
+    cbz(EmitSize, Upper, &Only64Bit);
 
     // Long divide
     {
@@ -1011,17 +1005,17 @@ DEF_OP(UDiv) {
       mov(EmitSize, Remainder, TMP2);
 
       // Skip 64-bit path
-      (void)b(&LongDIVRet);
+      b(&LongDIVRet);
     }
 
-    (void)Bind(&Only64Bit);
+    Bind(&Only64Bit);
     // 64-Bit only
     {
       udiv(EmitSize, Quotient, Lower, Divisor);
       msub(EmitSize, Remainder, Quotient, Divisor, Lower);
     }
 
-    (void)Bind(&LongDIVRet);
+    Bind(&LongDIVRet);
     break;
   }
   default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", OpSize); break;
@@ -1046,19 +1040,24 @@ DEF_OP(Popcount) {
 
   if (CTX->HostFeatures.SupportsCSSC) {
     switch (OpSize) {
-    case IR::OpSize::i8Bit:
-      uxtb(ARMEmitter::Size::i32Bit, Dst, Src);
-      cnt(ARMEmitter::Size::i32Bit, Dst, Dst);
-      break;
-    case IR::OpSize::i16Bit:
-      uxth(ARMEmitter::Size::i32Bit, Dst, Src);
-      cnt(ARMEmitter::Size::i32Bit, Dst, Dst);
-      break;
-    case IR::OpSize::i32Bit: cnt(ARMEmitter::Size::i32Bit, Dst, Src); break;
-    case IR::OpSize::i64Bit: cnt(ARMEmitter::Size::i64Bit, Dst, Src); break;
-    default: LOGMAN_MSG_A_FMT("Unsupported Popcount size: {}", OpSize);
+      case IR::OpSize::i8Bit:
+        uxtb(ARMEmitter::Size::i32Bit, Dst, Src);
+        cnt(ARMEmitter::Size::i32Bit, Dst, Dst);
+        break;
+      case IR::OpSize::i16Bit:
+        uxth(ARMEmitter::Size::i32Bit, Dst, Src);
+        cnt(ARMEmitter::Size::i32Bit, Dst, Dst);
+        break;
+      case IR::OpSize::i32Bit:
+        cnt(ARMEmitter::Size::i32Bit, Dst, Src);
+        break;
+      case IR::OpSize::i64Bit:
+        cnt(ARMEmitter::Size::i64Bit, Dst, Src);
+        break;
+      default: LOGMAN_MSG_A_FMT("Unsupported Popcount size: {}", OpSize);
     }
-  } else {
+  }
+  else {
     switch (OpSize) {
     case IR::OpSize::i8Bit:
       fmov(ARMEmitter::Size::i32Bit, VTMP1.S(), Src);
@@ -1369,12 +1368,12 @@ DEF_OP(VExtractToGPR) {
   const auto Op = IROp->C<IR::IROp_VExtractToGPR>();
   const auto OpSize = IROp->Size;
 
-  constexpr auto AVXRegBitSize = Core::CPUState::XMM_AVX_REG_SIZE * 8;
+  [[maybe_unused]] constexpr auto AVXRegBitSize = Core::CPUState::XMM_AVX_REG_SIZE * 8;
   constexpr auto SSERegBitSize = Core::CPUState::XMM_SSE_REG_SIZE * 8;
   const auto ElementSizeBits = IR::OpSizeAsBits(Op->Header.ElementSize);
 
   const auto Offset = ElementSizeBits * Op->Index;
-  const auto Is256Bit = Offset >= SSERegBitSize;
+  [[maybe_unused]] const auto Is256Bit = Offset >= SSERegBitSize;
   LOGMAN_THROW_A_FMT(!Is256Bit || HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
 
   const auto Dst = GetReg(Node);

FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp

@@ -33,7 +33,7 @@ void Arm64JITCore::InsertNamedThunkRelocation(ARMEmitter::Register Reg, const IR
 
   uint64_t Pointer = reinterpret_cast<uint64_t>(EmitterCTX->ThunkHandler->LookupThunk(Sum));
 
-  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Pointer, false);
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Pointer, EmitterCTX->Config.CacheObjectCodeCompilation());
   Relocations.emplace_back(MoveABI);
 }
 
@@ -63,7 +63,7 @@ void Arm64JITCore::PlaceNamedSymbolLiteral(NamedSymbolLiteralPair& Lit) {
   auto CurrentCursor = GetCursorAddress<uint8_t*>();
   Lit.MoveABI.NamedSymbolLiteral.Offset = CurrentCursor - CodeData.BlockBegin;
 
-  BindOrRestart(&Lit.Loc);
+  Bind(&Lit.Loc);
   dc64(Lit.Lit);
   Relocations.emplace_back(Lit.MoveABI);
 }
@@ -77,36 +77,39 @@ void Arm64JITCore::InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constan
   MoveABI.GuestRIPMove.GuestRIP = Constant;
   MoveABI.GuestRIPMove.RegisterIndex = Reg.Idx();
 
-  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Constant, false);
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Constant, EmitterCTX->Config.CacheObjectCodeCompilation());
   Relocations.emplace_back(MoveABI);
 }
 
-bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, std::span<std::byte> Code, std::span<const FEXCore::CPU::Relocation> Relocations) {
-  const auto OrigBase = GetBufferBase();
-  const auto OrigSize = GetBufferSize();
-  const auto OrigOffset = GetCursorOffset();
+bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations,
+                                    const char* EntryRelocations) {
+  size_t DataIndex {};
+  for (size_t j = 0; j < NumRelocations; ++j) {
+    const FEXCore::CPU::Relocation* Reloc = reinterpret_cast<const FEXCore::CPU::Relocation*>(&EntryRelocations[DataIndex]);
+    LOGMAN_THROW_A_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
 
-  SetBuffer(reinterpret_cast<std::uint8_t*>(Code.data()), Code.size_bytes());
-  for (auto& Reloc : Relocations) {
-    switch (Reloc.Header.Type) {
+    switch (Reloc->Header.Type) {
     case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: {
-      uint64_t Pointer = GetNamedSymbolLiteral(Reloc.NamedSymbolLiteral.Symbol);
+      uint64_t Pointer = GetNamedSymbolLiteral(Reloc->NamedSymbolLiteral.Symbol);
       // Relocation occurs at the cursorEntry + offset relative to that cursor
-      SetCursorOffset(Reloc.NamedSymbolLiteral.Offset);
+      SetCursorOffset(CursorEntry + Reloc->NamedSymbolLiteral.Offset);
 
       // Generate a literal so we can place it
       dc64(Pointer);
+
+      DataIndex += sizeof(Reloc->NamedSymbolLiteral);
       break;
     }
     case FEXCore::CPU::RelocationTypes::RELOC_NAMED_THUNK_MOVE: {
-      uint64_t Pointer = reinterpret_cast<uint64_t>(EmitterCTX->ThunkHandler->LookupThunk(Reloc.NamedThunkMove.Symbol));
+      uint64_t Pointer = reinterpret_cast<uint64_t>(EmitterCTX->ThunkHandler->LookupThunk(Reloc->NamedThunkMove.Symbol));
       if (Pointer == ~0ULL) {
         return false;
       }
 
       // Relocation occurs at the cursorEntry + offset relative to that cursor.
-      SetCursorOffset(Reloc.NamedThunkMove.Offset);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.NamedThunkMove.RegisterIndex), Pointer, true);
+      SetCursorOffset(CursorEntry + Reloc->NamedThunkMove.Offset);
+      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc->NamedThunkMove.RegisterIndex), Pointer, true);
+      DataIndex += sizeof(Reloc->NamedThunkMove);
       break;
     }
     case FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_MOVE: {
@@ -114,27 +117,18 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, std::span<std::byte> Co
       // XXX: Should spin the relocation list, create a list of guest RIP moves, and ask for them all once, reduces lock contention.
       uint64_t Pointer = ~0ULL; // EmitterCTX->JITObjectCache->FindRelocatedRIP(Reloc->GuestRIPMove.GuestRIP);
       if (Pointer == ~0ULL) {
-        SetBuffer(OrigBase, OrigSize);
-        SetCursorOffset(OrigOffset);
         return false;
       }
 
       // Relocation occurs at the cursorEntry + offset relative to that cursor.
-      SetCursorOffset(Reloc.GuestRIPMove.Offset);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.GuestRIPMove.RegisterIndex), Pointer, true);
+      SetCursorOffset(CursorEntry + Reloc->GuestRIPMove.Offset);
+      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc->GuestRIPMove.RegisterIndex), Pointer, true);
+      DataIndex += sizeof(Reloc->GuestRIPMove);
       break;
     }
     }
   }
 
-  SetBuffer(OrigBase, OrigSize);
-  SetCursorOffset(OrigOffset);
-
   return true;
 }
-
-fextl::vector<FEXCore::CPU::Relocation> Arm64JITCore::TakeRelocations() {
-  return std::move(Relocations);
-}
-
 } // namespace FEXCore::CPU

FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp

@@ -62,27 +62,27 @@ DEF_OP(CASPair) {
     ARMEmitter::BackwardLabel LoopTop;
     ARMEmitter::ForwardLabel LoopNotExpected;
     ARMEmitter::ForwardLabel LoopExpected;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
 
     // This instruction sequence must be synced with HandleCASPAL_Armv8.
     ldaxp(EmitSize, TMP2, TMP3, MemSrc);
     cmp(EmitSize, TMP2, Expected0);
     ccmp(EmitSize, TMP3, Expected1, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
-    (void)b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
+    b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
     stlxp(EmitSize, TMP2, Desired0, Desired1, MemSrc);
-    (void)cbnz(EmitSize, TMP2, &LoopTop);
+    cbnz(EmitSize, TMP2, &LoopTop);
     mov(EmitSize, Dst0, Expected0);
     mov(EmitSize, Dst1, Expected1);
 
-    (void)b(&LoopExpected);
+    b(&LoopExpected);
 
-    (void)Bind(&LoopNotExpected);
+    Bind(&LoopNotExpected);
     mov(EmitSize, Dst0, TMP2.R());
     mov(EmitSize, Dst1, TMP3.R());
     // exclusive monitor needs to be cleared here
     // Might have hit the case where ldaxr was hit but stlxr wasn't
     clrex();
-    (void)Bind(&LoopExpected);
+    Bind(&LoopExpected);
 
     // Restore
     msr(ARMEmitter::SystemRegister::NZCV, TMP1);
@@ -114,7 +114,7 @@ DEF_OP(CAS) {
     ARMEmitter::BackwardLabel LoopTop;
     ARMEmitter::ForwardLabel LoopNotExpected;
     ARMEmitter::ForwardLabel LoopExpected;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     if (IROp->Size == IR::OpSize::i8Bit) {
       cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTB, 0);
@@ -123,18 +123,18 @@ DEF_OP(CAS) {
     } else {
       cmp(EmitSize, TMP2, Expected);
     }
-    (void)b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
+    b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
     stlxr(SubEmitSize, TMP3, Desired, MemSrc);
-    (void)cbnz(EmitSize, TMP3, &LoopTop);
+    cbnz(EmitSize, TMP3, &LoopTop);
     mov(EmitSize, Dst, Expected);
-    (void)b(&LoopExpected);
+    b(&LoopExpected);
 
-    (void)Bind(&LoopNotExpected);
+    Bind(&LoopNotExpected);
     mov(EmitSize, Dst, TMP2.R());
     // exclusive monitor needs to be cleared here
     // Might have hit the case where ldaxr was hit but stlxr wasn't
     clrex();
-    (void)Bind(&LoopExpected);
+    Bind(&LoopExpected);
   }
 }
 
@@ -150,11 +150,11 @@ DEF_OP(AtomicXor) {
     steorl(SubEmitSize, Src, MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     eor(EmitSize, TMP2, TMP2, Src);
     stlxr(SubEmitSize, TMP2, TMP2, MemSrc);
-    (void)cbnz(EmitSize, TMP2, &LoopTop);
+    cbnz(EmitSize, TMP2, &LoopTop);
   }
 }
 
@@ -179,10 +179,10 @@ DEF_OP(AtomicSwap) {
     ldswpal(SubEmitSize, Src, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     stlxr(SubEmitSize, TMP4, Src, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     ubfm(EmitSize, GetReg(Node), TMP2, 0, IR::OpSizeAsBits(OpSize) - 1);
   }
 }
@@ -199,11 +199,11 @@ DEF_OP(AtomicFetchAdd) {
     ldaddal(SubEmitSize, Src, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     add(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -221,11 +221,11 @@ DEF_OP(AtomicFetchSub) {
     ldaddal(SubEmitSize, TMP2, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     sub(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -243,11 +243,11 @@ DEF_OP(AtomicFetchAnd) {
     ldclral(SubEmitSize, TMP2, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     and_(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -264,11 +264,11 @@ DEF_OP(AtomicFetchCLR) {
     ldclral(SubEmitSize, Src, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     bic(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -285,11 +285,11 @@ DEF_OP(AtomicFetchOr) {
     ldsetal(SubEmitSize, Src, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     orr(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -306,11 +306,11 @@ DEF_OP(AtomicFetchXor) {
     ldeoral(SubEmitSize, Src, GetReg(Node), MemSrc);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(SubEmitSize, TMP2, MemSrc);
     eor(EmitSize, TMP3, TMP2, Src);
     stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
+    cbnz(EmitSize, TMP4, &LoopTop);
     mov(EmitSize, GetReg(Node), TMP2.R());
   }
 }
@@ -322,26 +322,13 @@ DEF_OP(AtomicFetchNeg) {
 
   auto MemSrc = GetReg(Op->Addr);
 
-  if (CTX->HostFeatures.SupportsAtomics) {
-    // Use a CAS loop to avoid needing to emulate unaligned LLSC atomics
-    ldr(SubEmitSize, TMP2, MemSrc);
-    ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
-    mov(EmitSize, TMP4, TMP2);
-    neg(EmitSize, TMP3, TMP2);
-    casal(SubEmitSize, TMP2, TMP3, MemSrc);
-    sub(EmitSize, TMP3, TMP2, TMP4);
-    (void)cbnz(EmitSize, TMP3, &LoopTop);
-    mov(EmitSize, GetReg(Node), TMP2.R());
-  } else {
-    ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
-    ldaxr(SubEmitSize, TMP2, MemSrc);
-    neg(EmitSize, TMP3, TMP2);
-    stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
-    (void)cbnz(EmitSize, TMP4, &LoopTop);
-    mov(EmitSize, GetReg(Node), TMP2.R());
-  }
+  ARMEmitter::BackwardLabel LoopTop;
+  Bind(&LoopTop);
+  ldaxr(SubEmitSize, TMP2, MemSrc);
+  neg(EmitSize, TMP3, TMP2);
+  stlxr(SubEmitSize, TMP4, TMP3, MemSrc);
+  cbnz(EmitSize, TMP4, &LoopTop);
+  mov(EmitSize, GetReg(Node), TMP2.R());
 }
 
 DEF_OP(TelemetrySetValue) {
@@ -359,11 +346,11 @@ DEF_OP(TelemetrySetValue) {
     stsetl(ARMEmitter::SubRegSize::i64Bit, TMP1, TMP2);
   } else {
     ARMEmitter::BackwardLabel LoopTop;
-    (void)Bind(&LoopTop);
+    Bind(&LoopTop);
     ldaxr(ARMEmitter::SubRegSize::i64Bit, TMP3, TMP2);
     orr(ARMEmitter::Size::i32Bit, TMP3, TMP3, Src);
     stlxr(ARMEmitter::SubRegSize::i64Bit, TMP3, TMP3, TMP2);
-    (void)cbnz(ARMEmitter::Size::i32Bit, TMP3, &LoopTop);
+    cbnz(ARMEmitter::Size::i32Bit, TMP3, &LoopTop);
   }
 #endif
 }

FEXCore/Source/Interface/Core/JIT/BranchOps.cpp

@@ -141,24 +141,15 @@ DEF_OP(ExitFunction) {
         if (!Op->CallReturnBlock.IsInvalid()) {
           auto CallReturnAddressReg = GetReg(Op->CallReturnAddress).X();
           PendingCallReturnTargetLabel = &CallReturnTargets.try_emplace(Op->CallReturnBlock.ID()).first->second;
-          (void)adr(TMP1, &l_CallReturn);
+          adr(TMP1, &l_CallReturn);
           stp<ARMEmitter::IndexType::PRE>(CallReturnAddressReg, TMP1, REG_CALLRET_SP, -0x10);
         } else {
           stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10);
         }
-      } else if (Op->Hint == IR::BranchHint::CheckTF) {
-        ARMEmitter::ForwardLabel TFUnset;
-        ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
-        (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset);
-        LoadConstant(ARMEmitter::Size::i64Bit, TMP1, NewRIP);
-        str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
-        ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
-        blr(TMP2);
-        (void)Bind(&TFUnset);
       }
 
       EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call);
-      (void)Bind(&l_CallReturn);
+      Bind(&l_CallReturn);
 #ifdef _M_ARM_64EC
     }
 #endif
@@ -170,7 +161,7 @@ DEF_OP(ExitFunction) {
       // First try to pop from the call-ret stack, otherwise follow the normal path (but ending in a ret)
       ldp<ARMEmitter::IndexType::POST>(TMP1, TMP2, REG_CALLRET_SP, 0x10);
       sub(TMP1, TMP1, RipReg.X());
-      (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup);
     }
 
     // L1 Cache
@@ -187,23 +178,23 @@ DEF_OP(ExitFunction) {
 
     // Note: sub+cbnz used over cmp+br to preserve flags.
     sub(TMP1, TMP1, RipReg.X());
-    (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup);
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup);
     ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
     str(RipReg.X(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
 
-    (void)Bind(&SkipFullLookup);
+    Bind(&SkipFullLookup);
     if (Op->Hint == IR::BranchHint::Call) {
       ARMEmitter::ForwardLabel l_CallReturn;
       if (!Op->CallReturnBlock.IsInvalid()) {
         auto CallReturnAddressReg = GetReg(Op->CallReturnAddress).X();
         PendingCallReturnTargetLabel = &CallReturnTargets.try_emplace(Op->CallReturnBlock.ID()).first->second;
-        (void)adr(TMP1, &l_CallReturn);
+        adr(TMP1, &l_CallReturn);
         stp<ARMEmitter::IndexType::PRE>(CallReturnAddressReg, TMP1, REG_CALLRET_SP, -0x10);
       } else {
         stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10);
       }
       blr(TMP2);
-      (void)Bind(&l_CallReturn);
+      Bind(&l_CallReturn);
     } else if (Op->Hint == IR::BranchHint::Return) {
       ret(TMP2);
     } else {
@@ -214,20 +205,21 @@ DEF_OP(ExitFunction) {
 
 DEF_OP(Jump) {
   const auto Op = IROp->C<IR::IROp_Jump>();
+  const auto Target = Op->TargetBlock;
 
-  PendingTargetLabel = JumpTarget(Op->TargetBlock);
+  PendingTargetLabel = &JumpTargets.try_emplace(Target.ID()).first->second;
 }
 
 DEF_OP(CondJump) {
   auto Op = IROp->C<IR::IROp_CondJump>();
 
-  auto TrueTargetLabel = JumpTarget(Op->TrueBlock);
+  auto TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
 
   if (Op->FromNZCV) {
-    b_OrRestart(MapCC(Op->Cond), TrueTargetLabel);
+    b(MapCC(Op->Cond), TrueTargetLabel);
   } else {
-    uint64_t Const;
-    const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
+    [[maybe_unused]] uint64_t Const;
+    [[maybe_unused]] const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
     auto Reg = GetReg(Op->Cmp1);
     const auto Size = Op->CompareSize == IR::OpSize::i32Bit ? ARMEmitter::Size::i32Bit : ARMEmitter::Size::i64Bit;
@@ -237,22 +229,22 @@ DEF_OP(CondJump) {
 
     if (Op->Cond.Val == FEXCore::IR::COND_EQ) {
       LOGMAN_THROW_A_FMT(Const == 0, "CondJump: Expected 0 source");
-      cbz_OrRestart(Size, Reg, TrueTargetLabel);
+      cbz(Size, Reg, TrueTargetLabel);
     } else if (Op->Cond.Val == FEXCore::IR::COND_NEQ) {
       LOGMAN_THROW_A_FMT(Const == 0, "CondJump: Expected 0 source");
-      cbnz_OrRestart(Size, Reg, TrueTargetLabel);
+      cbnz(Size, Reg, TrueTargetLabel);
     } else if (Op->Cond.Val == FEXCore::IR::COND_TSTZ) {
       LOGMAN_THROW_A_FMT(Const < 64, "CondJump: Expected valid bit source");
-      tbz_OrRestart(Reg, Const, TrueTargetLabel);
+      tbz(Reg, Const, TrueTargetLabel);
     } else if (Op->Cond.Val == FEXCore::IR::COND_TSTNZ) {
       LOGMAN_THROW_A_FMT(Const < 64, "CondJump: Expected valid bit source");
-      tbnz_OrRestart(Reg, Const, TrueTargetLabel);
+      tbnz(Reg, Const, TrueTargetLabel);
     } else {
       LOGMAN_THROW_A_FMT(false, "CondJump expected simple condition");
     }
   }
 
-  PendingTargetLabel = JumpTarget(Op->FalseBlock);
+  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
 }
 
 DEF_OP(Syscall) {
@@ -446,50 +438,48 @@ DEF_OP(Thunk) {
 
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  auto OldCode = Op->CodeOriginal.data();
-  auto Base = GetReg(Op->Header.Args[0]).X();
+  const auto* OldCode = (const uint8_t*)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
-  int Offset = 0;
-  ARMEmitter::ForwardLabel Fail;
+  int idx = 0;
+
+  LoadConstant(ARMEmitter::Size::i64Bit, GetReg(Node), 0);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Entry + Op->Offset);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP2, 1);
 
   const auto Dst = GetReg(Node);
 
-  auto EmitCheck = [&](size_t Size, auto&& LoadData) {
-    while (len >= Size) {
-      LoadData();
-      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
-      cbnz_OrRestart(ARMEmitter::Size::i64Bit, TMP1, &Fail);
-      len -= Size;
-      Offset += Size;
-    }
-  };
-
-  EmitCheck(8, [&]() {
-    ldr(TMP1, Base, Offset);
-    LoadConstant(ARMEmitter::Size::i64Bit, TMP2, *(const uint64_t*)(OldCode + Offset));
-  });
-
-  EmitCheck(4, [&]() {
-    ldr(TMP1.W(), Base, Offset);
-    LoadConstant(ARMEmitter::Size::i32Bit, TMP2, *(const uint32_t*)(OldCode + Offset));
-  });
-
-  EmitCheck(2, [&]() {
-    ldrh(TMP1.W(), Base, Offset);
-    LoadConstant(ARMEmitter::Size::i32Bit, TMP2, *(const uint16_t*)(OldCode + Offset));
-  });
-
-  EmitCheck(1, [&]() {
-    ldrb(TMP1.W(), Base, Offset);
-    LoadConstant(ARMEmitter::Size::i32Bit, TMP2, *(const uint8_t*)(OldCode + Offset));
-  });
-
-  ARMEmitter::ForwardLabel End;
-  LoadConstant(ARMEmitter::Size::i32Bit, Dst, 0);
-  b_OrRestart(&End);
-  BindOrRestart(&Fail);
-  LoadConstant(ARMEmitter::Size::i32Bit, Dst, 1);
-  BindOrRestart(&End);
+  while (len >= 8) {
+    ldr(ARMEmitter::XReg::x2, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint64_t*)(OldCode + idx));
+    cmp(ARMEmitter::Size::i64Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
+    len -= 8;
+    idx += 8;
+  }
+  while (len >= 4) {
+    ldr(ARMEmitter::WReg::w2, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint32_t*)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
+    len -= 4;
+    idx += 4;
+  }
+  while (len >= 2) {
+    ldrh(TMP3, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint16_t*)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
+    len -= 2;
+    idx += 2;
+  }
+  while (len >= 1) {
+    ldrb(TMP3, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint8_t*)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
+    len -= 1;
+    idx += 1;
+  }
 }
 
 DEF_OP(ThreadRemoveCodeEntry) {

FEXCore/Source/Interface/Core/JIT/DebugData.h

@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: MIT
-#pragma once
-
-#include <FEXCore/Utils/AllocatorHooks.h>
-#include <FEXCore/fextl/vector.h>
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-union Relocation;
-} // namespace FEXCore::CPU
-
-namespace FEXCore::Core {
-struct DebugDataSubblock {
-  uint32_t HostCodeOffset;
-  uint32_t HostCodeSize;
-};
-
-struct DebugDataGuestOpcode {
-  uint64_t GuestEntryOffset;
-  ptrdiff_t HostEntryOffset;
-};
-
-/**
- * @brief Contains debug data for a block of code for later debugger analysis
- *
- * Needs to remain around for as long as the code could be executed at least
- */
-struct DebugData : public FEXCore::Allocator::FEXAllocOperators {
-  uint64_t HostCodeSize; ///< The size of the code generated in the host JIT
-  fextl::vector<DebugDataSubblock> Subblocks;
-  fextl::vector<DebugDataGuestOpcode> GuestOpcodes;
-  fextl::vector<FEXCore::CPU::Relocation>* Relocations;
-};
-} // namespace FEXCore::Core

FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp

@@ -16,7 +16,7 @@ DEF_OP(VAESImc) {
 
 DEF_OP(VAESEnc) {
   const auto Op = IROp->C<IR::IROp_VAESEnc>();
-  const auto OpSize = IROp->Size;
+  [[maybe_unused]] const auto OpSize = IROp->Size;
 
   const auto Dst = GetVReg(Node);
   const auto Key = GetVReg(Op->Key);
@@ -41,7 +41,7 @@ DEF_OP(VAESEnc) {
 
 DEF_OP(VAESEncLast) {
   const auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  const auto OpSize = IROp->Size;
+  [[maybe_unused]] const auto OpSize = IROp->Size;
 
   const auto Dst = GetVReg(Node);
   const auto Key = GetVReg(Op->Key);
@@ -64,7 +64,7 @@ DEF_OP(VAESEncLast) {
 
 DEF_OP(VAESDec) {
   const auto Op = IROp->C<IR::IROp_VAESDec>();
-  const auto OpSize = IROp->Size;
+  [[maybe_unused]] const auto OpSize = IROp->Size;
 
   const auto Dst = GetVReg(Node);
   const auto Key = GetVReg(Op->Key);
@@ -89,7 +89,7 @@ DEF_OP(VAESDec) {
 
 DEF_OP(VAESDecLast) {
   const auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  const auto OpSize = IROp->Size;
+  [[maybe_unused]] const auto OpSize = IROp->Size;
 
   const auto Dst = GetVReg(Node);
   const auto Key = GetVReg(Op->Key);
@@ -322,7 +322,7 @@ DEF_OP(VSha256U1) {
 
 DEF_OP(PCLMUL) {
   const auto Op = IROp->C<IR::IROp_PCLMUL>();
-  const auto OpSize = IROp->Size;
+  [[maybe_unused]] const auto OpSize = IROp->Size;
 
   const auto Dst = GetVReg(Node);
   const auto Src1 = GetVReg(Op->Src1);

FEXCore/Source/Interface/Core/JIT/JIT.cpp

@@ -11,12 +11,15 @@ desc: Main glue logic of the arm64 splatter backend
 $end_info$
 */
 
+#include "Common/SoftFloat.h"
+#include "FEXCore/Utils/Telemetry.h"
+#include "FEXCore/Utils/TypeDefines.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/JIT/DebugData.h"
 #include "Interface/Core/JIT/JITClass.h"
+
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 #include "Utils/MemberFunctionToPointer.h"
@@ -27,16 +30,15 @@ $end_info$
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/LongJump.h>
 #include <FEXCore/Utils/Profiler.h>
-#include <FEXCore/Utils/Telemetry.h>
-#include <FEXCore/Utils/TypeDefines.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 
-#include <cstdio>
-#include <cstring>
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+
+#include <stdio.h>
 #include <unistd.h>
+#include <string.h>
+#include <limits>
 
 namespace {
 struct DivRem {
@@ -220,7 +222,7 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       FillF64Result();
     } break;
 
-    case FABI_F64_F64_PTR: {
+    case FABI_F64_I16_F64_PTR: {
       // Linux Reg/Win32 Reg:
       // tmp4 (x4/x13): FallbackHandler
       // x30: return
@@ -237,7 +239,7 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
       FillF64Result();
     } break;
-    case FABI_F64x2_F64_PTR: {
+    case FABI_F64x2_I16_F64_PTR: {
       // Linux Reg/Win32 Reg:
       // tmp4 (x4/x13): FallbackHandler
       // x30: return
@@ -262,7 +264,7 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       FillF64x2Result(DstLo, DstHi);
     } break;
 
-    case FABI_F64_F64_F64_PTR: {
+    case FABI_F64_I16_F64_F64_PTR: {
       // Linux Reg/Win32 Reg:
       // tmp4 (x4/x13): FallbackHandler
       // x30: return
@@ -536,8 +538,7 @@ uint64_t Arm64JITCore::ExitFunctionLink(FEXCore::Core::CpuStateFrame* Frame, FEX
   } else {
     {
       // Guard the LookupCache lock with the code invalidation mutex, to avoid issues with forking
-      auto lk_inval =
-        GuardSignalDeferringSection<std::shared_lock>(static_cast<Context::ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
+      auto lk_inval = GuardSignalDeferringSection<std::shared_lock>(static_cast<Context::ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
       HostCode = Thread->LookupCache->FindBlock(GuestRip);
     }
     if (!HostCode) {
@@ -638,7 +639,6 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In
     Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
     Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
     Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit);
-    Common.MonoBackpatcherWrite = reinterpret_cast<uint64_t>(&Context::ContextImpl::MonoBackpatcherWrite);
     Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
 
     {
@@ -667,6 +667,15 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In
 
   CurrentCodeBuffer = CodeBuffers.GetLatest();
   ThreadState->LookupCache->Shared = CurrentCodeBuffer->LookupCache.get();
+
+  // Setup dynamic dispatch.
+  if (ParanoidTSO()) {
+    RT_LoadMemTSO = &Arm64JITCore::Op_ParanoidLoadMemTSO;
+    RT_StoreMemTSO = &Arm64JITCore::Op_ParanoidStoreMemTSO;
+  } else {
+    RT_LoadMemTSO = &Arm64JITCore::Op_LoadMemTSO;
+    RT_StoreMemTSO = &Arm64JITCore::Op_StoreMemTSO;
+  }
 }
 
 void Arm64JITCore::EmitDetectionString() {
@@ -730,48 +739,48 @@ bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode,
   }
 }
 
-void Arm64JITCore::EmitTFCheck() {
-  ARMEmitter::ForwardLabel l_TFUnset;
-  ARMEmitter::ForwardLabel l_TFBlocked;
+void Arm64JITCore::EmitInterruptChecks(bool CheckTF) {
+  if (CheckTF) {
+    ARMEmitter::ForwardLabel l_TFUnset;
+    ARMEmitter::ForwardLabel l_TFBlocked;
 
-  // Note that this needs to be before the below suspend checks, as X86 checks this flag immediately after executing an instruction.
-  ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
+    // Note that this needs to be before the below suspend checks, as X86 checks this flag immediately after executing an instruction.
+    ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
 
-  (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &l_TFUnset);
+    cbz(ARMEmitter::Size::i32Bit, TMP1, &l_TFUnset);
 
-  // X86 semantically checks TF after executing each instruction, so e.g. setting a context with TF set will execute a single instruction
-  // and then raise an exception. However on the FEX side this is simpler to implement by checking at the start of each instruction, handle this by having bit 1 being unset in the flag state indicate that TF is blocked for a single instruction.
-  (void)tbz(TMP1, 1, &l_TFBlocked);
+    // X86 semantically checks TF after executing each instruction, so e.g. setting a context with TF set will execute a single instruction
+    // and then raise an exception. However on the FEX side this is simpler to implement by checking at the start of each instruction, handle this by having bit 1 being unset in the flag state indicate that TF is blocked for a single instruction.
+    tbz(TMP1, 1, &l_TFBlocked);
 
-  // Block TF for a single instruction when the frontend jumps to a new context by unsetting bit 1.
-  ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
-  and_(ARMEmitter::Size::i32Bit, TMP1, TMP1, ~(1 << 1));
-  strb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
+    // Block TF for a single instruction when the frontend jumps to a new context by unsetting bit 1.
+    ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
+    and_(ARMEmitter::Size::i32Bit, TMP1, TMP1, ~(1 << 1));
+    strb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
 
-  Core::CpuStateFrame::SynchronousFaultDataStruct State = {
-    .FaultToTopAndGeneratedException = 1,
-    .Signal = Core::FAULT_SIGTRAP,
-    .TrapNo = X86State::X86_TRAPNO_DB,
-    .si_code = 2,
-    .err_code = 0,
-  };
+    Core::CpuStateFrame::SynchronousFaultDataStruct State = {
+      .FaultToTopAndGeneratedException = 1,
+      .Signal = Core::FAULT_SIGTRAP,
+      .TrapNo = X86State::X86_TRAPNO_DB,
+      .si_code = 2,
+      .err_code = 0,
+    };
 
-  uint64_t Constant {};
-  memcpy(&Constant, &State, sizeof(State));
+    uint64_t Constant {};
+    memcpy(&Constant, &State, sizeof(State));
 
-  LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Constant);
-  str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData));
-  ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
-  br(TMP1);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Constant);
+    str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
+    br(TMP1);
 
-  (void)Bind(&l_TFBlocked);
-  // If TF was blocked for this instruction, unblock it for the next.
-  LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 0b11);
-  strb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
-  (void)Bind(&l_TFUnset);
-}
+    Bind(&l_TFBlocked);
+    // If TF was blocked for this instruction, unblock it for the next.
+    LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 0b11);
+    strb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
+    Bind(&l_TFUnset);
+  }
 
-void Arm64JITCore::EmitSuspendInterruptCheck() {
   if (CTX->Config.NeedsPendingInterruptFaultCheck) {
     // Trigger a fault if there are any pending interrupts
     // Used only for suspend on WIN32 at the moment
@@ -786,19 +795,17 @@ void Arm64JITCore::EmitSuspendInterruptCheck() {
   ARMEmitter::ForwardLabel l_NoSuspend;
   cbz(ARMEmitter::Size::i32Bit, TMP2, &l_NoSuspend);
   brk(SuspendMagic);
-  (void)Bind(&l_NoSuspend);
+  Bind(&l_NoSuspend);
 #endif
 }
 
 void Arm64JITCore::EmitEntryPoint(ARMEmitter::BackwardLabel& HeaderLabel, bool CheckTF) {
   // Get the address of the JITCodeHeader and store in to the core state.
   // Two instruction cost, each 1 cycle.
-  adr_OrRestart(TMP1, &HeaderLabel);
+  adr(TMP1, &HeaderLabel);
   str(TMP1, STATE, offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader));
 
-  if (CheckTF) {
-    EmitTFCheck();
-  }
+  EmitInterruptChecks(CheckTF);
 
   if (SpillSlots) {
     const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize;
@@ -815,25 +822,15 @@ void Arm64JITCore::EmitEntryPoint(ARMEmitter::BackwardLabel& HeaderLabel, bool C
 CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size, bool SingleInst, const FEXCore::IR::IRListView* IR,
                                                    FEXCore::Core::DebugData* DebugData, bool CheckTF) {
   FEXCORE_PROFILE_SCOPED("Arm64::CompileCode");
-  this->Entry = Entry;
-  this->DebugData = DebugData;
-  this->IR = IR;
-  RequiresFarARM64Jumps = false;
 
-  switch (static_cast<RestartOptions::Control>(FEXCore::LongJump::SetJump(RestartControl.RestartJump))) {
-  case RestartOptions::Control::Incoming:
-    // Nothing
-    break;
-  case RestartOptions::Control::EnableFarARM64Jumps: RequiresFarARM64Jumps = true; break;
-  default: ERROR_AND_DIE_FMT("Unhandled Arm64 restart condition!");
-  }
-
-  uint32_t SSACount = IR->GetSSACount();
   JumpTargets.clear();
   CallReturnTargets.clear();
   PendingJumpThunks.clear();
-  JumpTargets.resize(IR->GetHeader()->BlockCount, {});
+  uint32_t SSACount = IR->GetSSACount();
 
+  this->Entry = Entry;
+  this->DebugData = DebugData;
+  this->IR = IR;
   CodeData.EntryPoints.clear();
 
   // Fairly excessive buffer range to make sure we don't overflow
@@ -848,7 +845,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
 
   // Put the code header at the start of the data block.
   ARMEmitter::BackwardLabel JITCodeHeaderLabel {};
-  (void)Bind(&JITCodeHeaderLabel);
+  Bind(&JITCodeHeaderLabel);
   JITCodeHeader* CodeHeader = GetCursorAddress<JITCodeHeader*>();
   CursorIncrement(sizeof(JITCodeHeader));
 
@@ -889,14 +886,11 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
     auto BlockStartHostCode = GetCursorAddress<uint8_t*>();
     {
       const auto Node = IR->GetID(BlockNode);
-      const auto Target = &JumpTargets[BlockIROp->ID];
+      const auto IsTarget = JumpTargets.try_emplace(Node).first;
 
       // if there's a pending branch, and it is not fall-through
-      if (PendingTargetLabel && PendingTargetLabel != Target) {
-        if (PendingTargetLabel->Backward.Location) {
-          EmitSuspendInterruptCheck();
-        }
-        b_OrRestart(PendingTargetLabel);
+      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second) {
+        b(PendingTargetLabel);
         PendingTargetLabel = nullptr;
       }
 
@@ -906,14 +900,14 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
         const auto IsReturnTarget = CallReturnTargets.try_emplace(Node).first;
         if (PendingTargetLabel) {
           // If there is a fallthrough branch to this block, skip over the entrypoint code.
-          b_OrRestart(Target);
+          b(&IsTarget->second);
         } else if (PendingCallReturnTargetLabel && PendingCallReturnTargetLabel != &IsReturnTarget->second) {
           // If we just emitted a call, but the block we're now emitting is not the return block so don't fallthrough.
-          b_OrRestart(PendingCallReturnTargetLabel);
+          b(PendingCallReturnTargetLabel);
         }
         PendingCallReturnTargetLabel = nullptr;
 
-        BindOrRestart(&IsReturnTarget->second);
+        Bind(&IsReturnTarget->second);
         CodeData.EntryPoints.emplace(BlockStartRIP, GetCursorAddress<uint8_t*>());
         DebugData->GuestOpcodes.push_back({BlockIROp->GuestEntryOffset, GetCursorAddress<uint8_t*>() - CodeData.BlockBegin});
 
@@ -922,12 +916,12 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
 
       if (PendingCallReturnTargetLabel) {
         // If there is still a pending call return target, then the block we're emitting is not the return block so don't fallthrough.
-        b_OrRestart(PendingCallReturnTargetLabel);
+        b(PendingCallReturnTargetLabel);
         PendingCallReturnTargetLabel = nullptr;
       }
       PendingTargetLabel = nullptr;
 
-      BindOrRestart(Target);
+      Bind(&IsTarget->second);
     }
 
     for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
@@ -951,10 +945,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
 
   // Make sure last branch is generated. It certainly can't be eliminated here.
   if (PendingTargetLabel) {
-    if (PendingTargetLabel->Backward.Location) {
-      EmitSuspendInterruptCheck();
-    }
-    b_OrRestart(PendingTargetLabel);
+    b(PendingTargetLabel);
   }
   PendingTargetLabel = nullptr;
 
@@ -965,21 +956,21 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
 
     ARMEmitter::ForwardLabel l_DoLink;
     uint64_t ThunkAddress = GetCursorAddress<uint64_t>();
-    BindOrRestart(&PendingJumpThunk.Label);
-    b_OrRestart(&l_DoLink);
+    Bind(&PendingJumpThunk.Label);
+    b(&l_DoLink);
     br(TMP1);
-    BindOrRestart(&l_DoLink);
+    Bind(&l_DoLink);
     ldr(TMP1, &l_ExitLink);
     blr(TMP1);
 
     // This is a ExitFunctionLinkData struct
-    BindOrRestart(&l_ExitLink);
+    Bind(&l_ExitLink);
     dc64(0);                                             // HostCode
     dc64(PendingJumpThunk.GuestRIP);                     // GuestRIP
     dc64(PendingJumpThunk.CallerAddress - ThunkAddress); // CallerOffset
   }
 
-  BindOrRestart(&l_ExitLink);
+  Bind(&l_ExitLink);
   dc64(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
 
   // CodeSize not including the header or tail data.

FEXCore/Source/Interface/Core/JIT/JITClass.h

@@ -19,13 +19,11 @@ $end_info$
 #include <FEXCore/fextl/map.h>
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/vector.h>
-#include <FEXCore/Utils/LongJump.h>
 
 #include <CodeEmitter/Emitter.h>
 
 #include <array>
 #include <cstdint>
-#include <functional>
 #include <utility>
 #include <variant>
 
@@ -55,7 +53,6 @@ public:
 
 private:
   FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
-  FEX_CONFIG_OPT(HalfBarrierTSOEnabled, HALFBARRIERTSOENABLED);
 
   const bool HostSupportsSVE128 {};
   const bool HostSupportsSVE256 {};
@@ -63,19 +60,6 @@ private:
   const bool HostSupportsRPRES {};
   const bool HostSupportsAFP {};
 
-  struct RestartOptions {
-    FEXCore::LongJump::JumpBuf RestartJump;
-    enum class Control : uint64_t {
-      Incoming = 0,
-      EnableFarARM64Jumps = 1,
-    };
-  };
-
-  // FEXCore makes assumptions in the JIT about certain conditions being true.
-  // In the rare case when those assumptions are broken, FEX needs to safely restart the JIT.
-  RestartOptions RestartControl {};
-  bool RequiresFarARM64Jumps {};
-
   ARMEmitter::BiDirectionalLabel* PendingTargetLabel {};
   ARMEmitter::BiDirectionalLabel* PendingCallReturnTargetLabel {};
   FEXCore::Context::ContextImpl* CTX {};
@@ -83,13 +67,7 @@ private:
   uint64_t Entry {};
   CPUBackend::CompiledCode CodeData {};
 
-  fextl::vector<ARMEmitter::BiDirectionalLabel> JumpTargets;
-
-  ARMEmitter::BiDirectionalLabel* JumpTarget(IR::OrderedNodeWrapper Node) {
-    auto Block = IR->GetOp<IR::IROp_CodeBlock>(Node);
-    return &JumpTargets[Block->ID];
-  }
-
+  fextl::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> JumpTargets;
   fextl::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> CallReturnTargets;
 
   struct PendingJumpThunk {
@@ -260,10 +238,10 @@ private:
     case FEXCore::IR::COND_FGE: return ARMEmitter::Condition::CC_GE;
     case FEXCore::IR::COND_FLEU: return ARMEmitter::Condition::CC_LE;
     case FEXCore::IR::COND_FGT: return ARMEmitter::Condition::CC_GT;
-    case FEXCore::IR::COND_FU:
-    case FEXCore::IR::COND_VS: return ARMEmitter::Condition::CC_VS;
-    case FEXCore::IR::COND_FNU:
-    case FEXCore::IR::COND_VC: return ARMEmitter::Condition::CC_VC;
+    case FEXCore::IR::COND_FU: return ARMEmitter::Condition::CC_VS;
+    case FEXCore::IR::COND_FNU: return ARMEmitter::Condition::CC_VC;
+    case FEXCore::IR::COND_VS:
+    case FEXCore::IR::COND_VC:
     case FEXCore::IR::COND_MI: return ARMEmitter::Condition::CC_MI;
     case FEXCore::IR::COND_PL: return ARMEmitter::Condition::CC_PL;
     default: LOGMAN_MSG_A_FMT("Unsupported compare type"); return ARMEmitter::Condition::CC_NV;
@@ -330,199 +308,14 @@ private:
   void EmitLinkedBranch(uint64_t GuestRIP, bool Call) {
     PendingJumpThunks.push_back({GetCursorAddress<uint64_t>(), GuestRIP, {}});
     auto& Thunk = PendingJumpThunks.back();
-    BindOrRestart(&Thunk.Label);
+    Bind(&Thunk.Label);
     if (Call) {
-      bl_OrRestart(&Thunk.Label);
+      bl(&Thunk.Label);
     } else {
-      b_OrRestart(&Thunk.Label);
+      b(&Thunk.Label);
     }
   }
 
-  // Restart helpers
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void bl_OrRestart(T* Label) {
-    if (bl(Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    // We can support this but currently unnecessary.
-    ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void b_OrRestart(T* Label) {
-    if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    // We can support this but currently unnecessary.
-    ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void b_OrRestart(ARMEmitter::Condition Cond, T* Label) {
-    if (RequiresFarARM64Jumps) {
-      ARMEmitter::ForwardLabel Skip {};
-      // Wrap a manual Cond check around an unconditional branch; this can encode larger offsets
-      (void)b(InvertCondition(Cond), &Skip);
-      if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Failure) {
-        ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-      }
-
-      (void)Bind(&Skip);
-      return;
-    }
-
-    if (b(Cond, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void cbz_OrRestart(ARMEmitter::Size s, ARMEmitter::Register rt, T* Label) {
-    if (RequiresFarARM64Jumps) {
-      ARMEmitter::ForwardLabel Skip {};
-      // Wrap a manual Cond check around an unconditional branch; this can encode larger offsets
-      (void)cbnz(s, rt, &Skip);
-      if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Failure) {
-        ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-      }
-
-      (void)Bind(&Skip);
-      return;
-    }
-
-    if (cbz(s, rt, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void cbnz_OrRestart(ARMEmitter::Size s, ARMEmitter::Register rt, T* Label) {
-    if (RequiresFarARM64Jumps) {
-      ARMEmitter::ForwardLabel Skip {};
-      // Wrap a manual Cond check around an unconditional branch; this can encode larger offsets
-      (void)cbz(s, rt, &Skip);
-      if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Failure) {
-        ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-      }
-
-      (void)Bind(&Skip);
-      return;
-    }
-
-    if (cbnz(s, rt, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void tbz_OrRestart(ARMEmitter::Register rt, uint32_t Bit, T* Label) {
-    if (RequiresFarARM64Jumps) {
-      ARMEmitter::ForwardLabel Skip {};
-      // Wrap a manual Cond check around an unconditional branch; this can encode larger offsets
-      (void)tbnz(rt, Bit, &Skip);
-      if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Failure) {
-        ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-      }
-
-      (void)Bind(&Skip);
-      return;
-    }
-
-    if (tbz(rt, Bit, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void tbnz_OrRestart(ARMEmitter::Register rt, uint32_t Bit, T* Label) {
-    if (RequiresFarARM64Jumps) {
-      ARMEmitter::ForwardLabel Skip {};
-      // Wrap a manual Cond check around an unconditional branch; this can encode larger offsets
-      (void)tbz(rt, Bit, &Skip);
-      if (b(Label) == ARMEmitter::BranchEncodeSucceeded::Failure) {
-        ERROR_AND_DIE_FMT("Tried to branch larger than 128MB away!");
-      }
-
-      (void)Bind(&Skip);
-      return;
-    }
-
-    if (tbnz(rt, Bit, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void adr_OrRestart(ARMEmitter::Register rd, T* Label) {
-    if (adr(rd, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    // We can support this but currently unnecessary.
-    ERROR_AND_DIE_FMT("Long ADR currently unsupported!");
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void adrp_OrRestart(ARMEmitter::Register rd, T* Label) {
-    if (adrp(rd, Label) == ARMEmitter::BranchEncodeSucceeded::Success) {
-      return;
-    }
-
-    // We can support this but currently unnecessary.
-    ERROR_AND_DIE_FMT("Long ADRP currently unsupported!");
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
-  template<typename T>
-  requires (std::is_same_v<T, ARMEmitter::ForwardLabel> || std::is_same_v<T, ARMEmitter::BackwardLabel> ||
-            std::is_same_v<T, ARMEmitter::BiDirectionalLabel> || std::is_same_v<T, ARMEmitter::ForwardLabel::Reference>)
-  void BindOrRestart(T* Label) {
-    if (Bind(Label)) {
-      return;
-    }
-
-    if (RequiresFarARM64Jumps) {
-      // This should have been caught before this point.
-      ERROR_AND_DIE_FMT("Oops. Unhandled long bind.");
-      return;
-    }
-
-    FEXCore::LongJump::LongJump(RestartControl.RestartJump, FEXCore::ToUnderlying(RestartOptions::Control::EnableFarARM64Jumps));
-  }
-
   // This is purely a debugging aid for developers to see if they are in JIT code space when inspecting raw memory
   void EmitDetectionString();
   IR::RegisterAllocationPass* RAPass {};
@@ -581,9 +374,7 @@ private:
   fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
   ///< Relocation code loading
-  bool ApplyRelocations(uint64_t GuestEntry, std::span<std::byte> Code, std::span<const FEXCore::CPU::Relocation>);
-
-  fextl::vector<FEXCore::CPU::Relocation> TakeRelocations() override;
+  bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
 
   /**  @} */
 
@@ -608,14 +399,21 @@ private:
                            std::optional<ARMEmitter::VRegister> VectorIndexHigh, ARMEmitter::VRegister MaskReg, IR::OpSize VectorIndexSize,
                            size_t DataElementOffsetStart, size_t IndexElementOffsetStart, uint8_t OffsetScale);
 
-  void EmitTFCheck();
-
-  void EmitSuspendInterruptCheck();
+  void EmitInterruptChecks(bool CheckTF);
 
   void EmitEntryPoint(ARMEmitter::BackwardLabel& HeaderLabel, bool CheckTF);
 
+  // Runtime selection;
+  // Load and store TSO memory style
+  OpType RT_LoadMemTSO;
+  OpType RT_StoreMemTSO;
+
 #define DEF_OP(x) void Op_##x(IR::IROp_Header const* IROp, IR::Ref Node)
 
+  // Dynamic Dispatcher supporting operations
+  DEF_OP(ParanoidLoadMemTSO);
+  DEF_OP(ParanoidStoreMemTSO);
+
   ///< Unhandled handler
   DEF_OP(Unhandled);
 

FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp

@@ -140,7 +140,7 @@ DEF_OP(LoadRegister) {
 
     mov(GetReg(Node).X(), StaticRegisters[Op->Reg].X());
   } else if (Op->Class == IR::FPRClass) {
-    const auto regSize = HostSupportsAVX256 ? IR::OpSize::i256Bit : IR::OpSize::i128Bit;
+    [[maybe_unused]] const auto regSize = HostSupportsAVX256 ? IR::OpSize::i256Bit : IR::OpSize::i128Bit;
     LOGMAN_THROW_A_FMT(Op->Reg < StaticFPRegisters.size(), "out of range reg");
     LOGMAN_THROW_A_FMT(IROp->Size == regSize, "expected sized");
 
@@ -181,7 +181,7 @@ DEF_OP(StoreRegister) {
     // Always use 64-bit, it's faster. Upper bits ignored for 32-bit mode.
     mov(ARMEmitter::Size::i64Bit, GetReg(Reg), GetReg(Op->Value));
   } else if (Reg.Class == IR::FPRFixedClass) {
-    const auto regSize = HostSupportsAVX256 ? IR::OpSize::i256Bit : IR::OpSize::i128Bit;
+    [[maybe_unused]] const auto regSize = HostSupportsAVX256 ? IR::OpSize::i256Bit : IR::OpSize::i128Bit;
     LOGMAN_THROW_A_FMT(IROp->Size == regSize, "expected sized");
 
     const auto guest = GetVReg(Reg);
@@ -348,25 +348,6 @@ DEF_OP(StoreContextIndexed) {
   }
 }
 
-DEF_OP(FormContextAddress) {
-  const auto Op = IROp->C<IR::IROp_FormContextAddress>();
-  const auto Index = GetReg(Op->Index);
-  const auto Dst = GetReg(Node);
-
-  switch (Op->Stride) {
-  case 1:
-  case 2:
-  case 4:
-  case 8:
-  case 16:
-  case 32: {
-    add(ARMEmitter::Size::i64Bit, Dst, STATE, Index, ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride));
-    break;
-  }
-  default: LOGMAN_MSG_A_FMT("Unhandled FormContextAddress stride: {}", Op->Stride); break;
-  }
-}
-
 DEF_OP(SpillRegister) {
   const auto Op = IROp->C<IR::IROp_SpillRegister>();
   const auto OpSize = IROp->Size;
@@ -761,7 +742,7 @@ DEF_OP(LoadMemTSO) {
     const auto Dst = GetReg(Node);
     uint64_t Offset = 0;
     if (!Op->Offset.IsInvalid()) {
-      bool IsInline = IsInlineConstant(Op->Offset, &Offset);
+      [[maybe_unused]] bool IsInline = IsInlineConstant(Op->Offset, &Offset);
       LOGMAN_THROW_A_FMT(IsInline, "expected immediate");
     }
 
@@ -776,10 +757,8 @@ DEF_OP(LoadMemTSO) {
       case IR::OpSize::i64Bit: ldapur(Dst.X(), MemReg, Offset); break;
       default: LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize); break;
       }
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        // Half-barrier once back-patched.
-        nop();
-      }
+      // Half-barrier once back-patched.
+      nop();
     }
   } else if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
     const auto Dst = GetReg(Node);
@@ -793,10 +772,8 @@ DEF_OP(LoadMemTSO) {
       case IR::OpSize::i64Bit: ldapr(Dst.X(), MemReg); break;
       default: LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize); break;
       }
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        // Half-barrier once back-patched.
-        nop();
-      }
+      // Half-barrier once back-patched.
+      nop();
     }
   } else if (Op->Class == FEXCore::IR::GPRClass) {
     const auto Dst = GetReg(Node);
@@ -810,10 +787,8 @@ DEF_OP(LoadMemTSO) {
       case IR::OpSize::i64Bit: ldar(Dst.X(), MemReg); break;
       default: LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize); break;
       }
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        // Half-barrier once back-patched.
-        nop();
-      }
+      // Half-barrier once back-patched.
+      nop();
     }
   } else {
     const auto Dst = GetVReg(Node);
@@ -917,7 +892,7 @@ DEF_OP(VLoadVectorMasked) {
 
       // If the sign bit is zero then skip the load
       ARMEmitter::ForwardLabel Skip {};
-      (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
+      tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
       // Do the gather load for this element into the destination
       switch (IROp->ElementSize) {
       case IR::OpSize::i8Bit: ld1<ARMEmitter::SubRegSize::i8Bit>(TempDst.Q(), i, TempMemReg); break;
@@ -928,7 +903,7 @@ DEF_OP(VLoadVectorMasked) {
       default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, IROp->ElementSize); return;
       }
 
-      (void)Bind(&Skip);
+      Bind(&Skip);
 
       if ((i + 1) != NumElements) {
         // Handle register rename to save a move.
@@ -1018,7 +993,7 @@ DEF_OP(VStoreVectorMasked) {
 
       // If the sign bit is zero then skip the load
       ARMEmitter::ForwardLabel Skip {};
-      (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
+      tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
       // Do the gather load for this element into the destination
       switch (IROp->ElementSize) {
       case IR::OpSize::i8Bit: st1<ARMEmitter::SubRegSize::i8Bit>(RegData.Q(), i, TempMemReg); break;
@@ -1029,7 +1004,7 @@ DEF_OP(VStoreVectorMasked) {
       default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, IROp->ElementSize); return;
       }
 
-      (void)Bind(&Skip);
+      Bind(&Skip);
 
       if ((i + 1) != NumElements) {
         // Handle register rename to save a move.
@@ -1107,7 +1082,7 @@ void Arm64JITCore::Emulate128BitGather(IR::OpSize Size, IR::OpSize ElementSize,
     PerformMove(ElementSize, WorkingReg, MaskReg, i);
 
     // Skip if the mask's sign bit isn't set
-    (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
+    tbz(WorkingReg, ElementSizeInBits - 1, &Skip);
 
     // Extract Index Element
     if ((IndexElement * IR::OpSizeToSize(VectorIndexSize)) >= 16) {
@@ -1145,7 +1120,7 @@ void Arm64JITCore::Emulate128BitGather(IR::OpSize Size, IR::OpSize ElementSize,
     default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, ElementSize); FEX_UNREACHABLE;
     }
 
-    (void)Bind(&Skip);
+    Bind(&Skip);
   }
 
   if (NeedsDestTmp) {
@@ -1775,7 +1750,7 @@ DEF_OP(StoreMemTSO) {
     const auto Src = GetZeroableReg(Op->Value);
     uint64_t Offset = 0;
     if (!Op->Offset.IsInvalid()) {
-      bool IsInline = IsInlineConstant(Op->Offset, &Offset);
+      [[maybe_unused]] bool IsInline = IsInlineConstant(Op->Offset, &Offset);
       LOGMAN_THROW_A_FMT(IsInline, "expected immediate");
     }
 
@@ -1783,10 +1758,8 @@ DEF_OP(StoreMemTSO) {
       // 8bit load is always aligned to natural alignment
       stlurb(Src, MemReg, Offset);
     } else {
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        // Half-barrier once back-patched.
-        nop();
-      }
+      // Half-barrier once back-patched.
+      nop();
       switch (OpSize) {
       case IR::OpSize::i16Bit: stlurh(Src, MemReg, Offset); break;
       case IR::OpSize::i32Bit: stlur(Src.W(), MemReg, Offset); break;
@@ -1801,10 +1774,8 @@ DEF_OP(StoreMemTSO) {
       // 8bit load is always aligned to natural alignment
       stlrb(Src, MemReg);
     } else {
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        // Half-barrier once back-patched.
-        nop();
-      }
+      // Half-barrier once back-patched.
+      nop();
       switch (OpSize) {
       case IR::OpSize::i16Bit: stlrh(Src, MemReg); break;
       case IR::OpSize::i32Bit: stlr(Src.W(), MemReg); break;
@@ -1880,7 +1851,7 @@ DEF_OP(MemSet) {
 
   if (!DirectionIsInline) {
     // Backward or forwards implementation depends on flag
-    (void)tbnz(DirectionReg, 1, &BackwardImpl);
+    tbnz(DirectionReg, 1, &BackwardImpl);
   }
 
   auto MemStore = [this](auto Value, uint32_t OpSize, int32_t Size) {
@@ -1898,9 +1869,7 @@ DEF_OP(MemSet) {
       // 8bit load is always aligned to natural alignment
       stlrb(Value.W(), TMP2);
     } else {
-      if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-        nop();
-      }
+      nop();
       switch (OpSize) {
       case 2: stlrh(Value.W(), TMP2); break;
       case 4: stlr(Value.W(), TMP2); break;
@@ -1930,7 +1899,7 @@ DEF_OP(MemSet) {
     ARMEmitter::ForwardLabel DoneInternal {};
 
     // Early exit if zero count.
-    (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
     if (!IsAtomic) {
       ARMEmitter::ForwardLabel AgainInternal256Exit {};
@@ -1947,50 +1916,50 @@ DEF_OP(MemSet) {
       // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the
       // single copy loop if size < 64.
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal128Exit);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
 
       // Fill VTMP2 with the set pattern
       dup(SubRegSize, VTMP2.Q(), Value);
 
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal256Exit);
+      tbnz(TMP1, 63, &AgainInternal256Exit);
 
-      (void)Bind(&AgainInternal256);
+      Bind(&AgainInternal256);
       stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
       stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
-      (void)tbz(TMP1, 63, &AgainInternal256);
+      tbz(TMP1, 63, &AgainInternal256);
 
-      (void)Bind(&AgainInternal256Exit);
+      Bind(&AgainInternal256Exit);
       add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
-      (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal128Exit);
-      (void)Bind(&AgainInternal128);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+      Bind(&AgainInternal128);
       stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbz(TMP1, 63, &AgainInternal128);
+      tbz(TMP1, 63, &AgainInternal128);
 
-      (void)Bind(&AgainInternal128Exit);
+      Bind(&AgainInternal128Exit);
       add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
       if (Direction == -1) {
         add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
       }
     }
 
-    (void)Bind(&AgainInternal);
+    Bind(&AgainInternal);
     if (IsAtomic) {
       MemStoreTSO(Value, OpSize, SizeDirection);
     } else {
       MemStore(Value, OpSize, SizeDirection);
     }
     sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
-    (void)cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal);
+    cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal);
 
-    (void)Bind(&DoneInternal);
+    Bind(&DoneInternal);
 
     if (SizeDirection >= 0) {
       switch (OpSize) {
@@ -2020,12 +1989,12 @@ DEF_OP(MemSet) {
       EmitMemset(Direction);
 
       if (Direction == 1) {
-        (void)b(&Done);
-        (void)Bind(&BackwardImpl);
+        b(&Done);
+        Bind(&BackwardImpl);
       }
     }
 
-    (void)Bind(&Done);
+    Bind(&Done);
     // Destination already set to the final pointer.
   }
 }
@@ -2075,7 +2044,7 @@ DEF_OP(MemCpy) {
 
   if (!DirectionIsInline) {
     // Backward or forwards implementation depends on flag
-    (void)tbnz(DirectionReg, 1, &BackwardImpl);
+    tbnz(DirectionReg, 1, &BackwardImpl);
   }
 
   auto MemCpy = [this](uint32_t OpSize, int32_t Size) {
@@ -2118,11 +2087,9 @@ DEF_OP(MemCpy) {
         default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size); break;
         }
 
-        if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-          // Placeholders for backpatching barriers (one per load/store)
-          nop();
-          nop();
-        }
+        // Placeholders for backpatching barriers (one per load/store)
+        nop();
+        nop();
 
         switch (OpSize) {
         case 2: stlrh(TMP4.W(), TMP2); break;
@@ -2144,11 +2111,9 @@ DEF_OP(MemCpy) {
         default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size); break;
         }
 
-        if (HalfBarrierTSOEnabled() && !ParanoidTSO()) {
-          // Placeholders for backpatching barriers (one per load/store)
-          nop();
-          nop();
-        }
+        // Placeholders for backpatching barriers (one per load/store)
+        nop();
+        nop();
 
         switch (OpSize) {
         case 2: stlrh(TMP4.W(), TMP2); break;
@@ -2176,7 +2141,7 @@ DEF_OP(MemCpy) {
     ARMEmitter::ForwardLabel DoneInternal {};
 
     // Early exit if zero count.
-    (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
     if (!IsAtomic) {
       ARMEmitter::ForwardLabel AbsPos {};
@@ -2186,11 +2151,11 @@ DEF_OP(MemCpy) {
       ARMEmitter::BackwardLabel AgainInternal256 {};
 
       sub(ARMEmitter::Size::i64Bit, TMP4, TMP2, TMP3);
-      (void)tbz(TMP4, 63, &AbsPos);
+      tbz(TMP4, 63, &AbsPos);
       neg(ARMEmitter::Size::i64Bit, TMP4, TMP4);
-      (void)Bind(&AbsPos);
+      Bind(&AbsPos);
       sub(ARMEmitter::Size::i64Bit, TMP4, TMP4, 32);
-      (void)tbnz(TMP4, 63, &AgainInternal);
+      tbnz(TMP4, 63, &AgainInternal);
 
       if (Direction == -1) {
         sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
@@ -2202,30 +2167,30 @@ DEF_OP(MemCpy) {
       // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the
       // single copy loop if size < 64.
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal128Exit);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal256Exit);
+      tbnz(TMP1, 63, &AgainInternal256Exit);
 
-      (void)Bind(&AgainInternal256);
+      Bind(&AgainInternal256);
       MemCpy(32, 32 * Direction);
       MemCpy(32, 32 * Direction);
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
-      (void)tbz(TMP1, 63, &AgainInternal256);
+      tbz(TMP1, 63, &AgainInternal256);
 
-      (void)Bind(&AgainInternal256Exit);
+      Bind(&AgainInternal256Exit);
       add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
-      (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbnz(TMP1, 63, &AgainInternal128Exit);
-      (void)Bind(&AgainInternal128);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+      Bind(&AgainInternal128);
       MemCpy(32, 32 * Direction);
       sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)tbz(TMP1, 63, &AgainInternal128);
+      tbz(TMP1, 63, &AgainInternal128);
 
-      (void)Bind(&AgainInternal128Exit);
+      Bind(&AgainInternal128Exit);
       add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
-      (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
 
       if (Direction == -1) {
         add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
@@ -2233,16 +2198,16 @@ DEF_OP(MemCpy) {
       }
     }
 
-    (void)Bind(&AgainInternal);
+    Bind(&AgainInternal);
     if (IsAtomic) {
       MemCpyTSO(OpSize, SizeDirection);
     } else {
       MemCpy(OpSize, SizeDirection);
     }
     sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
-    (void)cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal);
+    cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal);
 
-    (void)Bind(&DoneInternal);
+    Bind(&DoneInternal);
 
     // Needs to use temporaries just in case of overwrite
     mov(TMP1, MemRegDest.X());
@@ -2300,15 +2265,186 @@ DEF_OP(MemCpy) {
     for (int32_t Direction : {1, -1}) {
       EmitMemcpy(Direction);
       if (Direction == 1) {
-        (void)b(&Done);
-        (void)Bind(&BackwardImpl);
+        b(&Done);
+        Bind(&BackwardImpl);
       }
     }
-    (void)Bind(&Done);
+    Bind(&Done);
     // Destination already set to the final pointer.
   }
 }
 
+DEF_OP(ParanoidLoadMemTSO) {
+  const auto Op = IROp->C<IR::IROp_LoadMemTSO>();
+  const auto OpSize = IROp->Size;
+
+  auto MemReg = GetReg(Op->Addr);
+
+  if (CTX->HostFeatures.SupportsTSOImm9 && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Dst = GetReg(Node);
+    uint64_t Offset = 0;
+    if (!Op->Offset.IsInvalid()) {
+      if (!IsInlineConstant(Op->Offset, &Offset)) {
+        MemReg = ApplyMemOperand(OpSize, MemReg, TMP4, Op->Offset, Op->OffsetType, Op->OffsetScale);
+      }
+    }
+
+    if (OpSize == IR::OpSize::i8Bit) {
+      // 8bit load is always aligned to natural alignment
+      const auto Dst = GetReg(Node);
+      ldapurb(Dst, MemReg, Offset);
+    } else {
+      switch (OpSize) {
+      case IR::OpSize::i16Bit: ldapurh(Dst, MemReg, Offset); break;
+      case IR::OpSize::i32Bit: ldapur(Dst.W(), MemReg, Offset); break;
+      case IR::OpSize::i64Bit: ldapur(Dst.X(), MemReg, Offset); break;
+      default: LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize); break;
+      }
+    }
+  } else if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Dst = GetReg(Node);
+    MemReg = ApplyMemOperand(OpSize, MemReg, TMP4, Op->Offset, Op->OffsetType, Op->OffsetScale);
+    if (OpSize == IR::OpSize::i8Bit) {
+      // 8bit load is always aligned to natural alignment
+      ldaprb(Dst.W(), MemReg);
+    } else {
+      switch (OpSize) {
+      case IR::OpSize::i16Bit: ldaprh(Dst.W(), MemReg); break;
+      case IR::OpSize::i32Bit: ldapr(Dst.W(), MemReg); break;
+      case IR::OpSize::i64Bit: ldapr(Dst.X(), MemReg); break;
+      default: LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize); break;
+      }
+    }
+  } else if (Op->Class == FEXCore::IR::GPRClass) {
+    const auto Dst = GetReg(Node);
+    MemReg = ApplyMemOperand(OpSize, MemReg, TMP4, Op->Offset, Op->OffsetType, Op->OffsetScale);
+    switch (OpSize) {
+    case IR::OpSize::i8Bit: ldarb(Dst, MemReg); break;
+    case IR::OpSize::i16Bit: ldarh(Dst, MemReg); break;
+    case IR::OpSize::i32Bit: ldar(Dst.W(), MemReg); break;
+    case IR::OpSize::i64Bit: ldar(Dst.X(), MemReg); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize); break;
+    }
+  } else {
+    const auto Dst = GetVReg(Node);
+    MemReg = ApplyMemOperand(OpSize, MemReg, TMP4, Op->Offset, Op->OffsetType, Op->OffsetScale);
+    switch (OpSize) {
+    case IR::OpSize::i8Bit:
+      ldarb(TMP1, MemReg);
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
+      break;
+    case IR::OpSize::i16Bit:
+      ldarh(TMP1, MemReg);
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
+      break;
+    case IR::OpSize::i32Bit:
+      ldar(TMP1.W(), MemReg);
+      fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
+      break;
+    case IR::OpSize::i64Bit:
+      ldar(TMP1, MemReg);
+      fmov(ARMEmitter::Size::i64Bit, Dst.D(), TMP1);
+      break;
+    case IR::OpSize::i128Bit:
+      ldaxp(ARMEmitter::Size::i64Bit, TMP1, TMP2, MemReg);
+      clrex();
+      ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, TMP1);
+      ins(ARMEmitter::SubRegSize::i64Bit, Dst, 1, TMP2);
+      break;
+    case IR::OpSize::i256Bit:
+      LOGMAN_THROW_A_FMT(HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
+      dmb(ARMEmitter::BarrierScope::ISH);
+      ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), PRED_TMP_32B.Zeroing(), MemReg);
+      dmb(ARMEmitter::BarrierScope::ISH);
+      break;
+    default: LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize); break;
+    }
+  }
+}
+
+DEF_OP(ParanoidStoreMemTSO) {
+  const auto Op = IROp->C<IR::IROp_StoreMemTSO>();
+  const auto OpSize = IROp->Size;
+
+  auto MemReg = GetReg(Op->Addr);
+
+  if (CTX->HostFeatures.SupportsTSOImm9 && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Src = GetZeroableReg(Op->Value);
+    uint64_t Offset = 0;
+    if (!Op->Offset.IsInvalid()) {
+      if (!IsInlineConstant(Op->Offset, &Offset)) {
+        MemReg = ApplyMemOperand(OpSize, MemReg, TMP1, Op->Offset, Op->OffsetType, Op->OffsetScale);
+      }
+    }
+
+    if (OpSize == IR::OpSize::i8Bit) {
+      // 8bit load is always aligned to natural alignment
+      stlurb(Src, MemReg, Offset);
+    } else {
+      switch (OpSize) {
+      case IR::OpSize::i16Bit: stlurh(Src, MemReg, Offset); break;
+      case IR::OpSize::i32Bit: stlur(Src.W(), MemReg, Offset); break;
+      case IR::OpSize::i64Bit: stlur(Src.X(), MemReg, Offset); break;
+      default: LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize); break;
+      }
+    }
+  } else if (Op->Class == FEXCore::IR::GPRClass) {
+    const auto Src = GetZeroableReg(Op->Value);
+    MemReg = ApplyMemOperand(OpSize, MemReg, TMP1, Op->Offset, Op->OffsetType, Op->OffsetScale);
+    switch (OpSize) {
+    case IR::OpSize::i8Bit: stlrb(Src, MemReg); break;
+    case IR::OpSize::i16Bit: stlrh(Src, MemReg); break;
+    case IR::OpSize::i32Bit: stlr(Src.W(), MemReg); break;
+    case IR::OpSize::i64Bit: stlr(Src.X(), MemReg); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize); break;
+    }
+  } else {
+    const auto Src = GetVReg(Op->Value);
+
+    MemReg = ApplyMemOperand(OpSize, MemReg, TMP4, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+    switch (OpSize) {
+    case IR::OpSize::i8Bit:
+      umov<ARMEmitter::SubRegSize::i8Bit>(TMP1, Src, 0);
+      stlrb(TMP1, MemReg);
+      break;
+    case IR::OpSize::i16Bit:
+      umov<ARMEmitter::SubRegSize::i16Bit>(TMP1, Src, 0);
+      stlrh(TMP1, MemReg);
+      break;
+    case IR::OpSize::i32Bit:
+      umov<ARMEmitter::SubRegSize::i32Bit>(TMP1, Src, 0);
+      stlr(TMP1.W(), MemReg);
+      break;
+    case IR::OpSize::i64Bit:
+      umov<ARMEmitter::SubRegSize::i64Bit>(TMP1, Src, 0);
+      stlr(TMP1, MemReg);
+      break;
+    case IR::OpSize::i128Bit: {
+      // Move vector to GPRs
+      umov<ARMEmitter::SubRegSize::i64Bit>(TMP1, Src, 0);
+      umov<ARMEmitter::SubRegSize::i64Bit>(TMP2, Src, 1);
+      ARMEmitter::BackwardLabel B;
+      Bind(&B);
+
+      // ldaxp must not have both the destination registers be the same
+      ldaxp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::zr, TMP3, MemReg); // <- Can hit SIGBUS. Overwritten with DMB
+      stlxp(ARMEmitter::Size::i64Bit, TMP3, TMP1, TMP2, MemReg);          // <- Can also hit SIGBUS
+      cbnz(ARMEmitter::Size::i64Bit, TMP3, &B);                           // < Overwritten with DMB
+      break;
+    }
+    case IR::OpSize::i256Bit: {
+      LOGMAN_THROW_A_FMT(HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
+      dmb(ARMEmitter::BarrierScope::ISH);
+      st1b<ARMEmitter::SubRegSize::i8Bit>(Src.Z(), PRED_TMP_32B, MemReg, 0);
+      dmb(ARMEmitter::BarrierScope::ISH);
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize); break;
+    }
+  }
+}
+
 DEF_OP(CacheLineClear) {
   if (!CTX->HostFeatures.SupportsCacheMaintenanceOps) {
     dmb(ARMEmitter::BarrierScope::SY);
@@ -2450,7 +2586,7 @@ DEF_OP(VStoreNonTemporalPair) {
   const auto Op = IROp->C<IR::IROp_VStoreNonTemporalPair>();
   const auto OpSize = IROp->Size;
 
-  const auto Is128Bit = OpSize == IR::OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = OpSize == IR::OpSize::i128Bit;
   LOGMAN_THROW_A_FMT(Is128Bit, "This IR operation only operates at 128-bit wide");
 
   const auto ValueLow = GetVReg(Op->ValueLow);

FEXCore/Source/Interface/Core/JIT/MiscOps.cpp

@@ -10,11 +10,10 @@ $end_info$
 #endif
 
 #include "Interface/Context/Context.h"
-#include "Interface/Core/JIT/DebugData.h"
 #include "Interface/Core/JIT/JITClass.h"
+#include "FEXCore/Debug/InternalThreadState.h"
 
 #include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Debug/InternalThreadState.h>
 
 namespace FEXCore::CPU {
 
@@ -287,43 +286,4 @@ DEF_OP(Yield) {
   yield();
 }
 
-DEF_OP(MonoBackpatcherWrite) {
-  auto Op = IROp->C<IR::IROp_MonoBackpatcherWrite>();
-
-  mov(ARMEmitter::Size::i64Bit, TMP3, GetReg(Op->Addr));
-  mov(ARMEmitter::Size::i64Bit, TMP4, GetReg(Op->Value));
-
-  PushDynamicRegs(TMP1);
-  SpillStaticRegs(TMP1);
-
-  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, STATE.R());
-  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, IR::OpSizeToSize(Op->Size));
-
-  if (!TMP_ABIARGS) {
-    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, TMP3);
-    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, TMP4);
-  }
-
-#ifdef _M_ARM_64EC
-  ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
-  LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 1);
-  strb(TMP1.W(), TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
-#endif
-
-  ldr(ARMEmitter::XReg::x4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.MonoBackpatcherWrite));
-  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-    GenerateIndirectRuntimeCall<void, void*, uint8_t, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
-  } else {
-    blr(ARMEmitter::Reg::r4);
-  }
-
-#ifdef _M_ARM_64EC
-  ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
-  strb(ARMEmitter::WReg::zr, TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
-#endif
-
-  FillStaticRegs();
-  PopDynamicRegs();
-}
-
 } // namespace FEXCore::CPU

FEXCore/Source/Interface/Core/JIT/VectorOps.cpp

@@ -1352,7 +1352,7 @@ DEF_OP(VFMin) {
 
   const auto ElementSize = Op->Header.ElementSize;
   const auto SubRegSize = ConvertSubRegSize248(IROp);
-  const auto IsScalar = ElementSize == OpSize;
+  [[maybe_unused]] const auto IsScalar = ElementSize == OpSize;
   const auto Is256Bit = OpSize == IR::OpSize::i256Bit;
   LOGMAN_THROW_A_FMT(!Is256Bit || HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
 
@@ -1425,7 +1425,7 @@ DEF_OP(VFMax) {
 
   const auto ElementSize = Op->Header.ElementSize;
   const auto SubRegSize = ConvertSubRegSize248(IROp);
-  const auto IsScalar = ElementSize == OpSize;
+  [[maybe_unused]] const auto IsScalar = ElementSize == OpSize;
   const auto Is256Bit = OpSize == IR::OpSize::i256Bit;
   LOGMAN_THROW_A_FMT(!Is256Bit || HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
 

FEXCore/Source/Interface/Core/ObjectCache/CodeObjectSerializationConfig.h

@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+
+#include <FEXCore/Utils/CompilerDefs.h>
+
+#include <cstdint>
+
+namespace FEXCore::CodeSerialize {
+// If any of the config options mismatch on load then the cache won't be used
+// Any of these will result in codegen changes
+struct FEX_PACKED CodeObjectSerializationConfig {
+  // Cookie in the header of the file, isn't part of the config hash
+  uint64_t Cookie {};
+
+  // Instructions per block configuration
+  int32_t MaxInstPerBlock {};
+
+  // Follows CPUID 4000_0001_EAX[3:0]
+  unsigned Arch : 4;
+
+  // Multiblock enabled
+  unsigned MultiBlock : 1;
+
+  // Hardware TSO enabled
+  unsigned HardwareTSOEnabled : 1;
+
+  // TSO enabled
+  unsigned TSOEnabled : 1;
+
+  // ABI local flag unsafe optimization
+  unsigned ABILocalFlags : 1;
+
+  // Paranoid TSO mode enabled
+  unsigned ParanoidTSO : 1;
+
+  // Guest code execution mode (We don't support live mode switch)
+  unsigned Is64BitMode : 1;
+
+  // SMC checks style
+  unsigned SMCChecks : 2;
+
+  // x87 reduced precision
+  unsigned x87ReducedPrecision : 1;
+
+  // Padding to remove uninitialized data warning from asan
+  // Shows remaining amount of bits available for config
+  unsigned _Pad : 19;
+
+  bool operator==(const CodeObjectSerializationConfig& other) const {
+    return Cookie == other.Cookie && MaxInstPerBlock == other.MaxInstPerBlock && Arch == other.Arch && MultiBlock == other.MultiBlock &&
+           HardwareTSOEnabled == other.HardwareTSOEnabled && TSOEnabled == other.TSOEnabled && ABILocalFlags == other.ABILocalFlags &&
+           ParanoidTSO == other.ParanoidTSO && Is64BitMode == other.Is64BitMode && SMCChecks == other.SMCChecks &&
+           x87ReducedPrecision == other.x87ReducedPrecision;
+  }
+  static uint64_t GetHash(const CodeObjectSerializationConfig& other) {
+    // For < 64-bits of data just pack directly
+    // Skip the cookie
+    uint64_t Hash {};
+    Hash <<= 32;
+    Hash |= other.MaxInstPerBlock;
+    Hash <<= 1;
+    Hash |= other.Arch;
+    Hash <<= 1;
+    Hash |= other.MultiBlock;
+    Hash <<= 1;
+    Hash |= other.HardwareTSOEnabled;
+    Hash <<= 1;
+    Hash |= other.TSOEnabled;
+    Hash <<= 1;
+    Hash |= other.ABILocalFlags;
+    Hash <<= 1;
+    Hash |= other.ParanoidTSO;
+    Hash <<= 1;
+    Hash |= other.Is64BitMode;
+    Hash <<= 2;
+    Hash |= other.SMCChecks;
+    Hash <<= 1;
+    Hash |= other.x87ReducedPrecision;
+    return Hash;
+  }
+};
+
+static_assert(sizeof(CodeObjectSerializationConfig) == 16, "Size changed");
+static_assert((sizeof(CodeObjectSerializationConfig) - sizeof(uint64_t)) == 8, "Config size exceeded 64its. Need to change how the hash is "
+                                                                               "generated!");
+} // namespace FEXCore::CodeSerialize

FEXCore/Source/Interface/Core/ObjectCache/JobHandling.cpp

@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: MIT
+#include "Interface/Core/ObjectCache/ObjectCacheService.h"
+
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXHeaderUtils/Filesystem.h>
+
+#include <fcntl.h>
+#include <xxhash.h>
+
+namespace FEXCore::CodeSerialize {
+void AsyncJobHandler::AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string& filename) {
+#ifndef _WIN32
+  // This function adds a named region *JOB* to our named region handler
+  // This needs to be as fast as possible to keep out of the way of the JIT
+
+  const fextl::string BaseFilename = FHU::Filesystem::GetFilename(filename);
+
+  if (!BaseFilename.empty()) {
+    // Create a new entry that once set up will be put in to our section object map
+    auto Entry = fextl::make_unique<CodeRegionEntry>(Base, Size, Offset, filename, NamedRegionHandler->DefaultCodeHeader(Base, Offset));
+
+    // Lock the job ref counter so we can block anything attempting to use the entry before it is loaded
+    Entry->NamedJobRefCountMutex.lock();
+
+    CodeRegionMapType::iterator EntryIterator;
+    {
+      std::unique_lock lk {CodeObjectCacheService->GetEntryMapMutex()};
+
+      auto& EntryMap = CodeObjectCacheService->GetEntryMap();
+
+      auto it = EntryMap.emplace(Base, std::move(Entry));
+      if (!it.second) {
+        // This happens when an application overwrites a previous region without unmapping what was there
+
+        // Lock this entry's Named job reference counter.
+        // Once this passes then we know that this section has been loaded.
+        it.first->second->NamedJobRefCountMutex.lock();
+
+        // Finalize anything the region needs to do first.
+        CodeObjectCacheService->DoCodeRegionClosure(it.first->second->Base, it.first->second.get());
+
+        // munmap the file that was mapped
+        FEXCore::Allocator::munmap(it.first->second->CodeData, it.first->second->FileSize);
+
+        // Remove this entry from the unrelocated map as well
+        {
+          std::unique_lock lk2 {CodeObjectCacheService->GetUnrelocatedEntryMapMutex()};
+          CodeObjectCacheService->GetUnrelocatedEntryMap().erase(it.first->second->EntryHeader.OriginalBase);
+        }
+
+        // Now overwrite the entry in the map
+        it = EntryMap.insert_or_assign(Base, std::move(Entry));
+        EntryIterator = it.first;
+      } else {
+        // No overwrite, just insert
+        EntryIterator = it.first;
+      }
+    }
+
+    // Now that this entry has been added to the map, we can insert a load job using the entry iterator.
+    // This allows us to quickly unblock the JIT thread when it is loading multiple regions and have the async thread
+    // do the loading for us.
+    //
+    // Create the async work queue job now so it can load
+    NamedRegionHandler->AsyncAddNamedRegionWorkItem(BaseFilename, filename, true, EntryIterator);
+
+    // Tell the async thread that it has work to do
+    CodeObjectCacheService->NotifyWork();
+  }
+#endif
+}
+
+void AsyncJobHandler::AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size) {
+#ifndef _WIN32
+  // Removing a named region through the job system
+  // We need to find the entry that we are deleting first
+  fextl::unique_ptr<CodeRegionEntry> EntryPointer;
+  {
+    std::unique_lock lk {CodeObjectCacheService->GetEntryMapMutex()};
+
+    auto& EntryMap = CodeObjectCacheService->GetEntryMap();
+    auto it = EntryMap.find(Base);
+    if (it != EntryMap.end()) {
+      // Lock the job ref counter since we are erasing it
+      // Once this passes it will have been loaded
+      it->second->NamedJobRefCountMutex.lock();
+
+      // Take the pointer from the map
+      EntryPointer = std::move(it->second);
+
+      // We can now unmap the file data
+      FEXCore::Allocator::munmap(EntryPointer->CodeData, EntryPointer->FileSize);
+
+      // Remove this from the entry map
+      EntryMap.erase(it);
+
+      // Remove this entry from the unrelocated map as well
+      {
+        std::unique_lock lk2 {CodeObjectCacheService->GetUnrelocatedEntryMapMutex()};
+        CodeObjectCacheService->GetUnrelocatedEntryMap().erase(EntryPointer->EntryHeader.OriginalBase);
+      }
+    } else {
+      // Tried to remove something that wasn't in our code object tracking
+      return;
+    }
+
+    // Create the async work queue job now so it can finalize what it needs to do
+    NamedRegionHandler->AsyncRemoveNamedRegionWorkItem(Base, Size, std::move(EntryPointer));
+
+    // Tell the async thread that it has work to do
+    CodeObjectCacheService->NotifyWork();
+  }
+#endif
+}
+
+void AsyncJobHandler::AsyncAddSerializationJob(fextl::unique_ptr<SerializationJobData> Data) {
+  // XXX: Actually add serialization job
+}
+} // namespace FEXCore::CodeSerialize

FEXCore/Source/Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: MIT
+#include "Interface/Core/ObjectCache/ObjectCacheService.h"
+
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+
+namespace FEXCore::CodeSerialize {
+NamedRegionObjectHandler::NamedRegionObjectHandler(FEXCore::Context::ContextImpl* ctx) {
+  DefaultSerializationConfig.Cookie = CODE_COOKIE;
+
+  // Initialize the Arch from CPUID
+  uint32_t Arch = ctx->CPUID.RunFunction(0x4000'0001, 0).eax & 0xF;
+  DefaultSerializationConfig.Arch = Arch;
+
+  DefaultSerializationConfig.MaxInstPerBlock = ctx->Config.MaxInstPerBlock;
+  DefaultSerializationConfig.MultiBlock = ctx->Config.Multiblock;
+  DefaultSerializationConfig.TSOEnabled = ctx->Config.TSOEnabled;
+  DefaultSerializationConfig.ABILocalFlags = ctx->Config.ABILocalFlags;
+  DefaultSerializationConfig.ParanoidTSO = ctx->Config.ParanoidTSO;
+  DefaultSerializationConfig.Is64BitMode = ctx->Config.Is64BitMode;
+  DefaultSerializationConfig.SMCChecks = ctx->Config.SMCChecks;
+  DefaultSerializationConfig.x87ReducedPrecision = ctx->Config.x87ReducedPrecision;
+}
+
+void NamedRegionObjectHandler::AddNamedRegionObject(CodeRegionMapType::iterator Entry, const fextl::string& base_filename,
+                                                    const fextl::string& filename, bool Executable) {
+  // XXX: Add named region objects
+
+  // XXX: Until entry loading is complete just claim it is loaded
+  Entry->second->NamedJobRefCountMutex.unlock();
+}
+
+void NamedRegionObjectHandler::RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, fextl::unique_ptr<CodeRegionEntry> Entry) {
+  // XXX: Remove named region objects
+
+  // XXX: Until entry loading is complete just claim it is loaded
+  Entry->NamedJobRefCountMutex.unlock();
+}
+
+void NamedRegionObjectHandler::HandleNamedRegionObjectJobs() {
+  // Walk through all of our jobs sequentially until the work queue is empty
+  while (NamedWorkQueueJobs.load()) {
+    fextl::unique_ptr<AsyncJobHandler::NamedRegionWorkItem> WorkItem;
+
+    {
+      // Lock the work queue mutex for a short moment and grab an item from the list
+      std::unique_lock lk {NamedWorkQueueMutex};
+      size_t WorkItems = WorkQueue.size();
+      if (WorkItems != 0) {
+        WorkItem = std::move(WorkQueue.front());
+        WorkQueue.pop();
+      }
+
+      // Atomically update the number of jobs
+      --NamedWorkQueueJobs;
+    }
+
+    if (WorkItem) {
+      if (WorkItem->GetType() == AsyncJobHandler::NamedRegionJobType::JOB_ADD_NAMED_REGION) {
+        auto WorkAdd = static_cast<AsyncJobHandler::WorkItemAddNamedRegion*>(WorkItem.get());
+        AddNamedRegionObject(WorkAdd->Entry, WorkAdd->BaseFilename, WorkAdd->Filename, WorkAdd->Executable);
+      }
+
+      if (WorkItem->GetType() == AsyncJobHandler::NamedRegionJobType::JOB_REMOVE_NAMED_REGION) {
+        auto WorkRemove = static_cast<AsyncJobHandler::WorkItemRemoveNamedRegion*>(WorkItem.get());
+        RemoveNamedRegionObject(WorkRemove->Base, WorkRemove->Size, std::move(WorkRemove->Entry));
+      }
+    }
+  }
+}
+} // namespace FEXCore::CodeSerialize

FEXCore/Source/Interface/Core/ObjectCache/ObjectCacheService.cpp

@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: MIT
+#include "Interface/Core/ObjectCache/ObjectCacheService.h"
+
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/Utils/Threads.h>
+
+namespace {
+static void* ThreadHandler(void* Arg) {
+  FEXCore::CodeSerialize::CodeObjectSerializeService* This = reinterpret_cast<FEXCore::CodeSerialize::CodeObjectSerializeService*>(Arg);
+  This->ExecutionThread();
+  return nullptr;
+}
+} // namespace
+
+namespace FEXCore::CodeSerialize {
+CodeObjectSerializeService::CodeObjectSerializeService(FEXCore::Context::ContextImpl* ctx)
+  : CTX {ctx}
+  , AsyncHandler {&NamedRegionHandler, this}
+  , NamedRegionHandler {ctx} {
+  Initialize();
+}
+
+void CodeObjectSerializeService::Shutdown() {
+  if (CTX->Config.CacheObjectCodeCompilation() == FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE) {
+    return;
+  }
+
+  WorkerThreadShuttingDown = true;
+
+  // Kick the working thread
+  WorkAvailable.NotifyAll();
+
+  if (WorkerThread->joinable()) {
+    // Wait for worker thread to close down
+    WorkerThread->join(nullptr);
+  }
+}
+
+void CodeObjectSerializeService::Initialize() {
+  // Add a canary so we don't crash on empty map iterator handling
+  auto it = AddressToEntryMap.insert_or_assign(~0ULL, fextl::make_unique<CodeRegionEntry>());
+  UnrelocatedAddressToEntryMap.insert_or_assign(~0ULL, it.first->second.get());
+
+  uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
+  WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+  FEXCore::Threads::SetSignalMask(OldMask);
+}
+
+void CodeObjectSerializeService::DoCodeRegionClosure(uint64_t Base, CodeRegionEntry* it) {
+  if (Base == ~0ULL) {
+    // Don't do closure on canary
+    return;
+  }
+  // XXX: Do code region closure
+}
+
+const CodeObjectFileSection* CodeObjectSerializeService::FetchCodeObjectFromCache(uint64_t GuestRIP) {
+  // XXX: Actually fetch code objects from cache
+  return nullptr;
+}
+
+void CodeObjectSerializeService::ExecutionThread() {
+  // Set our thread name so we can see its relation
+  FEXCore::Threads::SetThreadName("ObjectCodeSeri\0");
+  while (WorkerThreadShuttingDown.load() != true) {
+    // Wait for work
+    WorkAvailable.Wait();
+
+    // Handle named region async jobs first. Highest priority
+    NamedRegionHandler.HandleNamedRegionObjectJobs();
+
+    // XXX: Handle code serialization jobs second.
+  }
+
+  // Do final code region closures on thread shutdown
+  for (auto& it : AddressToEntryMap) {
+    DoCodeRegionClosure(it.first, it.second.get());
+  }
+
+  // Safely clear our maps now
+  AddressToEntryMap.clear();
+  UnrelocatedAddressToEntryMap.clear();
+}
+} // namespace FEXCore::CodeSerialize

FEXCore/Source/Interface/Core/ObjectCache/ObjectCacheService.h

@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+#include "Interface/Context/Context.h"
+#include "Interface/Core/ObjectCache/Relocations.h"
+#include "Interface/Core/ObjectCache/CodeObjectSerializationConfig.h"
+#include "Interface/IR/AOTIR.h"
+
+#include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/queue.h>
+#include <FEXCore/fextl/robin_map.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
+
+#include <shared_mutex>
+
+namespace FEXCore::CodeSerialize {
+// XXX: Does this need to be signal safe?
+using CodeSerializationMutex = std::shared_mutex;
+struct CodeSerializationData {};
+
+struct CodeObjectFileSection {
+  bool Serialized;
+  bool Invalid;
+  const CodeSerializationData* Data;
+  const char* HostCode;
+  uint64_t NumRelocations;
+  const char* Relocations;
+};
+
+/**
+ * @brief This is the file header that lives at the start of an object cache file
+ *
+ * This header is updated from multiple processes!
+ * Care must be taken to use OS locks when updating the file backing including this header
+ */
+struct CodeObjectSerializationHeader {
+  // The configuration that this file has
+  CodeObjectSerializationConfig Config;
+  // The original RIP that this object section was mapped at
+  uint64_t OriginalBase {};
+  // The original offset in to the file that this object section was loaded from
+  uint64_t OriginalOffset {};
+  // Total amount of code that should be in this file
+  uint64_t TotalCodeSize {};
+  // Used to reserve the TSL map
+  uint64_t NumCodeEntries {};
+  // The number of relocations that point to this section
+  uint64_t NumRelocationsTo {};
+  // Total relocations in this file
+  uint64_t TotalRelocationsCount {};
+};
+
+struct CodeRegionEntry {
+  /**
+   * @name Threaded initialization objects for the initial object creation
+   * @{ */
+  // Base address in memory where the code region is at
+  uint64_t Base {};
+
+  // Size of this code entry
+  uint64_t Size {};
+
+  // The offset inside the file that is mapped to Base
+  uint64_t Offset {};
+
+  // Filename of the object
+  fextl::string Filename {};
+
+  CodeObjectSerializationHeader EntryHeader {};
+  /**  @} */
+
+  // The filename of the object cache for this entry
+  fextl::string ObjectEntrySourceFilename {};
+
+  // In the case of file corruption that we can detect, we can disable serialization early for an entry
+  // We should be resiliant to corruption but things happen
+  bool StillSerializing {true};
+
+  // Long lived FD for serialization if we have multiple jobs to serialize
+  // Bursts of code entries are common and this reduces file lock overhead
+  //
+  // Especially useful over network mounts where file locks are very slow
+  int CurrentSerializedFD {-1};
+
+  /**
+   * @name Objects required to sync objects between threads
+   * @{ */
+  // Refcount for the number of outstanding code entries waiting to be written for this object section
+  CodeSerializationMutex ObjectJobRefCountMutex;
+
+  // Refcount for outstanding named object region entry loading itself
+  // Will block JIT code cache look up when this has a unique_lock held
+  CodeSerializationMutex NamedJobRefCountMutex;
+  /**  @} */
+
+  /**
+   * @name Object Entry data management
+   * @{ */
+
+  /**
+   * @name This is the raw file data that we loaded from the code region entry file
+   * @{ */
+  char* CodeData {};
+  size_t FileSize {};
+
+  fextl::vector<CodeObjectFileSection> FileCodeSections;
+  /**  @} */
+
+  // This per section map takes the most time to load and needs to be quick
+  // This is the map of all code segments for this entry
+  fextl::robin_map<uint64_t, CodeObjectFileSection*> SectionLookupMap {};
+  /**  @} */
+
+  // Default initialization
+  CodeRegionEntry() = default;
+
+  // Initializer specifically for threaded loading
+  CodeRegionEntry(uint64_t Base, uint64_t Size, uint64_t Offset, const fextl::string& Filename, const CodeObjectSerializationHeader& DefaultHeader)
+    : Base {Base}
+    , Size {Size}
+    , Offset {Offset}
+    , Filename {Filename}
+    , EntryHeader {DefaultHeader} {}
+};
+
+// Map type must use an interator that isn't invalidation on erase/insert
+using CodeRegionMapType = fextl::map<uint64_t, fextl::unique_ptr<CodeRegionEntry>>;
+using CodeRegionPtrMapType = fextl::map<uint64_t, CodeRegionEntry*>;
+
+class NamedRegionObjectHandler;
+class CodeObjectSerializeService;
+
+class AsyncJobHandler final {
+public:
+  /**
+   * @brief Structure containing all the data required to async serialize code objects
+   */
+  struct SerializationJobData {
+    uint64_t GuestRIP; ///< The RIP for the guest
+    // XXX: Support multiblock
+    uint64_t GuestCodeLength; ///< The Guest's code length
+    uint64_t GuestCodeHash;   ///< Hash of the guest code
+
+    void* HostCodeBegin;   ///< Host JIT code starting memory address
+    size_t HostCodeLength; ///< Host JIT code length
+    uint64_t HostCodeHash; ///< Host JIT code hash before any backpatching
+
+    // This is the thread specific ref counter for outstanding jobs.
+    // This shared mutex is incremented when the job is added, then decremented when the job is complete.
+    // If a thread is shutting down or clearing code cache then the thread will pull a unique lock on this mutex.
+    // This way it will wait until the async job handler is complete with it.
+    CodeSerializationMutex* ThreadJobRefCount;
+
+    // These are the reolocations for this serialization job
+    // Relatively small number of entries most of the time
+    fextl::vector<FEXCore::CPU::Relocation> Relocations;
+
+    /**
+     * @name Objects filled in from the Code Object Serialization service when a job is added
+     * @{ */
+    // This is the code region's ref counter for outstanding jobs.
+    // This shared mutex is incremented when the job is added, then decremented when the job is complete.
+    // If a named region is being removed then a unique lock will be pulled to wait for all jobs to complete and no new jobs to be added.
+    CodeSerializationMutex* ObjectJobRefCountMutexPtr;
+
+    // This is the code region iterator to reduce the number of map lookups
+    // This will remain valid while jobs are outstanding for this region
+    CodeRegionMapType::iterator CodeRegionIterator;
+    /**  @} */
+  };
+
+  AsyncJobHandler(NamedRegionObjectHandler* NamedRegionHandler, CodeObjectSerializeService* CodeObjectCacheService)
+    : NamedRegionHandler {NamedRegionHandler}
+    , CodeObjectCacheService {CodeObjectCacheService} {}
+
+protected:
+  friend class CodeObjectSerializeService;
+  friend class NamedRegionObjectHandler;
+  /**
+   * @name Async job submission functions
+   * @{ */
+  void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string& filename);
+  void AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size);
+  void AsyncAddSerializationJob(fextl::unique_ptr<SerializationJobData> Data);
+  /**  @} */
+
+  /**
+   * @name Async named region handling
+   * @{ */
+  /**
+   * @brief The async named region jobs to handle.
+   *
+   * Only two, Code serialization goes in to a different queue.
+   */
+  enum class NamedRegionJobType {
+    JOB_ADD_NAMED_REGION,
+    JOB_REMOVE_NAMED_REGION,
+  };
+
+  class NamedRegionWorkItem {
+  public:
+    NamedRegionJobType GetType() const {
+      return Type;
+    }
+
+  protected:
+    friend class WorkItemAddNamedRegion;
+    NamedRegionWorkItem(NamedRegionJobType type)
+      : Type {type} {}
+
+  private:
+    NamedRegionJobType Type;
+  };
+
+  class WorkItemAddNamedRegion : public NamedRegionWorkItem {
+  public:
+    WorkItemAddNamedRegion(const fextl::string& base, const fextl::string& filename, bool executable, CodeRegionMapType::iterator entry)
+      : NamedRegionWorkItem {NamedRegionJobType::JOB_ADD_NAMED_REGION}
+      , BaseFilename {base}
+      , Filename {filename}
+      , Executable {executable}
+      , Entry {entry} {}
+    const fextl::string BaseFilename;
+    const fextl::string Filename;
+    bool Executable;
+    CodeRegionMapType::iterator Entry;
+  };
+
+  class WorkItemRemoveNamedRegion : public NamedRegionWorkItem {
+  public:
+    WorkItemRemoveNamedRegion(uint64_t base, uint64_t size, fextl::unique_ptr<CodeRegionEntry> entry)
+      : NamedRegionWorkItem {NamedRegionJobType::JOB_REMOVE_NAMED_REGION}
+      , Base {base}
+      , Size {size}
+      , Entry {std::move(entry)} {}
+
+    uint64_t Base;
+    uint64_t Size;
+    fextl::unique_ptr<CodeRegionEntry> Entry;
+  };
+  /**  @} */
+
+private:
+  NamedRegionObjectHandler* NamedRegionHandler;
+  CodeObjectSerializeService* CodeObjectCacheService;
+};
+
+class NamedRegionObjectHandler final {
+public:
+  NamedRegionObjectHandler(FEXCore::Context::ContextImpl* ctx);
+
+  void HandleNamedRegionObjectJobs();
+
+  const CodeObjectSerializationConfig& GetDefaultSerializationConfig() const {
+    return DefaultSerializationConfig;
+  }
+
+protected:
+  friend class AsyncJobHandler;
+
+  // Return a default code header based off the default serialization config
+  CodeObjectSerializationHeader DefaultCodeHeader(uint64_t Base, uint64_t Offset) const {
+    return CodeObjectSerializationHeader {
+      .Config = DefaultSerializationConfig,
+      .OriginalBase = Base,
+      .OriginalOffset = Offset,
+      .NumCodeEntries = 0,
+      .NumRelocationsTo = 0,
+      .TotalRelocationsCount = 0,
+    };
+  }
+
+  /**
+   * @brief Adds an asynchronous add named region work item to the object queue
+   *
+   * This adds the job that will do the loading of file resources and data tracking.
+   */
+  void AsyncAddNamedRegionWorkItem(const fextl::string& base, const fextl::string& filename, bool executable, CodeRegionMapType::iterator entry) {
+    std::unique_lock lk {NamedWorkQueueMutex};
+    WorkQueue.emplace(fextl::make_unique<AsyncJobHandler::WorkItemAddNamedRegion>(base, filename, executable, entry));
+    ++NamedWorkQueueJobs;
+  }
+
+  void AsyncRemoveNamedRegionWorkItem(uint64_t Base, uint64_t Size, fextl::unique_ptr<CodeRegionEntry> Entry) {
+    std::unique_lock lk {NamedWorkQueueMutex};
+    WorkQueue.emplace(fextl::make_unique<AsyncJobHandler::WorkItemRemoveNamedRegion>(Base, Size, std::move(Entry)));
+    ++NamedWorkQueueJobs;
+  }
+
+private:
+  // Code version. If the code emission changes then this needs to increment
+  constexpr static uint32_t CODE_VERSION = 0x0;
+
+  // Default cookie header for the file header
+  constexpr static uint64_t CODE_COOKIE = FEXCore::IR::COOKIE_VERSION("FEXC", CODE_VERSION);
+
+  // Code serialization config for our current process configuration
+  CodeObjectSerializationConfig DefaultSerializationConfig;
+
+  // Atomic counter for number of jobs in the queue without needing to pull the mutex to check
+  std::atomic<uint64_t> NamedWorkQueueJobs {};
+
+  // Mutex for ading new jobs to the work queue
+  std::mutex NamedWorkQueueMutex {};
+
+  // The job queue itself
+  // Jobs get consumed as a FIFO
+  // Jobs always get appended to the end
+  fextl::queue<fextl::unique_ptr<AsyncJobHandler::NamedRegionWorkItem>> WorkQueue {};
+
+  /**
+   * @name Named Region object handling
+   * @{ */
+  void AddNamedRegionObject(CodeRegionMapType::iterator Entry, const fextl::string& base_filename, const fextl::string& filename, bool Executable);
+  void RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, fextl::unique_ptr<CodeRegionEntry> Entry);
+  /**  @} */
+};
+
+/**
+ * @brief Context specific code object serialization class
+ *
+ * Contains everything required for FEXCore to serialize code objects
+ */
+class CodeObjectSerializeService final {
+public:
+  CodeObjectSerializeService(FEXCore::Context::ContextImpl* ctx);
+
+  /**
+   * @brief Initialize the internal interface
+   *
+   * Is a public interface to allow the service to reinitialize after forking
+   */
+  void Initialize();
+
+  /**
+   * @brief Safely shut down the Code Object serialization service.
+   *
+   * This service needs to be resiliant to application crashes, but shutting down safely is still preferred.
+   */
+  void Shutdown();
+
+  /**
+   * @name Async interface
+   * @{ */
+  /**
+   * @brief Loads a named region in to the code serialization service. As async as possible.
+   *
+   * @param Base - Virtual address that this named region is loaded
+   * @param Size - The size of the region
+   * @param Offset - The offset from the file
+   * @param filename - The filename itself
+   */
+  void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string& filename) {
+    AsyncHandler.AsyncAddNamedRegionJob(Base, Size, Offset, filename);
+  }
+
+  /**
+   * @brief Unloads a named region from the code serialization service. As async as possible.
+   *
+   * @param Base - Virtual address of the named region
+   * @param Size - The size of the region
+   */
+  void AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size) {
+    AsyncHandler.AsyncRemoveNamedRegionJob(Base, Size);
+  }
+
+  /**
+   * @brief Adds a code object serialization job. As async as possible.
+   * Code hashing happens prior to async job serialization to catch invalidations due to backpatching.
+   *
+   * @param Data - A fully filled out struct containing all the code serialization
+   */
+  void AsyncAddSerializationJob(fextl::unique_ptr<AsyncJobHandler::SerializationJobData> Data) {
+    AsyncHandler.AsyncAddSerializationJob(std::move(Data));
+  }
+  /**  @} */
+
+  /**
+   * @name Synchronous interface
+   * @{ */
+  /**
+   * @brief Synchronously waits for this thread's job queue to become empty.
+   *
+   * This is necessary for when a thread is shutting down
+   *
+   * @param ThreadJobRefCount - The shared mutex to wait on until to be empty
+   */
+  static void WaitForEmptyJobQueue(CodeSerializationMutex* ThreadJobRefCount) {
+    // Once the shared mutex is empty this unique lock will be gained
+    std::unique_lock lk {*ThreadJobRefCount};
+  }
+
+  /**
+   * @brief Fetches object code from the Code Object Cache for JIT.
+   *
+   * @param GuestRIP - Which GuestRIP to search the cache for
+   *
+   * @return Data required for the JIT to relocate the Object code.
+   */
+  const CodeObjectFileSection* FetchCodeObjectFromCache(uint64_t GuestRIP);
+  /**  @} */
+
+  // Public for threading
+  void ExecutionThread();
+
+protected:
+  friend class AsyncJobHandler;
+
+  /**
+   * @brief Safely closes out code object regions from the map
+   *
+   * @param it - iterator to do a closure on
+   */
+  void DoCodeRegionClosure(uint64_t Base, CodeRegionEntry* it);
+
+  CodeSerializationMutex& GetEntryMapMutex() {
+    return EntryMapMutex;
+  }
+  CodeSerializationMutex& GetUnrelocatedEntryMapMutex() {
+    return EntryMapMutex;
+  }
+
+  CodeRegionMapType& GetEntryMap() {
+    return AddressToEntryMap;
+  }
+  CodeRegionPtrMapType& GetUnrelocatedEntryMap() {
+    return UnrelocatedAddressToEntryMap;
+  }
+
+  /**
+   * @brief Notify the async thread that it has work to do
+   */
+  void NotifyWork() {
+    WorkAvailable.NotifyOne();
+  }
+
+private:
+  FEXCore::Context::ContextImpl* CTX;
+
+  Event WorkAvailable {};
+  fextl::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
+  std::atomic_bool WorkerThreadShuttingDown {false};
+  AsyncJobHandler AsyncHandler;
+  NamedRegionObjectHandler NamedRegionHandler;
+
+  // Mutex to hold when modifying the entry maps
+  CodeSerializationMutex EntryMapMutex;
+  CodeSerializationMutex UnrelocatedEntryMapMutex;
+
+  // Entry maps
+  CodeRegionMapType AddressToEntryMap;
+  CodeRegionPtrMapType UnrelocatedAddressToEntryMap;
+};
+} // namespace FEXCore::CodeSerialize

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -27,6 +27,8 @@
 #include <xxhash.h>
 
 namespace FEXCore::IR {
+class Pass;
+class PassManager;
 
 enum class MemoryAccessType {
   // Choose TSO or Non-TSO depending on access type
@@ -85,6 +87,9 @@ struct DispatchTableEntry {
 };
 
 class OpDispatchBuilder final : public IREmitter {
+  friend class FEXCore::IR::Pass;
+  friend class FEXCore::IR::PassManager;
+
 public:
   Ref GetNewJumpBlock(uint64_t RIP) {
     auto it = JumpTargets.find(RIP);
@@ -196,7 +201,8 @@ public:
         const auto GPRSize = GetGPROpSize();
         // If we don't have a jump target to a new block then we have to leave
         // Set the RIP to the next instruction and leave
-        ExitFunction(_InlineEntrypointOffset(GPRSize, NextRIP - Entry));
+        auto RelocatedNextRIP = _EntrypointOffset(GPRSize, NextRIP - Entry);
+        ExitFunction(RelocatedNextRIP);
       } else if (it != JumpTargets.end()) {
         Jump(it->second.BlockEntry);
         return true;
@@ -209,17 +215,10 @@ public:
   }
 
   static bool CanHaveSideEffects(const FEXCore::X86Tables::X86InstInfo* TableInfo, FEXCore::X86Tables::DecodedOp Op) {
-    if (TableInfo) {
-      if (TableInfo->Flags & X86Tables::InstFlags::FLAGS_DEBUG_MEM_ACCESS) {
-        // If it is marked as having memory access then always say it has a side-effect.
-        // Not always true but better to be safe.
-        return true;
-      }
-
-      if (TableInfo->Flags & (X86Tables::InstFlags::FLAGS_SETS_RIP | X86Tables::InstFlags::FLAGS_BLOCK_END)) {
-        // Cooperative suspend interrupts can be triggered at any back-edge, the RIP must be reconstructed correctly in such cases
-        return true;
-      }
+    if (TableInfo && TableInfo->Flags & X86Tables::InstFlags::FLAGS_DEBUG_MEM_ACCESS) {
+      // If it is marked as having memory access then always say it has a side-effect.
+      // Not always true but better to be safe.
+      return true;
     }
 
     auto CanHaveSideEffects = false;
@@ -267,6 +266,7 @@ public:
   }
 
   OpDispatchBuilder(FEXCore::Context::ContextImpl* ctx);
+  OpDispatchBuilder(FEXCore::Utils::IntrusivePooledAllocator& Allocator);
 
   void ResetWorkingList();
   void ResetDecodeFailure() {
@@ -300,8 +300,7 @@ public:
     return ShouldDump;
   }
 
-  void BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions,
-                     bool Is64BitMode, bool MonoBackpatcherBlock);
+  void BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions, bool Is64BitMode);
   void Finalize();
 
   // Dispatch builder functions
@@ -318,7 +317,6 @@ public:
 
   void UnhandledOp(OpcodeArgs);
   void MOVGPROp(OpcodeArgs, uint32_t SrcIndex);
-  void MOVGPRImmediate(OpcodeArgs);
   void MOVGPRNTOp(OpcodeArgs);
   void MOVVectorAlignedOp(OpcodeArgs);
   void MOVVectorUnalignedOp(OpcodeArgs);
@@ -352,9 +350,6 @@ public:
   void LoopOp(OpcodeArgs);
   void JUMPOp(OpcodeArgs);
   void JUMPAbsoluteOp(OpcodeArgs);
-  void JUMPFARIndirectOp(OpcodeArgs);
-  void CALLFARIndirectOp(OpcodeArgs);
-  void RETFARIndirectOp(OpcodeArgs);
   void TESTOp(OpcodeArgs, uint32_t SrcIndex);
   void MOVSXDOp(OpcodeArgs);
   void MOVSXOp(OpcodeArgs);
@@ -740,7 +735,6 @@ public:
   void FADD(OpcodeArgs, IR::OpSize Width, bool Integer, OpResult ResInST0);
   void FDIV(OpcodeArgs, IR::OpSize Width, bool Integer, bool Reverse, OpResult ResInST0);
   void FMUL(OpcodeArgs, IR::OpSize Width, bool Integer, OpResult ResInST0);
-  void FNCLEX(OpcodeArgs);
   void FNINIT(OpcodeArgs);
   void FSUB(OpcodeArgs, IR::OpSize Width, bool Integer, bool Reverse, OpResult ResInST0);
   void FTST(OpcodeArgs);
@@ -855,6 +849,8 @@ public:
 
   void PSADBW(OpcodeArgs);
 
+  Ref BitwiseAtLeastTwo(Ref A, Ref B, Ref C);
+
   void SHA1NEXTEOp(OpcodeArgs);
   void SHA1MSG1Op(OpcodeArgs);
   void SHA1MSG2Op(OpcodeArgs);
@@ -944,6 +940,7 @@ public:
   RefVSIB AVX128_LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags, bool NeedsHigh);
   void AVX128_StoreResult_WithOpSize(FEXCore::X86Tables::DecodedOp Op, const FEXCore::X86Tables::DecodedOperand& Operand, const RefPair Src,
                                      MemoryAccessType AccessType = MemoryAccessType::DEFAULT);
+  void InstallAVX128Handlers();
   void AVX128_VMOVScalarImpl(OpcodeArgs, IR::OpSize ElementSize);
   void AVX128_VectorALU(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
   void AVX128_VectorUnary(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
@@ -972,26 +969,39 @@ public:
   void AVX128_VMOVDDUP(OpcodeArgs);
   void AVX128_VMOVSLDUP(OpcodeArgs);
   void AVX128_VMOVSHDUP(OpcodeArgs);
-  void AVX128_VBROADCAST(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_VPUNPCKL(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_VPUNPCKH(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VBROADCAST(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPUNPCKL(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPUNPCKH(OpcodeArgs);
   void AVX128_MOVVectorUnaligned(OpcodeArgs);
-  void AVX128_InsertCVTGPR_To_FPR(OpcodeArgs, IR::OpSize DstElementSize);
-  void AVX128_CVTFPR_To_GPR(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode);
+  template<IR::OpSize DstElementSize>
+  void AVX128_InsertCVTGPR_To_FPR(OpcodeArgs);
+  template<IR::OpSize SrcElementSize, bool HostRoundingMode>
+  void AVX128_CVTFPR_To_GPR(OpcodeArgs);
   void AVX128_VANDN(OpcodeArgs);
-  void AVX128_VPACKSS(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_VPACKUS(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPACKSS(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPACKUS(OpcodeArgs);
   Ref AVX128_PSIGNImpl(IR::OpSize ElementSize, Ref Src1, Ref Src2);
-  void AVX128_VPSIGN(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_UCOMISx(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPSIGN(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_UCOMISx(OpcodeArgs);
   void AVX128_VectorScalarInsertALU(OpcodeArgs, FEXCore::IR::IROps IROp, IR::OpSize ElementSize);
   Ref AVX128_VFCMPImpl(IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t CompType);
-  void AVX128_VFCMP(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_InsertScalarFCMP(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VFCMP(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_InsertScalarFCMP(OpcodeArgs);
   void AVX128_MOVBetweenGPR_FPR(OpcodeArgs);
-  void AVX128_PExtr(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_PExtr(OpcodeArgs);
   void AVX128_ExtendVectorElements(OpcodeArgs, IR::OpSize ElementSize, IR::OpSize DstElementSize, bool Signed);
-  void AVX128_MOVMSK(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_MOVMSK(OpcodeArgs);
   void AVX128_MOVMSKB(OpcodeArgs);
   void AVX128_PINSRImpl(OpcodeArgs, IR::OpSize ElementSize, const X86Tables::DecodedOperand& Src1Op,
                         const X86Tables::DecodedOperand& Src2Op, const X86Tables::DecodedOperand& Imm);
@@ -1005,25 +1015,33 @@ public:
   void AVX128_VINSERTPS(OpcodeArgs);
 
   Ref AVX128_PHSUBImpl(Ref Src1, Ref Src2, size_t ElementSize);
-  void AVX128_VPHSUB(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPHSUB(OpcodeArgs);
 
   void AVX128_VPHSUBSW(OpcodeArgs);
 
-  void AVX128_VADDSUBP(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VADDSUBP(OpcodeArgs);
 
-  void AVX128_VPMULL(OpcodeArgs, IR::OpSize ElementSize, bool Signed);
+  template<IR::OpSize ElementSize, bool Signed>
+  void AVX128_VPMULL(OpcodeArgs);
 
   void AVX128_VPMULHRSW(OpcodeArgs);
 
-  void AVX128_VPMULHW(OpcodeArgs, bool Signed);
+  template<bool Signed>
+  void AVX128_VPMULHW(OpcodeArgs);
 
-  void AVX128_InsertScalar_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize);
+  template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
+  void AVX128_InsertScalar_CVT_Float_To_Float(OpcodeArgs);
 
-  void AVX128_Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize);
+  template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
+  void AVX128_Vector_CVT_Float_To_Float(OpcodeArgs);
 
-  void AVX128_Vector_CVT_Float_To_Int(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode);
+  template<IR::OpSize SrcElementSize, bool HostRoundingMode>
+  void AVX128_Vector_CVT_Float_To_Int(OpcodeArgs);
 
-  void AVX128_Vector_CVT_Int_To_Float(OpcodeArgs, IR::OpSize SrcElementSize, bool Widen);
+  template<IR::OpSize SrcElementSize, bool Widen>
+  void AVX128_Vector_CVT_Int_To_Float(OpcodeArgs);
 
   void AVX128_VEXTRACT128(OpcodeArgs);
   void AVX128_VAESImc(OpcodeArgs);
@@ -1040,28 +1058,36 @@ public:
 
   void AVX128_PHMINPOSUW(OpcodeArgs);
 
-  void AVX128_VectorRound(OpcodeArgs, IR::OpSize ElementSize);
-  void AVX128_InsertScalarRound(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VectorRound(OpcodeArgs);
+  template<IR::OpSize ElementSize>
+  void AVX128_InsertScalarRound(OpcodeArgs);
 
-  void AVX128_VDPP(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VDPP(OpcodeArgs);
   void AVX128_VPERMQ(OpcodeArgs);
 
   void AVX128_VPSHUFW(OpcodeArgs, bool Low);
 
-  void AVX128_VSHUF(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VSHUF(OpcodeArgs);
 
-  void AVX128_VPERMILImm(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPERMILImm(OpcodeArgs);
 
-  void AVX128_VHADDP(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
+  template<IROps IROp, IR::OpSize ElementSize>
+  void AVX128_VHADDP(OpcodeArgs);
 
   void AVX128_VPHADDSW(OpcodeArgs);
 
   void AVX128_VPMADDUBSW(OpcodeArgs);
   void AVX128_VPMADDWD(OpcodeArgs);
 
-  void AVX128_VBLEND(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VBLEND(OpcodeArgs);
 
-  void AVX128_VHSUBP(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VHSUBP(OpcodeArgs);
 
   void AVX128_VPSHUFB(OpcodeArgs);
   void AVX128_VPSADBW(OpcodeArgs);
@@ -1072,23 +1098,28 @@ public:
   void AVX128_VMASKMOVImpl(OpcodeArgs, IR::OpSize ElementSize, IR::OpSize DstSize, bool IsStore, const X86Tables::DecodedOperand& MaskOp,
                            const X86Tables::DecodedOperand& DataOp);
 
-  void AVX128_VPMASKMOV(OpcodeArgs, bool IsStore);
+  template<bool IsStore>
+  void AVX128_VPMASKMOV(OpcodeArgs);
 
-  void AVX128_VMASKMOV(OpcodeArgs, IR::OpSize ElementSize, bool IsStore);
+  template<IR::OpSize ElementSize, bool IsStore>
+  void AVX128_VMASKMOV(OpcodeArgs);
 
   void AVX128_MASKMOV(OpcodeArgs);
 
-  void AVX128_VectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VectorVariableBlend(OpcodeArgs);
 
   void AVX128_SaveAVXState(Ref MemBase);
   void AVX128_RestoreAVXState(Ref MemBase);
   void AVX128_DefaultAVXState();
 
   void AVX128_VPERM2(OpcodeArgs);
-  void AVX128_VTESTP(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VTESTP(OpcodeArgs);
   void AVX128_PTest(OpcodeArgs);
 
-  void AVX128_VPERMILReg(OpcodeArgs, IR::OpSize ElementSize);
+  template<IR::OpSize ElementSize>
+  void AVX128_VPERMILReg(OpcodeArgs);
 
   void AVX128_VPERMD(OpcodeArgs);
 
@@ -1101,7 +1132,8 @@ public:
   RefPair AVX128_VPGatherQPSImpl(Ref Dest, Ref Mask, RefVSIB VSIB);
   RefPair AVX128_VPGatherImpl(OpSize Size, OpSize ElementLoadSize, OpSize AddrElementSize, RefPair Dest, RefPair Mask, RefVSIB VSIB);
 
-  void AVX128_VPGATHER(OpcodeArgs, OpSize AddrElementSize);
+  template<OpSize AddrElementSize>
+  void AVX128_VPGATHER(OpcodeArgs);
 
   void AVX128_VCVTPH2PS(OpcodeArgs);
   void AVX128_VCVTPS2PH(OpcodeArgs);
@@ -1135,10 +1167,6 @@ public:
     StoreXMMRegister(XMM, Value);
   }
 
-  void AVXVectorALUOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
-  void AVXVectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
-  void AVXVectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize);
-
   // End of AVX 256-bit implementation
 
   void InvalidOp(OpcodeArgs);
@@ -1161,42 +1189,13 @@ public:
     }
   }
 
-  void StoreContextHelper(IR::OpSize Size, RegisterClassType Class, Ref Value, uint32_t Offset) {
-    // For i128Bit, we won't see a normal Constant to inline, but as a special
-    // case we can replace with a 2x64-bit store which can use inline zeroes.
-    if (Size == OpSize::i128Bit) {
-      auto Header = GetOpHeader(WrapNode(Value));
-      const auto MAX_STP_OFFSET = (252 * 4);
-
-      if (Offset <= MAX_STP_OFFSET && Header->Op == OP_LOADNAMEDVECTORCONSTANT) {
-        auto Const = Header->C<IR::IROp_LoadNamedVectorConstant>();
-
-        if (Const->Constant == IR::NamedVectorConstant::NAMED_VECTOR_ZERO) {
-          Ref Zero = _Constant(0);
-          Ref STP = _StoreContextPair(IR::OpSize::i64Bit, GPRClass, Zero, Zero, Offset);
-
-          // XXX: This works around InlineConstant not having an associated
-          // register class, else we'd just do InlineConstant above.
-          Ref InlineZero = _InlineConstant(0);
-          ReplaceNodeArgument(STP, 0, InlineZero);
-          ReplaceNodeArgument(STP, 1, InlineZero);
-          return;
-        }
-      }
-    }
-
-    _StoreContext(Size, Class, Value, Offset);
-  }
-
-  void FlushRegisterCache(bool SRAOnly = false, bool MMXOnly = false) {
+  void FlushRegisterCache(bool SRAOnly = false) {
     // At block boundaries, fix up the carry flag.
     if (!SRAOnly) {
       RectifyCarryInvert(CFInvertedABI);
     }
 
-    if (!MMXOnly) {
-      CalculateDeferredFlags();
-    }
+    CalculateDeferredFlags();
 
     const auto GPRSize = GetGPROpSize();
     const auto VectorSize = GetGuestVectorLength();
@@ -1218,11 +1217,6 @@ public:
       Bits &= Mask;
     }
 
-    if (MMXOnly) {
-      Mask &= ((1ull << (MM7Index - MM0Index + 1)) - 1) << MM0Index;
-      Bits &= Mask;
-    }
-
     while (Bits != 0) {
       uint32_t Index = 63 - std::countl_zero(Bits);
       Ref Value = RegCache.Value[Index];
@@ -1260,7 +1254,7 @@ public:
           _StoreContextPair(Size, Class, ValueNext, Value, Offset - SizeInt);
           Bits &= ~NextBit;
         } else {
-          StoreContextHelper(Size, Class, Value, Offset);
+          _StoreContext(Size, Class, Value, Offset);
           // If Partial and MMX register, then we need to store all 1s in bits 64-80
           if (Partial && Index >= MM0Index && Index <= MM7Index) {
             _StoreContext(OpSize::i16Bit, IR::GPRClass, Constant(0xFFFF), Offset + 8);
@@ -1382,6 +1376,11 @@ private:
 
   Ref ADDSUBPOpImpl(OpSize Size, IR::OpSize ElementSize, Ref Src1, Ref Src2);
 
+  void AVXVectorALUOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
+  void AVXVectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize);
+
+  void AVXVectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize);
+
   void AVXVariableShiftImpl(OpcodeArgs, IROps IROp);
 
   Ref AESKeyGenAssistImpl(OpcodeArgs);
@@ -1522,23 +1521,7 @@ private:
   void StoreGPRRegister(uint32_t GPR, const Ref Src, IR::OpSize Size = OpSize::iInvalid, uint8_t Offset = 0);
   void StoreXMMRegister(uint32_t XMM, const Ref Src);
 
-  Ref _GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, bool Inline) {
-    const auto GPRSize = GetGPROpSize();
-    const auto Offs = Op->PC + Op->InstSize + Offset - Entry;
-    return Inline ? _InlineEntrypointOffset(GPRSize, Offs) : _EntrypointOffset(GPRSize, Offs);
-  }
-
-  Ref GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) {
-    return _GetRelocatedPC(Op, Offset, false);
-  }
-
-  void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) {
-    ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */));
-  }
-
-  void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock) {
-    ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */), Hint, CallReturnAddress, CallReturnBlock);
-  }
+  Ref GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0);
 
   [[nodiscard]]
   static bool IsOperandMem(const X86Tables::DecodedOperand& Operand, bool Load) {
@@ -1667,7 +1650,7 @@ private:
     // This is currently worse for 8/16-bit, but that should be optimized. TODO
     if (SrcSize >= OpSize::i32Bit) {
       if (SetPF) {
-        CalculatePF(SubWithFlags(SrcSize, Res, (uint64_t)0));
+        CalculatePF(_SubWithFlags(SrcSize, Res, Constant(0)));
       } else {
         _SubNZCV(SrcSize, Res, Constant(0));
       }
@@ -1854,10 +1837,10 @@ private:
   static const int PFIndex = 16;
   static const int AFIndex = 17;
   /* Gap 18..19 */
-  /* Note this range is only valid if MMXState = MMXState_MMX */
   static const int MM0Index = 20;
   static const int MM7Index = 27;
-  /* Gap 28..30 */
+  static const int AbridgedFTWIndex = 28;
+  /* Gap 29..30 */
   static const int DFIndex = 31;
   static const int FPR0Index = 32;
   static const int FPR15Index = 47;
@@ -1869,6 +1852,7 @@ private:
     switch (Index) {
     case MM0Index ... MM7Index: return offsetof(FEXCore::Core::CPUState, mm[Index - MM0Index]);
     case AVXHigh0Index ... AVXHigh15Index: return offsetof(FEXCore::Core::CPUState, avx_high[Index - AVXHigh0Index][0]);
+    case AbridgedFTWIndex: return offsetof(FEXCore::Core::CPUState, AbridgedFTW);
     default: return ~0U;
     }
   }
@@ -1930,7 +1914,7 @@ private:
     if (!(RegCache.Cached & Bit)) {
       if (Index == DFIndex) {
         RegCache.Value[Index] = _LoadDF();
-      } else if ((Index >= MM0Index && Index <= MM7Index) || Index >= AVXHigh0Index) {
+      } else if ((Index >= MM0Index && Index <= AbridgedFTWIndex) || Index >= AVXHigh0Index) {
         RegCache.Value[Index] = _LoadContext(Size, RegClass, Offset);
 
         // We may have done a partial load, this requires special handling.
@@ -2052,7 +2036,7 @@ private:
       } else {
         // Because we explicitly inverted for CF above, we use the unsafe
         // _NZCVSelect rather than the safe CF-aware version.
-        return _NZCVSelect01(CondForNZCVBit(BitOffset, Invert));
+        return _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(BitOffset, Invert), Constant(1), Constant(0));
       }
     } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) {
       return LoadGPR(Core::CPUState::PF_AS_GREG);
@@ -2149,7 +2133,7 @@ private:
   void ConvertNZCVToX87() {
     LOGMAN_THROW_A_FMT(NZCVDirty && CachedNZCV, "NZCV must be saved");
 
-    Ref V = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_OF_RAW_LOC, false));
+    Ref V = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_OF_RAW_LOC, false), Constant(1), Constant(0));
 
     if (CTX->HostFeatures.SupportsFlagM2) {
       // Convert to x86 flags, saves us from or'ing after.
@@ -2157,8 +2141,8 @@ private:
     }
 
     // CF is inverted after FCMP
-    Ref C = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_CF_RAW_LOC, true));
-    Ref Z = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_ZF_RAW_LOC, false));
+    Ref C = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_CF_RAW_LOC, true), Constant(1), Constant(0));
+    Ref Z = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_ZF_RAW_LOC, false), Constant(1), Constant(0));
 
     if (!CTX->HostFeatures.SupportsFlagM2) {
       C = _Or(OpSize::i32Bit, C, V);
@@ -2254,7 +2238,7 @@ private:
 
   std::optional<CondClassType> DecodeNZCVCondition(uint8_t OP);
   Ref SelectBit(Ref Cmp, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue);
-  Ref SelectCC0All1(uint8_t OP);
+  Ref SelectCC(uint8_t OP, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue);
 
   /**
    * @brief Flushes NZCV. Mostly vestigial.
@@ -2329,6 +2313,7 @@ private:
    * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs.
    * @{ */
   Ref LoadPFRaw(bool Mask, bool Invert);
+  Ref SelectPF(bool Invert, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue);
   Ref LoadAF();
   void FixupAF();
   void SetAFAndFixup(Ref AF);
@@ -2364,19 +2349,17 @@ private:
   void ChgStateX87_MMX() override {
     LOGMAN_THROW_A_FMT(MMXState == MMXState_X87, "Expected state to be x87");
     _StackForceSlow();
-    SetX87Top(Constant(0)); // top reset to zero
-    _StoreContext(OpSize::i8Bit, GPRClass, Constant(0xFFFFUL), offsetof(FEXCore::Core::CPUState, AbridgedFTW));
+    SetX87Top(Constant(0));                             // top reset to zero
+    StoreContext(AbridgedFTWIndex, Constant(0xFFFFUL)); // all valid
     MMXState = MMXState_MMX;
   }
 
   void ChgStateMMX_X87() override {
     LOGMAN_THROW_A_FMT(MMXState == MMXState_MMX, "Expected state to be MMX");
-    // The opcode dispatcher register cache is used for MMX, but the x87 pass register cache is used for x87, spill to
-    // context to ensure coherence.
-    FlushRegisterCache(false, true);
     // We explicitly initialize to x87 state in StartNewBlock.
     // So if we ever change this to do something else, we need to
     // make sure that we consider if we need to explicitly set it there.
+    FlushRegisterCache();
     MMXState = MMXState_X87;
   }
 
@@ -2394,11 +2377,6 @@ private:
   bool Multiblock {};
   bool Is64BitMode {};
   uint64_t Entry {};
-
-  // Set if mono hacks are enabled and the current block is the mono callsite backpatcher, in which case the
-  // XCHG ops that would patch code are replaced with a hook that performs the write and manually invalidates
-  // the target address.
-  bool IsMonoBackpatcherBlock {false};
   IROp_IRHeader* CurrentHeader {};
 
   [[nodiscard]]
@@ -2568,7 +2546,7 @@ private:
     }
 
     ArithRef Presub(uint64_t K) {
-      return IsConstant ? ArithRef(E, K - C) : ArithRef(E, E->Sub(OpSize::i64Bit, E->Constant(K), R));
+      return IsConstant ? ArithRef(E, K - C) : ArithRef(E, E->_Sub(OpSize::i64Bit, E->Constant(K), R));
     }
 
     ArithRef Lshl(uint64_t Shift) {
@@ -2660,6 +2638,8 @@ private:
     return ArithRef(this, K);
   }
 
+  void InstallHostSpecificOpcodeHandlers();
+
   ///< Segment telemetry tracking
   uint32_t SegmentsNeedReadCheck {~0U};
   void CheckLegacySegmentWrite(Ref NewNode, uint32_t SegmentReg);
@@ -2673,14 +2653,16 @@ constexpr inline void InstallToTable(auto& FinalTable, const auto& LocalTable) {
     for (uint8_t i = 0; i < Op.Count; ++i) {
       auto& TableOp = FinalTable[OpNum + i];
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-      if (TableOp.OpcodeDispatcher.OpDispatch) {
+      if (TableOp.OpcodeDispatcher) {
         ERROR_AND_DIE_FMT("Duplicate Entry {}", TableOp.Name);
       }
 #endif
 
-      TableOp.OpcodeDispatcher.OpDispatch = Dispatcher;
+      TableOp.OpcodeDispatcher = Dispatcher;
     }
   }
 }
 
+void InstallOpcodeHandlers(Context::OperatingMode Mode);
+
 } // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp

@@ -21,6 +21,466 @@ class OrderedNode;
 
 #define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
 
+void OpDispatchBuilder::InstallAVX128Handlers() {
+#define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
+  static constexpr DispatchTableEntry AVX128Table[] = {
+    {OPD(1, 0b00, 0x10), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b01, 0x10), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b10, 0x10), 1, &OpDispatchBuilder::AVX128_VMOVSS},
+    {OPD(1, 0b11, 0x10), 1, &OpDispatchBuilder::AVX128_VMOVSD},
+    {OPD(1, 0b00, 0x11), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b01, 0x11), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b10, 0x11), 1, &OpDispatchBuilder::AVX128_VMOVSS},
+    {OPD(1, 0b11, 0x11), 1, &OpDispatchBuilder::AVX128_VMOVSD},
+
+    {OPD(1, 0b00, 0x12), 1, &OpDispatchBuilder::AVX128_VMOVLP},
+    {OPD(1, 0b01, 0x12), 1, &OpDispatchBuilder::AVX128_VMOVLP},
+    {OPD(1, 0b10, 0x12), 1, &OpDispatchBuilder::AVX128_VMOVSLDUP},
+    {OPD(1, 0b11, 0x12), 1, &OpDispatchBuilder::AVX128_VMOVDDUP},
+    {OPD(1, 0b00, 0x13), 1, &OpDispatchBuilder::AVX128_VMOVLP},
+    {OPD(1, 0b01, 0x13), 1, &OpDispatchBuilder::AVX128_VMOVLP},
+
+    {OPD(1, 0b00, 0x14), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x14), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x15), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x15), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x16), 1, &OpDispatchBuilder::AVX128_VMOVHP},
+    {OPD(1, 0b01, 0x16), 1, &OpDispatchBuilder::AVX128_VMOVHP},
+    {OPD(1, 0b10, 0x16), 1, &OpDispatchBuilder::AVX128_VMOVSHDUP},
+    {OPD(1, 0b00, 0x17), 1, &OpDispatchBuilder::AVX128_VMOVHP},
+    {OPD(1, 0b01, 0x17), 1, &OpDispatchBuilder::AVX128_VMOVHP},
+
+    {OPD(1, 0b00, 0x28), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b01, 0x28), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b01, 0x29), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+
+    {OPD(1, 0b10, 0x2A), 1, &OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR<OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x2A), 1, &OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR<OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
+    {OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
+
+    {OPD(1, 0b10, 0x2C), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<OpSize::i32Bit, false>},
+    {OPD(1, 0b11, 0x2C), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<OpSize::i64Bit, false>},
+
+    {OPD(1, 0b10, 0x2D), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<OpSize::i32Bit, true>},
+    {OPD(1, 0b11, 0x2D), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<OpSize::i64Bit, true>},
+
+    {OPD(1, 0b00, 0x2E), 1, &OpDispatchBuilder::AVX128_UCOMISx<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x2E), 1, &OpDispatchBuilder::AVX128_UCOMISx<OpSize::i64Bit>},
+    {OPD(1, 0b00, 0x2F), 1, &OpDispatchBuilder::AVX128_UCOMISx<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x2F), 1, &OpDispatchBuilder::AVX128_UCOMISx<OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x50), 1, &OpDispatchBuilder::AVX128_MOVMSK<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x50), 1, &OpDispatchBuilder::AVX128_MOVMSK<OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x51), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VFSQRT, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x51), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VFSQRT, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x51), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFSQRTSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x51), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFSQRTSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x52), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VFRSQRT, OpSize::i32Bit>},
+    {OPD(1, 0b10, 0x52), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFRSQRTSCALARINSERT, OpSize::i32Bit>},
+
+    {OPD(1, 0b00, 0x53), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VFRECP, OpSize::i32Bit>},
+    {OPD(1, 0b10, 0x53), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFRECPSCALARINSERT, OpSize::i32Bit>},
+
+    {OPD(1, 0b00, 0x54), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VAND, OpSize::i128Bit>},
+    {OPD(1, 0b01, 0x54), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VAND, OpSize::i128Bit>},
+
+    {OPD(1, 0b00, 0x55), 1, &OpDispatchBuilder::AVX128_VANDN},
+    {OPD(1, 0b01, 0x55), 1, &OpDispatchBuilder::AVX128_VANDN},
+
+    {OPD(1, 0b00, 0x56), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VOR, OpSize::i128Bit>},
+    {OPD(1, 0b01, 0x56), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VOR, OpSize::i128Bit>},
+
+    {OPD(1, 0b00, 0x57), 1, &OpDispatchBuilder::AVX128_VectorXOR},
+    {OPD(1, 0b01, 0x57), 1, &OpDispatchBuilder::AVX128_VectorXOR},
+
+    {OPD(1, 0b00, 0x58), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFADD, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x58), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFADD, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x58), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFADDSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x58), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFADDSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x59), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMUL, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x59), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMUL, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x59), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMULSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x59), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMULSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x5A), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float<OpSize::i64Bit, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x5A), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x5A), 1, &OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float<OpSize::i64Bit, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x5A), 1, &OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float<OpSize::i32Bit, false>},
+    {OPD(1, 0b01, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int<OpSize::i32Bit, true>},
+    {OPD(1, 0b10, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int<OpSize::i32Bit, false>},
+
+    {OPD(1, 0b00, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFSUB, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFSUB, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFSUBSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFSUBSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x5D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMIN, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x5D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMIN, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x5D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMINSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x5D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMINSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x5E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFDIV, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x5E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFDIV, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x5E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFDIVSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x5E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFDIVSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMAX, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x5F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFMAX, OpSize::i64Bit>},
+    {OPD(1, 0b10, 0x5F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMAXSCALARINSERT, OpSize::i32Bit>},
+    {OPD(1, 0b11, 0x5F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorScalarInsertALU, IR::OP_VFMAXSCALARINSERT, OpSize::i64Bit>},
+
+    {OPD(1, 0b01, 0x60), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i8Bit>},
+    {OPD(1, 0b01, 0x61), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x62), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x63), 1, &OpDispatchBuilder::AVX128_VPACKSS<OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPGT, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPGT, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x66), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPGT, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x67), 1, &OpDispatchBuilder::AVX128_VPACKUS<OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x68), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i8Bit>},
+    {OPD(1, 0b01, 0x69), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x6A), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x6B), 1, &OpDispatchBuilder::AVX128_VPACKSS<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x6C), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<OpSize::i64Bit>},
+    {OPD(1, 0b01, 0x6D), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<OpSize::i64Bit>},
+    {OPD(1, 0b01, 0x6E), 1, &OpDispatchBuilder::AVX128_MOVBetweenGPR_FPR},
+
+    {OPD(1, 0b01, 0x6F), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+
+    {OPD(1, 0b01, 0x70), 1, &OpDispatchBuilder::AVX128_VPERMILImm<OpSize::i32Bit>},
+    {OPD(1, 0b10, 0x70), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VPSHUFW, false>},
+    {OPD(1, 0b11, 0x70), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VPSHUFW, true>},
+
+    {OPD(1, 0b01, 0x74), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPEQ, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0x75), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPEQ, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0x76), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPEQ, OpSize::i32Bit>},
+
+    {OPD(1, 0b00, 0x77), 1, &OpDispatchBuilder::AVX128_VZERO},
+
+    {OPD(1, 0b01, 0x7C), 1, &OpDispatchBuilder::AVX128_VHADDP<IR::OP_VFADDP, OpSize::i64Bit>},
+    {OPD(1, 0b11, 0x7C), 1, &OpDispatchBuilder::AVX128_VHADDP<IR::OP_VFADDP, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0x7D), 1, &OpDispatchBuilder::AVX128_VHSUBP<OpSize::i64Bit>},
+    {OPD(1, 0b11, 0x7D), 1, &OpDispatchBuilder::AVX128_VHSUBP<OpSize::i32Bit>},
+
+    {OPD(1, 0b01, 0x7E), 1, &OpDispatchBuilder::AVX128_MOVBetweenGPR_FPR},
+    {OPD(1, 0b10, 0x7E), 1, &OpDispatchBuilder::AVX128_MOVQ},
+
+    {OPD(1, 0b01, 0x7F), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+    {OPD(1, 0b10, 0x7F), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
+
+    {OPD(1, 0b00, 0xC2), 1, &OpDispatchBuilder::AVX128_VFCMP<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0xC2), 1, &OpDispatchBuilder::AVX128_VFCMP<OpSize::i64Bit>},
+    {OPD(1, 0b10, 0xC2), 1, &OpDispatchBuilder::AVX128_InsertScalarFCMP<OpSize::i32Bit>},
+    {OPD(1, 0b11, 0xC2), 1, &OpDispatchBuilder::AVX128_InsertScalarFCMP<OpSize::i64Bit>},
+
+    {OPD(1, 0b01, 0xC4), 1, &OpDispatchBuilder::AVX128_VPINSRW},
+    {OPD(1, 0b01, 0xC5), 1, &OpDispatchBuilder::AVX128_PExtr<OpSize::i16Bit>},
+
+    {OPD(1, 0b00, 0xC6), 1, &OpDispatchBuilder::AVX128_VSHUF<OpSize::i32Bit>},
+    {OPD(1, 0b01, 0xC6), 1, &OpDispatchBuilder::AVX128_VSHUF<OpSize::i64Bit>},
+
+    {OPD(1, 0b01, 0xD0), 1, &OpDispatchBuilder::AVX128_VADDSUBP<OpSize::i64Bit>},
+    {OPD(1, 0b11, 0xD0), 1, &OpDispatchBuilder::AVX128_VADDSUBP<OpSize::i32Bit>},
+
+    {OPD(1, 0b01, 0xD1), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i16Bit, IROps::OP_VUSHRSWIDE>}, // VPSRL
+    {OPD(1, 0b01, 0xD2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i32Bit, IROps::OP_VUSHRSWIDE>}, // VPSRL
+    {OPD(1, 0b01, 0xD3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i64Bit, IROps::OP_VUSHRSWIDE>}, // VPSRL
+    {OPD(1, 0b01, 0xD4), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VADD, OpSize::i64Bit>},
+    {OPD(1, 0b01, 0xD5), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VMUL, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xD6), 1, &OpDispatchBuilder::AVX128_MOVQ},
+    {OPD(1, 0b01, 0xD7), 1, &OpDispatchBuilder::AVX128_MOVMSKB},
+
+    {OPD(1, 0b01, 0xD8), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUQSUB, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xD9), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUQSUB, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xDA), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMIN, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xDB), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VAND, OpSize::i128Bit>},
+    {OPD(1, 0b01, 0xDC), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUQADD, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xDD), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUQADD, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xDE), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMAX, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VANDN},
+
+    {OPD(1, 0b01, 0xE0), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VURAVG, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xE1), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i16Bit, IROps::OP_VSSHRSWIDE>}, // VPSRA
+    {OPD(1, 0b01, 0xE2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i32Bit, IROps::OP_VSSHRSWIDE>}, // VPSRA
+    {OPD(1, 0b01, 0xE3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VURAVG, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xE4), 1, &OpDispatchBuilder::AVX128_VPMULHW<false>},
+    {OPD(1, 0b01, 0xE5), 1, &OpDispatchBuilder::AVX128_VPMULHW<true>},
+
+    {OPD(1, 0b01, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int<OpSize::i64Bit, false>},
+    {OPD(1, 0b10, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float<OpSize::i32Bit, true>},
+    {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int<OpSize::i64Bit, true>},
+
+    {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
+
+    {OPD(1, 0b01, 0xE8), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSQSUB, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xE9), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSQSUB, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xEA), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMIN, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VOR, OpSize::i128Bit>},
+    {OPD(1, 0b01, 0xEC), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSQADD, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xED), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSQADD, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xEE), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMAX, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xEF), 1, &OpDispatchBuilder::AVX128_VectorXOR},
+
+    {OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::AVX128_MOVVectorUnaligned},
+    {OPD(1, 0b01, 0xF1), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i16Bit, IROps::OP_VUSHLSWIDE>}, // VPSLL
+    {OPD(1, 0b01, 0xF2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i32Bit, IROps::OP_VUSHLSWIDE>}, // VPSLL
+    {OPD(1, 0b01, 0xF3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftWideImpl, OpSize::i64Bit, IROps::OP_VUSHLSWIDE>}, // VPSLL
+    {OPD(1, 0b01, 0xF4), 1, &OpDispatchBuilder::AVX128_VPMULL<OpSize::i32Bit, false>},
+    {OPD(1, 0b01, 0xF5), 1, &OpDispatchBuilder::AVX128_VPMADDWD},
+    {OPD(1, 0b01, 0xF6), 1, &OpDispatchBuilder::AVX128_VPSADBW},
+    {OPD(1, 0b01, 0xF7), 1, &OpDispatchBuilder::AVX128_MASKMOV},
+
+    {OPD(1, 0b01, 0xF8), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSUB, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xF9), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSUB, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xFA), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSUB, OpSize::i32Bit>},
+    {OPD(1, 0b01, 0xFB), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSUB, OpSize::i64Bit>},
+    {OPD(1, 0b01, 0xFC), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VADD, OpSize::i8Bit>},
+    {OPD(1, 0b01, 0xFD), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VADD, OpSize::i16Bit>},
+    {OPD(1, 0b01, 0xFE), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VADD, OpSize::i32Bit>},
+
+    {OPD(2, 0b01, 0x00), 1, &OpDispatchBuilder::AVX128_VPSHUFB},
+    {OPD(2, 0b01, 0x01), 1, &OpDispatchBuilder::AVX128_VHADDP<IR::OP_VADDP, OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x02), 1, &OpDispatchBuilder::AVX128_VHADDP<IR::OP_VADDP, OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x03), 1, &OpDispatchBuilder::AVX128_VPHADDSW},
+    {OPD(2, 0b01, 0x04), 1, &OpDispatchBuilder::AVX128_VPMADDUBSW},
+
+    {OPD(2, 0b01, 0x05), 1, &OpDispatchBuilder::AVX128_VPHSUB<OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x06), 1, &OpDispatchBuilder::AVX128_VPHSUB<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x07), 1, &OpDispatchBuilder::AVX128_VPHSUBSW},
+
+    {OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::AVX128_VPSIGN<OpSize::i8Bit>},
+    {OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::AVX128_VPSIGN<OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::AVX128_VPSIGN<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x0B), 1, &OpDispatchBuilder::AVX128_VPMULHRSW},
+    {OPD(2, 0b01, 0x0C), 1, &OpDispatchBuilder::AVX128_VPERMILReg<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x0D), 1, &OpDispatchBuilder::AVX128_VPERMILReg<OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x0E), 1, &OpDispatchBuilder::AVX128_VTESTP<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x0F), 1, &OpDispatchBuilder::AVX128_VTESTP<OpSize::i64Bit>},
+
+
+    {OPD(2, 0b01, 0x13), 1, &OpDispatchBuilder::AVX128_VCVTPH2PS},
+    {OPD(2, 0b01, 0x16), 1, &OpDispatchBuilder::AVX128_VPERMD},
+    {OPD(2, 0b01, 0x17), 1, &OpDispatchBuilder::AVX128_PTest},
+    {OPD(2, 0b01, 0x18), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x19), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x1A), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i128Bit>},
+    {OPD(2, 0b01, 0x1C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VABS, OpSize::i8Bit>},
+    {OPD(2, 0b01, 0x1D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VABS, OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x1E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorUnary, IR::OP_VABS, OpSize::i32Bit>},
+
+    {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i16Bit, true>},
+    {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i32Bit, true>},
+    {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i64Bit, true>},
+    {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i16Bit, OpSize::i32Bit, true>},
+    {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i16Bit, OpSize::i64Bit, true>},
+    {OPD(2, 0b01, 0x25), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i32Bit, OpSize::i64Bit, true>},
+
+    {OPD(2, 0b01, 0x28), 1, &OpDispatchBuilder::AVX128_VPMULL<OpSize::i32Bit, true>},
+    {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPEQ, OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
+    {OPD(2, 0b01, 0x2B), 1, &OpDispatchBuilder::AVX128_VPACKUS<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x2C), 1, &OpDispatchBuilder::AVX128_VMASKMOV<OpSize::i32Bit, false>},
+    {OPD(2, 0b01, 0x2D), 1, &OpDispatchBuilder::AVX128_VMASKMOV<OpSize::i64Bit, false>},
+    {OPD(2, 0b01, 0x2E), 1, &OpDispatchBuilder::AVX128_VMASKMOV<OpSize::i32Bit, true>},
+    {OPD(2, 0b01, 0x2F), 1, &OpDispatchBuilder::AVX128_VMASKMOV<OpSize::i64Bit, true>},
+
+    {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i16Bit, false>},
+    {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i32Bit, false>},
+    {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i8Bit, OpSize::i64Bit, false>},
+    {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i16Bit, OpSize::i32Bit, false>},
+    {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i16Bit, OpSize::i64Bit, false>},
+    {OPD(2, 0b01, 0x35), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ExtendVectorElements, OpSize::i32Bit, OpSize::i64Bit, false>},
+    {OPD(2, 0b01, 0x36), 1, &OpDispatchBuilder::AVX128_VPERMD},
+
+    {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VCMPGT, OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMIN, OpSize::i8Bit>},
+    {OPD(2, 0b01, 0x39), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMIN, OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x3A), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMIN, OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x3B), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMIN, OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x3C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMAX, OpSize::i8Bit>},
+    {OPD(2, 0b01, 0x3D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VSMAX, OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x3E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMAX, OpSize::i16Bit>},
+    {OPD(2, 0b01, 0x3F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VUMAX, OpSize::i32Bit>},
+
+    {OPD(2, 0b01, 0x40), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VMUL, OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x41), 1, &OpDispatchBuilder::AVX128_PHMINPOSUW},
+    {OPD(2, 0b01, 0x45), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VariableShiftImpl, IROps::OP_VUSHR>}, // VPSRLV
+    {OPD(2, 0b01, 0x46), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VariableShiftImpl, IROps::OP_VSSHR>}, // VPSRAVD
+    {OPD(2, 0b01, 0x47), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VariableShiftImpl, IROps::OP_VUSHL>}, // VPSLLV
+
+    {OPD(2, 0b01, 0x58), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x59), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x5A), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i128Bit>},
+
+    {OPD(2, 0b01, 0x78), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i8Bit>},
+    {OPD(2, 0b01, 0x79), 1, &OpDispatchBuilder::AVX128_VBROADCAST<OpSize::i16Bit>},
+
+    {OPD(2, 0b01, 0x8C), 1, &OpDispatchBuilder::AVX128_VPMASKMOV<false>},
+    {OPD(2, 0b01, 0x8E), 1, &OpDispatchBuilder::AVX128_VPMASKMOV<true>},
+
+    {OPD(2, 0b01, 0x90), 1, &OpDispatchBuilder::AVX128_VPGATHER<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x91), 1, &OpDispatchBuilder::AVX128_VPGATHER<OpSize::i64Bit>},
+    {OPD(2, 0b01, 0x92), 1, &OpDispatchBuilder::AVX128_VPGATHER<OpSize::i32Bit>},
+    {OPD(2, 0b01, 0x93), 1, &OpDispatchBuilder::AVX128_VPGATHER<OpSize::i64Bit>},
+
+    {OPD(2, 0b01, 0x96), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, true, 1, 3, 2>},  // VFMADDSUB
+    {OPD(2, 0b01, 0x97), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, false, 1, 3, 2>}, // VFMSUBADD
+
+    {OPD(2, 0b01, 0x98), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLA, 1, 3, 2>}, // VFMADD
+    {OPD(2, 0b01, 0x99), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLASCALARINSERT, 1, 3, 2>}, // VFMADD
+    {OPD(2, 0b01, 0x9A), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLS, 1, 3, 2>}, // VFMSUB
+    {OPD(2, 0b01, 0x9B), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLSSCALARINSERT, 1, 3, 2>}, // VFMSUB
+    {OPD(2, 0b01, 0x9C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLA, 1, 3, 2>}, // VFNMADD
+    {OPD(2, 0b01, 0x9D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLASCALARINSERT, 1, 3, 2>}, // VFNMADD
+    {OPD(2, 0b01, 0x9E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLS, 1, 3, 2>}, // VFNMSUB
+    {OPD(2, 0b01, 0x9F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLSSCALARINSERT, 1, 3, 2>}, // VFNMSUB
+
+    {OPD(2, 0b01, 0xA8), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLA, 2, 1, 3>}, // VFMADD
+    {OPD(2, 0b01, 0xA9), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLASCALARINSERT, 2, 1, 3>}, // VFMADD
+    {OPD(2, 0b01, 0xAA), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLS, 2, 1, 3>}, // VFMSUB
+    {OPD(2, 0b01, 0xAB), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLSSCALARINSERT, 2, 1, 3>}, // VFMSUB
+    {OPD(2, 0b01, 0xAC), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLA, 2, 1, 3>}, // VFNMADD
+    {OPD(2, 0b01, 0xAD), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLASCALARINSERT, 2, 1, 3>}, // VFNMADD
+    {OPD(2, 0b01, 0xAE), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLS, 2, 1, 3>}, // VFNMSUB
+    {OPD(2, 0b01, 0xAF), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLSSCALARINSERT, 2, 1, 3>}, // VFNMSUB
+
+    {OPD(2, 0b01, 0xB8), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLA, 2, 3, 1>}, // VFMADD
+    {OPD(2, 0b01, 0xB9), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLASCALARINSERT, 2, 3, 1>}, // VFMADD
+    {OPD(2, 0b01, 0xBA), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFMLS, 2, 3, 1>}, // VFMSUB
+    {OPD(2, 0b01, 0xBB), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFMLSSCALARINSERT, 2, 3, 1>}, // VFMSUB
+    {OPD(2, 0b01, 0xBC), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLA, 2, 3, 1>}, // VFNMADD
+    {OPD(2, 0b01, 0xBD), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLASCALARINSERT, 2, 3, 1>}, // VFNMADD
+    {OPD(2, 0b01, 0xBE), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAImpl, IR::OP_VFNMLS, 2, 3, 1>}, // VFNMSUB
+    {OPD(2, 0b01, 0xBF), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAScalarImpl, IR::OP_VFNMLSSCALARINSERT, 2, 3, 1>}, // VFNMSUB
+
+    {OPD(2, 0b01, 0xA6), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, true, 2, 1, 3>},  // VFMADDSUB
+    {OPD(2, 0b01, 0xA7), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, false, 2, 1, 3>}, // VFMSUBADD
+
+    {OPD(2, 0b01, 0xB6), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, true, 2, 3, 1>},  // VFMADDSUB
+    {OPD(2, 0b01, 0xB7), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VFMAddSubImpl, false, 2, 3, 1>}, // VFMSUBADD
+
+    {OPD(2, 0b01, 0xDB), 1, &OpDispatchBuilder::AVX128_VAESImc},
+    {OPD(2, 0b01, 0xDC), 1, &OpDispatchBuilder::AVX128_VAESEnc},
+    {OPD(2, 0b01, 0xDD), 1, &OpDispatchBuilder::AVX128_VAESEncLast},
+    {OPD(2, 0b01, 0xDE), 1, &OpDispatchBuilder::AVX128_VAESDec},
+    {OPD(2, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VAESDecLast},
+
+    {OPD(3, 0b01, 0x00), 1, &OpDispatchBuilder::AVX128_VPERMQ},
+    {OPD(3, 0b01, 0x01), 1, &OpDispatchBuilder::AVX128_VPERMQ},
+    {OPD(3, 0b01, 0x02), 1, &OpDispatchBuilder::AVX128_VBLEND<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x04), 1, &OpDispatchBuilder::AVX128_VPERMILImm<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x05), 1, &OpDispatchBuilder::AVX128_VPERMILImm<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x06), 1, &OpDispatchBuilder::AVX128_VPERM2},
+    {OPD(3, 0b01, 0x08), 1, &OpDispatchBuilder::AVX128_VectorRound<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x09), 1, &OpDispatchBuilder::AVX128_VectorRound<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x0A), 1, &OpDispatchBuilder::AVX128_InsertScalarRound<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x0B), 1, &OpDispatchBuilder::AVX128_InsertScalarRound<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x0C), 1, &OpDispatchBuilder::AVX128_VBLEND<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x0D), 1, &OpDispatchBuilder::AVX128_VBLEND<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x0E), 1, &OpDispatchBuilder::AVX128_VBLEND<OpSize::i16Bit>},
+    {OPD(3, 0b01, 0x0F), 1, &OpDispatchBuilder::AVX128_VPALIGNR},
+
+    {OPD(3, 0b01, 0x14), 1, &OpDispatchBuilder::AVX128_PExtr<OpSize::i8Bit>},
+    {OPD(3, 0b01, 0x15), 1, &OpDispatchBuilder::AVX128_PExtr<OpSize::i16Bit>},
+    {OPD(3, 0b01, 0x16), 1, &OpDispatchBuilder::AVX128_PExtr<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x17), 1, &OpDispatchBuilder::AVX128_PExtr<OpSize::i32Bit>},
+
+    {OPD(3, 0b01, 0x18), 1, &OpDispatchBuilder::AVX128_VINSERT},
+    {OPD(3, 0b01, 0x19), 1, &OpDispatchBuilder::AVX128_VEXTRACT128},
+    {OPD(3, 0b01, 0x1D), 1, &OpDispatchBuilder::AVX128_VCVTPS2PH},
+    {OPD(3, 0b01, 0x20), 1, &OpDispatchBuilder::AVX128_VPINSRB},
+    {OPD(3, 0b01, 0x21), 1, &OpDispatchBuilder::AVX128_VINSERTPS},
+    {OPD(3, 0b01, 0x22), 1, &OpDispatchBuilder::AVX128_VPINSRDQ},
+
+    {OPD(3, 0b01, 0x38), 1, &OpDispatchBuilder::AVX128_VINSERT},
+    {OPD(3, 0b01, 0x39), 1, &OpDispatchBuilder::AVX128_VEXTRACT128},
+
+    {OPD(3, 0b01, 0x40), 1, &OpDispatchBuilder::AVX128_VDPP<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x41), 1, &OpDispatchBuilder::AVX128_VDPP<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x42), 1, &OpDispatchBuilder::AVX128_VMPSADBW},
+
+    {OPD(3, 0b01, 0x46), 1, &OpDispatchBuilder::AVX128_VPERM2},
+
+    {OPD(3, 0b01, 0x4A), 1, &OpDispatchBuilder::AVX128_VectorVariableBlend<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x4B), 1, &OpDispatchBuilder::AVX128_VectorVariableBlend<OpSize::i64Bit>},
+    {OPD(3, 0b01, 0x4C), 1, &OpDispatchBuilder::AVX128_VectorVariableBlend<OpSize::i8Bit>},
+
+    {OPD(3, 0b01, 0x60), 1, &OpDispatchBuilder::AVX128_VPCMPESTRM},
+    {OPD(3, 0b01, 0x61), 1, &OpDispatchBuilder::AVX128_VPCMPESTRI},
+    {OPD(3, 0b01, 0x62), 1, &OpDispatchBuilder::AVX128_VPCMPISTRM},
+    {OPD(3, 0b01, 0x63), 1, &OpDispatchBuilder::AVX128_VPCMPISTRI},
+
+    {OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VAESKeyGenAssist},
+  };
+#undef OPD
+
+#define OPD(group, pp, opcode) (((group - X86Tables::TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
+  static constexpr DispatchTableEntry VEX128TableGroupOps[] {
+    // VPSRLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b010), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VUSHRI>},
+    // VPSLLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b110), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VSHLI>},
+    // VPSRAI
+    {OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b100), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VSSHRI>},
+
+    // VPSRLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b010), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VUSHRI>},
+    // VPSLLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b110), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VSHLI>},
+    // VPSRAI
+    {OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b100), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VSSHRI>},
+
+    // VPSRLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b010), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i64Bit, IROps::OP_VUSHRI>},
+    // VPSRLDQ
+    {OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b011), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ShiftDoubleImm, ShiftDirection::RIGHT>},
+    // VPSLLI
+    {OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b110), 1,
+     &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i64Bit, IROps::OP_VSHLI>},
+    // VPSLLDQ
+    {OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b111), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ShiftDoubleImm, ShiftDirection::LEFT>},
+
+    ///< Use the regular implementation. It just happens to be in the VEX table.
+    {OPD(X86Tables::TYPE_VEX_GROUP_15, 0, 0b010), 1, &OpDispatchBuilder::LDMXCSR},
+    {OPD(X86Tables::TYPE_VEX_GROUP_15, 0, 0b011), 1, &OpDispatchBuilder::STMXCSR},
+  };
+#undef OPD
+
+#define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
+  constexpr DispatchTableEntry VEX128_PCLMUL[] = {
+    {OPD(3, 0b01, 0x44), 1, &OpDispatchBuilder::AVX128_VPCLMULQDQ},
+  };
+#undef OPD
+
+  InstallToTable(FEXCore::X86Tables::VEXTableOps, AVX128Table);
+  InstallToTable(FEXCore::X86Tables::VEXTableGroupOps, VEX128TableGroupOps);
+  if (CTX->HostFeatures.SupportsPMULL_128Bit) {
+    InstallToTable(FEXCore::X86Tables::VEXTableOps, VEX128_PCLMUL);
+  }
+
+  SaveAVXStateFunc = &OpDispatchBuilder::AVX128_SaveAVXState;
+  RestoreAVXStateFunc = &OpDispatchBuilder::AVX128_RestoreAVXState;
+  DefaultAVXStateFunc = &OpDispatchBuilder::AVX128_DefaultAVXState;
+}
+
 OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_LoadSource_WithOpSize(
   const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags, bool NeedsHigh, MemoryAccessType AccessType) {
 
@@ -41,7 +501,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_LoadSource_WithOpSize(
     HighA.Offset += 16;
 
     if (Operand.IsSIB()) {
-      const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
+      [[maybe_unused]] const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
       LOGMAN_THROW_A_FMT(!IsVSIB, "VSIB uses LoadVSIB instead");
     }
 
@@ -55,7 +515,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_LoadSource_WithOpSize(
 
 OpDispatchBuilder::RefVSIB
 OpDispatchBuilder::AVX128_LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags, bool NeedsHigh) {
-  const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
+  [[maybe_unused]] const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
   LOGMAN_THROW_A_FMT(Operand.IsSIB() && IsVSIB, "Trying to load VSIB for something that isn't the correct type!");
 
   // VSIB is a very special case which has a ton of encoded data.
@@ -494,7 +954,8 @@ void OpDispatchBuilder::AVX128_VMOVSHDUP(OpcodeArgs) {
                          [this](IR::OpSize ElementSize, Ref Src) { return _VTrn2(OpSize::i128Bit, ElementSize, Src, Src); });
 }
 
-void OpDispatchBuilder::AVX128_VBROADCAST(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VBROADCAST(OpcodeArgs) {
   const auto DstSize = GetDstSize(Op);
   const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
   RefPair Src {};
@@ -520,12 +981,14 @@ void OpDispatchBuilder::AVX128_VBROADCAST(OpcodeArgs, IR::OpSize ElementSize) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Src);
 }
 
-void OpDispatchBuilder::AVX128_VPUNPCKL(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPUNPCKL(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize,
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return _VZip(OpSize::i128Bit, _ElementSize, Src1, Src2); });
 }
 
-void OpDispatchBuilder::AVX128_VPUNPCKH(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPUNPCKH(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize,
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return _VZip2(OpSize::i128Bit, _ElementSize, Src1, Src2); });
 }
@@ -548,7 +1011,8 @@ void OpDispatchBuilder::AVX128_MOVVectorUnaligned(OpcodeArgs) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Src);
 }
 
-void OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR(OpcodeArgs, IR::OpSize DstElementSize) {
+template<IR::OpSize DstElementSize>
+void OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   const auto DstSize = OpSizeFromDst(Op);
 
@@ -569,19 +1033,20 @@ void OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR(OpcodeArgs, IR::OpSize DstEle
   } else {
     // In the case of cvtsi2s{s,d} where the source and destination are the same size,
     // then it is more optimal to load in to the FPR register directly and convert there.
-    auto Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
+    auto Src2 = AVX128_LoadSource_WithOpSize(Op, Op->Src[1], Op->Flags, false);
     // Always signed
-    Result.Low = _VSToFVectorInsert(DstSize, DstElementSize, DstElementSize, Src1.Low, Src2, false, false);
+    Result.Low = _VSToFVectorInsert(DstSize, DstElementSize, DstElementSize, Src1.Low, Src2.Low, false, false);
   }
 
-  const auto Is128Bit = DstSize == OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = DstSize == OpSize::i128Bit;
   LOGMAN_THROW_A_FMT(Is128Bit, "Programming Error: This should never occur!");
   Result.High = LoadZeroVector(OpSize::i128Bit);
 
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode) {
+template<IR::OpSize SrcElementSize, bool HostRoundingMode>
+void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs) {
   // If loading a vector, use the full size, so we don't
   // unnecessarily zero extend the vector. Otherwise, if
   // memory, then we want to load the element size exactly.
@@ -601,13 +1066,15 @@ void OpDispatchBuilder::AVX128_VANDN(OpcodeArgs) {
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return _VAndn(OpSize::i128Bit, _ElementSize, Src2, Src1); });
 }
 
-void OpDispatchBuilder::AVX128_VPACKSS(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPACKSS(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) {
     return _VSQXTNPair(OpSize::i128Bit, _ElementSize, Src1, Src2);
   });
 }
 
-void OpDispatchBuilder::AVX128_VPACKUS(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPACKUS(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) {
     return _VSQXTUNPair(OpSize::i128Bit, _ElementSize, Src1, Src2);
   });
@@ -619,12 +1086,14 @@ Ref OpDispatchBuilder::AVX128_PSIGNImpl(IR::OpSize ElementSize, Ref Src1, Ref Sr
   return _VMul(OpSize::i128Bit, ElementSize, Src1, Control);
 }
 
-void OpDispatchBuilder::AVX128_VPSIGN(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPSIGN(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize,
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return AVX128_PSIGNImpl(_ElementSize, Src1, Src2); });
 }
 
-void OpDispatchBuilder::AVX128_UCOMISx(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_UCOMISx(OpcodeArgs) {
   const auto SrcSize = Op->Src[0].IsGPR() ? GetGuestVectorLength() : ElementSize;
 
   auto Src1 = AVX128_LoadSource_WithOpSize(Op, Op->Dest, Op->Flags, false);
@@ -662,7 +1131,8 @@ void OpDispatchBuilder::AVX128_VectorScalarInsertALU(OpcodeArgs, FEXCore::IR::IR
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, RefPair {.Low = Result_Low, .High = High});
 }
 
-void OpDispatchBuilder::AVX128_VFCMP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VFCMP(OpcodeArgs) {
   const uint8_t CompType = Op->Src[2].Literal();
 
   struct {
@@ -678,7 +1148,8 @@ void OpDispatchBuilder::AVX128_VFCMP(OpcodeArgs, IR::OpSize ElementSize) {
   });
 }
 
-void OpDispatchBuilder::AVX128_InsertScalarFCMP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_InsertScalarFCMP(OpcodeArgs) {
   // We load the full vector width when dealing with a source vector,
   // so that we don't do any unnecessary zero extension to the scalar
   // element that we're going to operate on.
@@ -735,7 +1206,8 @@ void OpDispatchBuilder::AVX128_MOVBetweenGPR_FPR(OpcodeArgs) {
   }
 }
 
-void OpDispatchBuilder::AVX128_PExtr(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_PExtr(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
 
   auto Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, false);
@@ -746,7 +1218,7 @@ void OpDispatchBuilder::AVX128_PExtr(OpcodeArgs, IR::OpSize ElementSize) {
   // is the same except that REX.W or VEX.W is set to 1. Incredibly frustrating.
   // Use the destination size as the element size in this case.
   auto OverridenElementSize = ElementSize;
-  if (ElementSize == OpSize::i32Bit) {
+  if constexpr (ElementSize == OpSize::i32Bit) {
     OverridenElementSize = DstSize;
   }
 
@@ -819,7 +1291,8 @@ void OpDispatchBuilder::AVX128_ExtendVectorElements(OpcodeArgs, IR::OpSize Eleme
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_MOVMSK(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_MOVMSK(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   const auto Is128Bit = SrcSize == OpSize::i128Bit;
 
@@ -1001,7 +1474,8 @@ void OpDispatchBuilder::AVX128_VINSERTPS(OpcodeArgs) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, AVX128_Zext(Result));
 }
 
-void OpDispatchBuilder::AVX128_VPHSUB(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPHSUB(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) {
     return PHSUBOpImpl(OpSize::i128Bit, Src1, Src2, _ElementSize);
   });
@@ -1012,17 +1486,19 @@ void OpDispatchBuilder::AVX128_VPHSUBSW(OpcodeArgs) {
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return PHSUBSOpImpl(OpSize::i128Bit, Src1, Src2); });
 }
 
-void OpDispatchBuilder::AVX128_VADDSUBP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VADDSUBP(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) {
     return ADDSUBPOpImpl(OpSize::i128Bit, _ElementSize, Src1, Src2);
   });
 }
 
-void OpDispatchBuilder::AVX128_VPMULL(OpcodeArgs, IR::OpSize ElementSize, bool Signed) {
-  LOGMAN_THROW_A_FMT(ElementSize == OpSize::i32Bit, "Currently only handles 32-bit -> 64-bit");
+template<IR::OpSize ElementSize, bool Signed>
+void OpDispatchBuilder::AVX128_VPMULL(OpcodeArgs) {
+  static_assert(ElementSize == OpSize::i32Bit, "Currently only handles 32-bit -> 64-bit");
 
-  AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), ElementSize, [&](IR::OpSize _ElementSize, Ref Src1, Ref Src2) -> Ref {
-    return PMULLOpImpl(OpSize::i128Bit, _ElementSize, Signed, Src1, Src2);
+  AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) -> Ref {
+    return PMULLOpImpl(OpSize::i128Bit, ElementSize, Signed, Src1, Src2);
   });
 }
 
@@ -1031,8 +1507,9 @@ void OpDispatchBuilder::AVX128_VPMULHRSW(OpcodeArgs) {
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) -> Ref { return PMULHRSWOpImpl(OpSize::i128Bit, Src1, Src2); });
 }
 
-void OpDispatchBuilder::AVX128_VPMULHW(OpcodeArgs, bool Signed) {
-  AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), OpSize::i16Bit, [&](IR::OpSize _ElementSize, Ref Src1, Ref Src2) -> Ref {
+template<bool Signed>
+void OpDispatchBuilder::AVX128_VPMULHW(OpcodeArgs) {
+  AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), OpSize::i16Bit, [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) -> Ref {
     if (Signed) {
       return _VSMulH(OpSize::i128Bit, _ElementSize, Src1, Src2);
     } else {
@@ -1041,11 +1518,12 @@ void OpDispatchBuilder::AVX128_VPMULHW(OpcodeArgs, bool Signed) {
   });
 }
 
-void OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize) {
+template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
+void OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float(OpcodeArgs) {
   // Gotta be careful with this operation.
   // It inserts in to the lowest element, retaining the remainder of the lower 128-bits.
   // Then zero extends the top 128-bit.
-  const auto SrcSize = Op->Src[1].IsGPR() ? OpSize::i128Bit : SrcElementSize;
+  const auto SrcSize = OpSizeFromSrc(Op);
   auto Src1 = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, false);
   Ref Src2 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[1], SrcSize, Op->Flags, {.AllowUpperGarbage = true});
 
@@ -1053,7 +1531,8 @@ void OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float(OpcodeArgs, IR::O
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, AVX128_Zext(Result));
 }
 
-void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize) {
+template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
+void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   const auto DstSize = OpSizeFromDst(Op);
 
@@ -1081,11 +1560,11 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize
 
   RefPair Result {};
 
-  auto TransformLow = [&](Ref Src) -> Ref {
+  auto TransformLow = [this](Ref Src) -> Ref {
     return _Vector_FToF(OpSize::i128Bit, DstElementSize, Src, SrcElementSize);
   };
 
-  auto TransformHigh = [&](Ref Src) -> Ref {
+  auto TransformHigh = [this](Ref Src) -> Ref {
     return _VFCVTL2(OpSize::i128Bit, SrcElementSize, Src);
   };
 
@@ -1116,7 +1595,8 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs, IR::OpSize SrcElementSize, bool HostRoundingMode) {
+template<IR::OpSize SrcElementSize, bool HostRoundingMode>
+void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs) {
   const auto SrcSize = GetSrcSize(Op);
 
   const auto Is128BitSrc = SrcSize == Core::CPUState::XMM_SSE_REG_SIZE;
@@ -1144,7 +1624,8 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs, IR::OpSize Sr
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float(OpcodeArgs, IR::OpSize SrcElementSize, bool Widen) {
+template<IR::OpSize SrcElementSize, bool Widen>
+void OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float(OpcodeArgs) {
   const auto Size = OpSizeFromDst(Op);
   const auto Is128Bit = Size == OpSize::i128Bit;
 
@@ -1160,7 +1641,7 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float(OpcodeArgs, IR::OpSize Sr
     }
   }();
 
-  auto Convert = [&](Ref Src, IROps Op) -> Ref {
+  auto Convert = [this](Ref Src, IROps Op) -> Ref {
     auto ElementSize = SrcElementSize;
     if (Widen) {
       DeriveOp(Extended, Op, _VSXTL(OpSize::i128Bit, ElementSize, Src));
@@ -1285,15 +1766,17 @@ void OpDispatchBuilder::AVX128_PHMINPOSUW(OpcodeArgs) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, AVX128_Zext(Result));
 }
 
-void OpDispatchBuilder::AVX128_VectorRound(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VectorRound(OpcodeArgs) {
   const auto Size = OpSizeFromSrc(Op);
   const auto Mode = Op->Src[1].Literal();
 
   AVX128_VectorUnaryImpl(Op, Size, ElementSize,
-                         [this, Mode](IR::OpSize ElementSize, Ref Src) { return VectorRoundImpl(OpSize::i128Bit, ElementSize, Src, Mode); });
+                         [this, Mode](IR::OpSize, Ref Src) { return VectorRoundImpl(OpSize::i128Bit, ElementSize, Src, Mode); });
 }
 
-void OpDispatchBuilder::AVX128_InsertScalarRound(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_InsertScalarRound(OpcodeArgs) {
   // We load the full vector width when dealing with a source vector,
   // so that we don't do any unnecessary zero extension to the scalar
   // element that we're going to operate on.
@@ -1314,10 +1797,11 @@ void OpDispatchBuilder::AVX128_InsertScalarRound(OpcodeArgs, IR::OpSize ElementS
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, AVX128_Zext(Result));
 }
 
-void OpDispatchBuilder::AVX128_VDPP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VDPP(OpcodeArgs) {
   const uint64_t Literal = Op->Src[2].Literal();
 
-  AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this, Literal](IR::OpSize ElementSize, Ref Src1, Ref Src2) {
+  AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this, Literal](IR::OpSize, Ref Src1, Ref Src2) {
     return DPPOpImpl(OpSize::i128Bit, Src1, Src2, Literal, ElementSize);
   });
 }
@@ -1385,7 +1869,8 @@ void OpDispatchBuilder::AVX128_VPSHUFW(OpcodeArgs, bool Low) {
   });
 }
 
-void OpDispatchBuilder::AVX128_VSHUF(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VSHUF(OpcodeArgs) {
   const auto SrcSize = GetSrcSize(Op);
   const auto Is128Bit = SrcSize == Core::CPUState::XMM_SSE_REG_SIZE;
   auto Shuffle = Op->Src[2].Literal();
@@ -1399,13 +1884,14 @@ void OpDispatchBuilder::AVX128_VSHUF(OpcodeArgs, IR::OpSize ElementSize) {
   if (Is128Bit) {
     Result.High = LoadZeroVector(OpSize::i128Bit);
   } else {
-    const uint8_t ShiftAmount = ElementSize == OpSize::i32Bit ? 0 : 2;
+    constexpr uint8_t ShiftAmount = ElementSize == OpSize::i32Bit ? 0 : 2;
     Result.High = SHUFOpImpl(Op, OpSize::i128Bit, ElementSize, Src1.High, Src2.High, Shuffle >> ShiftAmount);
   }
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_VPERMILImm(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPERMILImm(OpcodeArgs) {
   const auto SrcSize = GetSrcSize(Op);
   const auto Is128Bit = SrcSize == Core::CPUState::XMM_SSE_REG_SIZE;
 
@@ -1414,7 +1900,7 @@ void OpDispatchBuilder::AVX128_VPERMILImm(OpcodeArgs, IR::OpSize ElementSize) {
 
   RefPair Result = AVX128_Zext(LoadZeroVector(OpSize::i128Bit));
 
-  if (ElementSize == OpSize::i64Bit) {
+  if constexpr (ElementSize == OpSize::i64Bit) {
     auto DoSwizzle64 = [this](Ref Src, uint8_t Selector) -> Ref {
       switch (Selector) {
       case 0b00:
@@ -1442,8 +1928,9 @@ void OpDispatchBuilder::AVX128_VPERMILImm(OpcodeArgs, IR::OpSize ElementSize) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_VHADDP(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) {
-  AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [&](IR::OpSize ElementSize, Ref Src1, Ref Src2) {
+template<IROps IROp, IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VHADDP(OpcodeArgs) {
+  AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this](IR::OpSize, Ref Src1, Ref Src2) {
     DeriveOp(Res, IROp, _VFAddP(OpSize::i128Bit, ElementSize, Src1, Src2));
     return Res;
   });
@@ -1464,7 +1951,8 @@ void OpDispatchBuilder::AVX128_VPMADDWD(OpcodeArgs) {
                           [this](IR::OpSize _ElementSize, Ref Src1, Ref Src2) { return PMADDWDOpImpl(OpSize::i128Bit, Src1, Src2); });
 }
 
-void OpDispatchBuilder::AVX128_VBLEND(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VBLEND(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   const auto Is128Bit = SrcSize == OpSize::i128Bit;
   const uint64_t Selector = Op->Src[2].Literal();
@@ -1473,7 +1961,7 @@ void OpDispatchBuilder::AVX128_VBLEND(OpcodeArgs, IR::OpSize ElementSize) {
   /// i16Bit: Reuses same bits, no shift
   /// i32Bit: Shift by 4
   /// i64Bit: Shift by 2
-  const uint64_t SelectorShift = ElementSize == OpSize::i64Bit ? 2 : ElementSize == OpSize::i32Bit ? 4 : 0;
+  constexpr uint64_t SelectorShift = ElementSize == OpSize::i64Bit ? 2 : ElementSize == OpSize::i32Bit ? 4 : 0;
 
   auto Src1 = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, !Is128Bit);
   auto Src2 = AVX128_LoadSource_WithOpSize(Op, Op->Src[1], Op->Flags, !Is128Bit);
@@ -1490,9 +1978,10 @@ void OpDispatchBuilder::AVX128_VBLEND(OpcodeArgs, IR::OpSize ElementSize) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_VHSUBP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VHSUBP(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromDst(Op), ElementSize,
-                          [&](IR::OpSize, Ref Src1, Ref Src2) { return HSUBPOpImpl(OpSize::i128Bit, ElementSize, Src1, Src2); });
+                          [this](IR::OpSize, Ref Src1, Ref Src2) { return HSUBPOpImpl(OpSize::i128Bit, ElementSize, Src1, Src2); });
 }
 
 void OpDispatchBuilder::AVX128_VPSHUFB(OpcodeArgs) {
@@ -1592,11 +2081,13 @@ void OpDispatchBuilder::AVX128_VMASKMOVImpl(OpcodeArgs, IR::OpSize ElementSize,
   }
 }
 
-void OpDispatchBuilder::AVX128_VPMASKMOV(OpcodeArgs, bool IsStore) {
+template<bool IsStore>
+void OpDispatchBuilder::AVX128_VPMASKMOV(OpcodeArgs) {
   AVX128_VMASKMOVImpl(Op, OpSizeFromSrc(Op), OpSizeFromDst(Op), IsStore, Op->Src[0], Op->Src[1]);
 }
 
-void OpDispatchBuilder::AVX128_VMASKMOV(OpcodeArgs, IR::OpSize ElementSize, bool IsStore) {
+template<IR::OpSize ElementSize, bool IsStore>
+void OpDispatchBuilder::AVX128_VMASKMOV(OpcodeArgs) {
   AVX128_VMASKMOVImpl(Op, ElementSize, OpSizeFromDst(Op), IsStore, Op->Src[0], Op->Src[1]);
 }
 
@@ -1623,7 +2114,8 @@ void OpDispatchBuilder::AVX128_MASKMOV(OpcodeArgs) {
   _StoreMem(FPRClass, Size, MemDest, XMMReg, OpSize::i8Bit);
 }
 
-void OpDispatchBuilder::AVX128_VectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VectorVariableBlend(OpcodeArgs) {
   const auto Size = OpSizeFromSrc(Op);
   const auto Is128Bit = Size == OpSize::i128Bit;
   const auto Src3Selector = Op->Src[2].Literal();
@@ -1638,7 +2130,7 @@ void OpDispatchBuilder::AVX128_VectorVariableBlend(OpcodeArgs, IR::OpSize Elemen
     Mask.High = AVX128_LoadXMMRegister(MaskRegister, true);
   }
 
-  auto Convert = [&](Ref Src1, Ref Src2, Ref Mask) {
+  auto Convert = [this](Ref Src1, Ref Src2, Ref Mask) {
     const auto ElementSizeBits = IR::OpSizeAsBits(ElementSize);
     Ref Shifted = _VSShrI(OpSize::i128Bit, ElementSize, Mask, ElementSizeBits - 1);
     return _VBSL(OpSize::i128Bit, Shifted, Src2, Src1);
@@ -1703,7 +2195,8 @@ void OpDispatchBuilder::AVX128_VPERM2(OpcodeArgs) {
   AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
 }
 
-void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs) {
   const auto Size = GetSrcSize(Op);
   const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE;
 
@@ -1719,6 +2212,8 @@ void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs, IR::OpSize ElementSize) {
   // For 256-bit, we need to split up the operation. This is nontrivial.
   // Let's go the simple route here.
   Ref ZF, CFInv;
+  Ref ZeroConst = Constant(0);
+  Ref OneConst = Constant(1);
 
   const auto ElementSizeInBits = IR::OpSizeAsBits(ElementSize);
 
@@ -1760,7 +2255,7 @@ void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs, IR::OpSize ElementSize) {
 
     // ExtGPR will either be [0, 8] or [0, 16] If 0 then set Flag.
     auto ExtGPR = _VExtractToGPR(OpSize::i128Bit, ElementSize, AddWide, 0);
-    CFInv = To01(OpSize::i64Bit, ExtGPR);
+    CFInv = _Select(IR::COND_NEQ, ExtGPR, ZeroConst, OneConst, ZeroConst);
   }
 
   // As in PTest, this sets Z appropriately while zeroing the rest of NZCV.
@@ -1799,7 +2294,10 @@ void OpDispatchBuilder::AVX128_PTest(OpcodeArgs) {
   Test1 = _VExtractToGPR(OpSize::i128Bit, OpSize::i16Bit, Test1, 0);
   Test2 = _VExtractToGPR(OpSize::i128Bit, OpSize::i16Bit, Test2, 0);
 
-  Test2 = To01(OpSize::i64Bit, Test2);
+  auto ZeroConst = Constant(0);
+  auto OneConst = Constant(1);
+
+  Test2 = _Select(FEXCore::IR::COND_NEQ, Test2, ZeroConst, OneConst, ZeroConst);
 
   // Careful, these flags are different between {V,}PTEST and VTESTP{S,D}
   // Set ZF according to Test1. SF will be zeroed since we do a 32-bit test on
@@ -1810,9 +2308,10 @@ void OpDispatchBuilder::AVX128_PTest(OpcodeArgs) {
   ZeroPF_AF();
 }
 
-void OpDispatchBuilder::AVX128_VPERMILReg(OpcodeArgs, IR::OpSize ElementSize) {
+template<IR::OpSize ElementSize>
+void OpDispatchBuilder::AVX128_VPERMILReg(OpcodeArgs) {
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), ElementSize, [this](IR::OpSize _ElementSize, Ref Src, Ref Indices) {
-    return VPERMILRegOpImpl(OpSize::i128Bit, _ElementSize, Src, Indices);
+    return VPERMILRegOpImpl(OpSize::i128Bit, ElementSize, Src, Indices);
   });
 }
 
@@ -1839,11 +2338,6 @@ void OpDispatchBuilder::AVX128_VPERMD(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AVX128_VPCLMULQDQ(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsPMULL_128Bit) {
-    UnimplementedOp(Op);
-    return;
-  }
-
   const auto Selector = static_cast<uint8_t>(Op->Src[2].Literal());
 
   AVX128_VectorBinaryImpl(Op, OpSizeFromSrc(Op), OpSize::iInvalid, [this, Selector](IR::OpSize, Ref Src1, Ref Src2) {
@@ -2024,7 +2518,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherImpl(OpSize Size, O
   ///< BaseAddr doesn't need to exist, calculate that here.
   Ref BaseAddr = VSIB.BaseAddr;
   if (BaseAddr && VSIB.Displacement) {
-    BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement);
+    BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement));
   } else if (VSIB.Displacement) {
     BaseAddr = Constant(VSIB.Displacement);
   } else if (!BaseAddr) {
@@ -2119,7 +2613,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherQPSImpl(Ref Dest, R
   ///< BaseAddr doesn't need to exist, calculate that here.
   Ref BaseAddr = VSIB.BaseAddr;
   if (BaseAddr && VSIB.Displacement) {
-    BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement);
+    BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement));
   } else if (VSIB.Displacement) {
     BaseAddr = Constant(VSIB.Displacement);
   } else if (!BaseAddr) {
@@ -2154,7 +2648,8 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherQPSImpl(Ref Dest, R
   return Result;
 }
 
-void OpDispatchBuilder::AVX128_VPGATHER(OpcodeArgs, OpSize AddrElementSize) {
+template<OpSize AddrElementSize>
+void OpDispatchBuilder::AVX128_VPGATHER(OpcodeArgs) {
 
   const auto Size = OpSizeFromDst(Op);
   const auto Is128Bit = Size == OpSize::i128Bit;

FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h

@@ -53,11 +53,10 @@ constexpr inline DispatchTableEntry OpDispatch_BaseOpTable[] = {
   {0xAA, 2, &OpDispatchBuilder::STOSOp},
   {0xAC, 2, &OpDispatchBuilder::LODSOp},
   {0xAE, 2, &OpDispatchBuilder::SCASOp},
-  {0xB0, 16, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPRImmediate>},
+  {0xB0, 16, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPROp, 0>},
   {0xC2, 2, &OpDispatchBuilder::RETOp},
   {0xC8, 1, &OpDispatchBuilder::EnterOp},
   {0xC9, 1, &OpDispatchBuilder::LEAVEOp},
-  {0xCA, 2, &OpDispatchBuilder::RETFARIndirectOp},
   {0xCC, 2, &OpDispatchBuilder::INTOp},
   {0xCF, 1, &OpDispatchBuilder::IRETOp},
   {0xD7, 2, &OpDispatchBuilder::XLATOp},
@@ -76,4 +75,33 @@ constexpr inline DispatchTableEntry OpDispatch_BaseOpTable[] = {
   {0xFA, 2, &OpDispatchBuilder::PermissionRestrictedOp},
   {0xFC, 2, &OpDispatchBuilder::FLAGControlOp},
 };
+
+constexpr inline DispatchTableEntry OpDispatch_BaseOpTable_64[] = {
+  {0x63, 1, &OpDispatchBuilder::MOVSXDOp},
+  {0xA0, 4, &OpDispatchBuilder::MOVOffsetOp},
+};
+
+constexpr inline DispatchTableEntry OpDispatch_BaseOpTable_32[] = {
+  {0x06, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
+  {0x07, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX>},
+  {0x0E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_CS_PREFIX>},
+  {0x16, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
+  {0x17, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX>},
+  {0x1E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
+  {0x1F, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX>},
+  {0x27, 1, &OpDispatchBuilder::DAAOp},
+  {0x2F, 1, &OpDispatchBuilder::DASOp},
+  {0x37, 1, &OpDispatchBuilder::AAAOp},
+  {0x3F, 1, &OpDispatchBuilder::AASOp},
+  {0x40, 8, &OpDispatchBuilder::INCOp},
+  {0x48, 8, &OpDispatchBuilder::DECOp},
+
+  {0x60, 1, &OpDispatchBuilder::PUSHAOp},
+  {0x61, 1, &OpDispatchBuilder::POPAOp},
+  {0xA0, 4, &OpDispatchBuilder::MOVOffsetOp},
+  {0xCE, 1, &OpDispatchBuilder::INTOp},
+  {0xD4, 1, &OpDispatchBuilder::AAMOp},
+  {0xD5, 1, &OpDispatchBuilder::AADOp},
+  {0xD6, 1, &OpDispatchBuilder::SALCOp},
+};
 } // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -19,10 +19,6 @@ class OrderedNode;
 #define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
 
 void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -40,10 +36,6 @@ void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHA1MSG1Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -56,10 +48,6 @@ void OpDispatchBuilder::SHA1MSG1Op(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -74,10 +62,6 @@ void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   const uint64_t Imm8 = Op->Src[1].Literal() & 0b11;
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
@@ -116,10 +100,6 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -129,10 +109,6 @@ void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -145,11 +121,17 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
   StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
 }
 
+Ref OpDispatchBuilder::BitwiseAtLeastTwo(Ref A, Ref B, Ref C) {
+  // Returns whether at least 2/3 of A/B/C is true.
+  // Expressed as (A & (B | C)) | (B & C)
+  //
+  // Equivalent to expression in SHA calculations: (A & B) ^ (A & C) ^ (B & C)
+  auto And = _And(OpSize::i32Bit, B, C);
+  auto Or = _Or(OpSize::i32Bit, B, C);
+  return _Or(OpSize::i32Bit, _And(OpSize::i32Bit, A, Or), And);
+}
+
 void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsSHA) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   // Hardcoded to XMM0
@@ -181,20 +163,12 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESImc(Src);
   StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
 }
 
 void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESEnc(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
@@ -203,7 +177,7 @@ void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
 
 void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
-  const auto Is128Bit = DstSize == OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = DstSize == OpSize::i128Bit;
 
   // TODO: Handle 256-bit VAESENC.
   LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESENC unimplemented");
@@ -216,10 +190,6 @@ void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESEncLast(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
@@ -228,7 +198,7 @@ void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
 
 void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
-  const auto Is128Bit = DstSize == OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = DstSize == OpSize::i128Bit;
 
   // TODO: Handle 256-bit VAESENCLAST.
   LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESENCLAST unimplemented");
@@ -241,10 +211,6 @@ void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESDec(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
@@ -253,7 +219,7 @@ void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
 
 void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
-  const auto Is128Bit = DstSize == OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = DstSize == OpSize::i128Bit;
 
   // TODO: Handle 256-bit VAESDEC.
   LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESDEC unimplemented");
@@ -266,10 +232,6 @@ void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESDecLast(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
@@ -278,7 +240,7 @@ void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
 
 void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
-  const auto Is128Bit = DstSize == OpSize::i128Bit;
+  [[maybe_unused]] const auto Is128Bit = DstSize == OpSize::i128Bit;
 
   // TODO: Handle 256-bit VAESDECLAST.
   LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESDECLAST unimplemented");
@@ -299,20 +261,11 @@ Ref OpDispatchBuilder::AESKeyGenAssistImpl(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsAES) {
-    UnimplementedOp(Op);
-    return;
-  }
-
   Ref Result = AESKeyGenAssistImpl(Op);
   StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
 }
 
 void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsPMULL_128Bit) {
-    UnimplementedOp(Op);
-    return;
-  }
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   const auto Selector = static_cast<uint8_t>(Op->Src[1].Literal());
@@ -322,10 +275,6 @@ void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPCLMULQDQOp(OpcodeArgs) {
-  if (!CTX->HostFeatures.SupportsPMULL_128Bit) {
-    UnimplementedOp(Op);
-    return;
-  }
   const auto DstSize = OpSizeFromDst(Op);
 
   Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);

FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp

@@ -201,7 +201,7 @@ void OpDispatchBuilder::FixupAF() {
   auto PFRaw = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
   auto AFRaw = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC);
 
-  // Again 64-bit as masking is more expensive.
+  // Again 64-bit as masking is more expensive given our ConstProp design.
   Ref XorRes = _Xor(OpSize::i64Bit, AFRaw, PFRaw);
   SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
 }
@@ -267,6 +267,8 @@ Ref OpDispatchBuilder::IncrementByCarry(OpSize OpSize, Ref Src) {
 }
 
 Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2) {
+  auto Zero = _InlineConstant(0);
+  auto One = _InlineConstant(1);
   auto OpSize = SrcSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit;
   Ref Res;
 
@@ -286,11 +288,11 @@ Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2
     Ref Src2PlusCF = IncrementByCarry(OpSize, Src2);
 
     // Need to zero-extend for the comparison.
-    Res = Add(OpSize, Src1, Src2PlusCF);
+    Res = _Add(OpSize, Src1, Src2PlusCF);
     Res = _Bfe(OpSize, IR::OpSizeAsBits(SrcSize), 0, Res);
 
     // TODO: We can fold that second Bfe in (cmp uxth).
-    auto SelectCFInv = Select01(OpSize, CondClassType {COND_UGE}, Res, Src2PlusCF);
+    auto SelectCFInv = _Select(FEXCore::IR::COND_UGE, Res, Src2PlusCF, One, Zero);
 
     SetNZ_ZeroCV(SrcSize, Res);
     SetCFInverted(SelectCFInv);
@@ -302,6 +304,8 @@ Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2
 }
 
 Ref OpDispatchBuilder::CalculateFlags_SBB(IR::OpSize SrcSize, Ref Src1, Ref Src2) {
+  auto Zero = _InlineConstant(0);
+  auto One = _InlineConstant(1);
   auto OpSize = SrcSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit;
 
   CalculateAF(Src1, Src2);
@@ -321,10 +325,10 @@ Ref OpDispatchBuilder::CalculateFlags_SBB(IR::OpSize SrcSize, Ref Src1, Ref Src2
 
     auto Src2PlusCF = IncrementByCarry(OpSize, Src2);
 
-    Res = Sub(OpSize, Src1, Src2PlusCF);
+    Res = _Sub(OpSize, Src1, Src2PlusCF);
     Res = _Bfe(OpSize, IR::OpSizeAsBits(SrcSize), 0, Res);
 
-    auto SelectCFInv = Select01(OpSize, CondClassType {COND_UGE}, Src1, Src2PlusCF);
+    auto SelectCFInv = _Select(FEXCore::IR::COND_UGE, Src1, Src2PlusCF, One, Zero);
 
     SetNZ_ZeroCV(SrcSize, Res);
     SetCFInverted(SelectCFInv);
@@ -345,10 +349,10 @@ Ref OpDispatchBuilder::CalculateFlags_SUB(IR::OpSize SrcSize, Ref Src1, Ref Src2
 
   Ref Res;
   if (SrcSize >= OpSize::i32Bit) {
-    Res = SubWithFlags(SrcSize, Src1, Src2);
+    Res = _SubWithFlags(SrcSize, Src1, Src2);
   } else {
     _SubNZCV(SrcSize, Src1, Src2);
-    Res = Sub(OpSize::i32Bit, Src1, Src2);
+    Res = _Sub(OpSize::i32Bit, Src1, Src2);
   }
 
   CalculatePF(Res);
@@ -375,10 +379,10 @@ Ref OpDispatchBuilder::CalculateFlags_ADD(IR::OpSize SrcSize, Ref Src1, Ref Src2
 
   Ref Res;
   if (SrcSize >= OpSize::i32Bit) {
-    Res = AddWithFlags(SrcSize, Src1, Src2);
+    Res = _AddWithFlags(SrcSize, Src1, Src2);
   } else {
     _AddNZCV(SrcSize, Src1, Src2);
-    Res = Add(OpSize::i32Bit, Src1, Src2);
+    Res = _Add(OpSize::i32Bit, Src1, Src2);
   }
 
   CalculatePF(Res);

FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h

@@ -6,7 +6,6 @@ namespace FEXCore::IR {
 #define OPD(prefix, opcode) (((prefix) << 8) | opcode)
 constexpr uint16_t PF_38_NONE = 0;
 constexpr uint16_t PF_38_66 = (1U << 0);
-constexpr uint16_t PF_38_F2 = (1U << 1);
 constexpr uint16_t PF_38_F3 = (1U << 2);
 
 constexpr DispatchTableEntry OpDispatch_H0F38Table[] = {
@@ -72,28 +71,9 @@ constexpr DispatchTableEntry OpDispatch_H0F38Table[] = {
   {OPD(PF_38_66, 0x40), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VMUL, OpSize::i32Bit>},
   {OPD(PF_38_66, 0x41), 1, &OpDispatchBuilder::PHMINPOSUWOp},
 
-  {OPD(PF_38_NONE, 0xC8), 1, &OpDispatchBuilder::SHA1NEXTEOp},
-  {OPD(PF_38_NONE, 0xC9), 1, &OpDispatchBuilder::SHA1MSG1Op},
-  {OPD(PF_38_NONE, 0xCA), 1, &OpDispatchBuilder::SHA1MSG2Op},
-  {OPD(PF_38_NONE, 0xCB), 1, &OpDispatchBuilder::SHA256RNDS2Op},
-  {OPD(PF_38_NONE, 0xCC), 1, &OpDispatchBuilder::SHA256MSG1Op},
-  {OPD(PF_38_NONE, 0xCD), 1, &OpDispatchBuilder::SHA256MSG2Op},
-
-  {OPD(PF_38_66, 0xDB), 1, &OpDispatchBuilder::AESImcOp},
-  {OPD(PF_38_66, 0xDC), 1, &OpDispatchBuilder::AESEncOp},
-  {OPD(PF_38_66, 0xDD), 1, &OpDispatchBuilder::AESEncLastOp},
-  {OPD(PF_38_66, 0xDE), 1, &OpDispatchBuilder::AESDecOp},
-  {OPD(PF_38_66, 0xDF), 1, &OpDispatchBuilder::AESDecLastOp},
-
   {OPD(PF_38_NONE, 0xF0), 2, &OpDispatchBuilder::MOVBEOp},
   {OPD(PF_38_66, 0xF0), 2, &OpDispatchBuilder::MOVBEOp},
 
-  {OPD(PF_38_F2, 0xF0), 1, &OpDispatchBuilder::CRC32},
-  {OPD(PF_38_F2, 0xF1), 1, &OpDispatchBuilder::CRC32},
-
-  {OPD(PF_38_66 | PF_38_F2, 0xF0), 1, &OpDispatchBuilder::CRC32},
-  {OPD(PF_38_66 | PF_38_F2, 0xF1), 1, &OpDispatchBuilder::CRC32},
-
   {OPD(PF_38_66, 0xF6), 1, &OpDispatchBuilder::ADXOp},
   {OPD(PF_38_F3, 0xF6), 1, &OpDispatchBuilder::ADXOp},
 };

FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h

@@ -29,7 +29,6 @@ constexpr auto OpDispatchTableGenH0F3A = []() consteval {
       {OPD(REX, PF_3A_66, 0x40), 1, &OpDispatchBuilder::DPPOp<OpSize::i32Bit>},
       {OPD(REX, PF_3A_66, 0x41), 1, &OpDispatchBuilder::DPPOp<OpSize::i64Bit>},
       {OPD(REX, PF_3A_66, 0x42), 1, &OpDispatchBuilder::MPSADBWOp},
-      {OPD(REX, PF_3A_66, 0x44), 1, &OpDispatchBuilder::PCLMULQDQOp},
 
       {OPD(REX, PF_3A_66, 0x60), 1, &OpDispatchBuilder::VPCMPESTRMOp},
       {OPD(REX, PF_3A_66, 0x61), 1, &OpDispatchBuilder::VPCMPESTRIOp},
@@ -37,8 +36,6 @@ constexpr auto OpDispatchTableGenH0F3A = []() consteval {
       {OPD(REX, PF_3A_66, 0x63), 1, &OpDispatchBuilder::VPCMPISTRIOp},
 
       {OPD(REX, PF_3A_NONE, 0xCC), 1, &OpDispatchBuilder::SHA1RNDS4Op},
-      {OPD(REX, PF_3A_66, 0xDF), 1, &OpDispatchBuilder::AESKeyGenAssist},
-
     };
     return std::to_array(Table);
   };
@@ -68,6 +65,11 @@ constexpr DispatchTableEntry OpDispatch_H0F3ATableNeedsREX0[] = {
   {OPD(0, PF_3A_66, 0x22), 1, &OpDispatchBuilder::PINSROp<OpSize::i32Bit>},
 };
 
+constexpr DispatchTableEntry OpDispatch_H0F3ATable_64[] = {
+  {OPD(1, PF_3A_66, 0x16), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PExtrOp, OpSize::i64Bit>},
+  {OPD(1, PF_3A_66, 0x22), 1, &OpDispatchBuilder::PINSROp<OpSize::i64Bit>},
+};
+
 #undef PF_3A_NONE
 #undef PF_3A_66
 

FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h

@@ -117,9 +117,7 @@ constexpr DispatchTableEntry OpDispatch_PrimaryGroupTables[] = {
   {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 0), 1, &OpDispatchBuilder::INCOp}, // INC
   {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 1), 1, &OpDispatchBuilder::DECOp}, // DEC
   {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 2), 1, &OpDispatchBuilder::CALLAbsoluteOp},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 3), 1, &OpDispatchBuilder::CALLFARIndirectOp},
   {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 4), 1, &OpDispatchBuilder::JUMPAbsoluteOp},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 5), 1, &OpDispatchBuilder::JUMPFARIndirectOp},
   {OPD(FEXCore::X86Tables::TYPE_GROUP_5, OpToIndex(0xFF), 6), 1, &OpDispatchBuilder::PUSHOp},
 
   // GROUP 11

FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryGroupTables.h

@@ -69,16 +69,10 @@ constexpr DispatchTableEntry OpDispatch_SecondaryGroupTables[] = {
 
   // GROUP 9
   {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_NONE, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_NONE, 6), 1, &OpDispatchBuilder::RDRANDOp<false>},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_NONE, 7), 1, &OpDispatchBuilder::RDRANDOp<true>},
-
+  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F3, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
   {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_66, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_66, 6), 1, &OpDispatchBuilder::RDRANDOp<false>},
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_66, 7), 1, &OpDispatchBuilder::RDRANDOp<true>},
-
   {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F2, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
 
-  {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F3, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
   {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F3, 7), 1, &OpDispatchBuilder::RDPIDOp},
 
   // GROUP 12
@@ -162,6 +156,18 @@ constexpr DispatchTableEntry OpDispatch_SecondaryGroupTables[] = {
   {OPD(FEXCore::X86Tables::TYPE_GROUP_P, PF_F2, 0), 8, &OpDispatchBuilder::NOPOp},
 };
 
+constexpr DispatchTableEntry OpDispatch_SecondaryGroupTables_64[] = {
+  // GROUP 15
+  {OPD(FEXCore::X86Tables::TYPE_GROUP_15, PF_F3, 0), 1,
+   &OpDispatchBuilder::Bind<&OpDispatchBuilder::ReadSegmentReg, OpDispatchBuilder::Segment::FS>},
+  {OPD(FEXCore::X86Tables::TYPE_GROUP_15, PF_F3, 1), 1,
+   &OpDispatchBuilder::Bind<&OpDispatchBuilder::ReadSegmentReg, OpDispatchBuilder::Segment::GS>},
+  {OPD(FEXCore::X86Tables::TYPE_GROUP_15, PF_F3, 2), 1,
+   &OpDispatchBuilder::Bind<&OpDispatchBuilder::WriteSegmentReg, OpDispatchBuilder::Segment::FS>},
+  {OPD(FEXCore::X86Tables::TYPE_GROUP_15, PF_F3, 3), 1,
+   &OpDispatchBuilder::Bind<&OpDispatchBuilder::WriteSegmentReg, OpDispatchBuilder::Segment::GS>},
+};
+
 #undef OPD
 
 } // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryModRMTables.h

@@ -17,7 +17,6 @@ constexpr DispatchTableEntry OpDispatch_SecondaryModRMTables[] = {
   // REG /7
   {((3 << 3) | 0), 1, &OpDispatchBuilder::PermissionRestrictedOp},
   {((3 << 3) | 1), 1, &OpDispatchBuilder::RDTSCPOp},
-  {((3 << 3) | 4), 1, &OpDispatchBuilder::CLZeroOp},
 };
 
 } // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h

@@ -313,4 +313,20 @@ constexpr DispatchTableEntry OpDispatch_SecondaryOpSizeModTables[] = {
   {0xFD, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADD, OpSize::i16Bit>},
   {0xFE, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADD, OpSize::i32Bit>},
 };
+
+constexpr DispatchTableEntry OpDispatch_TwoByteOpTable_64[] = {
+  {0x05, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SyscallOp, true>},
+  {0xA0, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX>},
+  {0xA1, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX>},
+  {0xA8, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX>},
+  {0xA9, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX>},
+};
+
+constexpr DispatchTableEntry OpDispatch_TwoByteOpTable_32[] = {
+  {0x05, 1, &OpDispatchBuilder::NOPOp},
+  {0xA0, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX>},
+  {0xA1, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX>},
+  {0xA8, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX>},
+  {0xA9, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX>},
+};
 } // namespace FEXCore::IR

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp

@@ -477,7 +477,7 @@ Ref OpDispatchBuilder::InsertScalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::OpSiz
   // We load the full vector width when dealing with a source vector,
   // so that we don't do any unnecessary zero extension to the scalar
   // element that we're going to operate on.
-  const auto SrcSize = Src2Op.IsGPR() ? OpSize::i128Bit : SrcElementSize;
+  const auto SrcSize = OpSizeFromSrc(Op);
 
   Ref Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, DstSize, Op->Flags);
   Ref Src2 = LoadSource_WithOpSize(FPRClass, Op, Src2Op, SrcSize, Op->Flags, {.AllowUpperGarbage = true});
@@ -2557,8 +2557,6 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) {
-  _SyncStackToSlow();
-
   // Saves 512bytes to the memory location provided
   // Header changes depending on if REX.W is set or not
   if (Op->Flags & X86Tables::DecodeFlags::FLAG_REX_WIDENING) {
@@ -2582,8 +2580,7 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) {
 
   {
     // Abridged FTW
-    auto FTW = _LoadContext(OpSize::i8Bit, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
-    _StoreMem(GPRClass, OpSize::i8Bit, FTW, MemBase, Constant(4), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
+    _StoreMem(GPRClass, OpSize::i8Bit, LoadContext(AbridgedFTWIndex), MemBase, Constant(4), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
   }
 
   // BYTE | 0 1 | 2 3 | 4   | 5     | 6 7 | 8 9 | a b | c d | e f |
@@ -2630,19 +2627,9 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) {
   // MXCSR_MASK: Mask for writes to the MXCSR register
   // If OSFXSR bit in CR4 is not set than FXSAVE /may/ not save the XMM registers
   // This is implementation dependent
-  //
-  // x87 registers are stored rotated depending on the current TOP.
-  Ref Top = GetX87Top();
-  auto SevenConst = Constant(7);
-  const auto LoadSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit;
-
-  for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-    Ref data = _LoadContextIndexed(Top, LoadSize, MMBaseOffset(), IR::OpSizeToSize(OpSize::i128Bit), FPRClass);
-    if (ReducedPrecisionMode) {
-      data = _F80CVTTo(data, OpSize::i64Bit);
-    }
-    _StoreMem(FPRClass, OpSize::i128Bit, data, MemBase, Constant(16 * i + 32), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
-    Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst);
+  for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; i += 2) {
+    RefPair MMRegs = LoadContextPair(OpSize::i128Bit, MM0Index + i);
+    _StoreMemPair(FPRClass, OpSize::i128Bit, MMRegs.Low, MMRegs.High, MemBase, i * 16 + 32);
   }
 }
 
@@ -2753,8 +2740,6 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::RestoreX87State(Ref MemBase) {
-  _StackForceSlow();
-
   auto NewFCW = _LoadMem(GPRClass, OpSize::i16Bit, MemBase, OpSize::i16Bit);
   _StoreContext(OpSize::i16Bit, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
@@ -2765,14 +2750,14 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) {
 
   {
     // Abridged FTW
-    auto NewFTW = _LoadMem(GPRClass, OpSize::i8Bit, MemBase, Constant(4), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
-    _StoreContext(OpSize::i8Bit, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
+    StoreContext(AbridgedFTWIndex, _LoadMem(GPRClass, OpSize::i8Bit, MemBase, Constant(4), OpSize::i8Bit, MEM_OFFSET_SXTX, 1));
   }
 
   for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; i += 2) {
     auto MMRegs = LoadMemPair(FPRClass, OpSize::i128Bit, MemBase, i * 16 + 32);
-    _StoreContext(OpSize::i128Bit, FPRClass, MMRegs.Low, MMBaseOffset() + i * 16);
-    _StoreContext(OpSize::i128Bit, FPRClass, MMRegs.High, MMBaseOffset() + (i + 1) * 16);
+
+    StoreContext(MM0Index + i, MMRegs.Low);
+    StoreContext(MM0Index + i + 1, MMRegs.High);
   }
 }
 
@@ -2818,7 +2803,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) {
   // all of the ST0-7/MM0-7 registers to zero.
   Ref ZeroVector = LoadZeroVector(OpSize::i64Bit);
   for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-    _StoreContext(OpSize::i128Bit, FPRClass, ZeroVector, MMBaseOffset() + i * 16);
+    StoreContext(MM0Index + i, ZeroVector);
   }
 }
 
@@ -3965,7 +3950,10 @@ void OpDispatchBuilder::PTestOpImpl(OpSize Size, Ref Dest, Ref Src) {
   Test1 = _VExtractToGPR(Size, OpSize::i16Bit, Test1, 0);
   Test2 = _VExtractToGPR(Size, OpSize::i16Bit, Test2, 0);
 
-  Test2 = To01(OpSize::i64Bit, Test2);
+  auto ZeroConst = Constant(0);
+  auto OneConst = Constant(1);
+
+  Test2 = _Select(FEXCore::IR::COND_NEQ, Test2, ZeroConst, OneConst, ZeroConst);
 
   // Careful, these flags are different between {V,}PTEST and VTESTP{S,D}
   // Set ZF according to Test1. SF will be zeroed since we do a 32-bit test on
@@ -4002,7 +3990,10 @@ void OpDispatchBuilder::VTESTOpImpl(OpSize SrcSize, IR::OpSize ElementSize, Ref
   Ref AndGPR = _VExtractToGPR(SrcSize, OpSize::i16Bit, MaxAnd, 0);
   Ref AndNotGPR = _VExtractToGPR(SrcSize, OpSize::i16Bit, MaxAndNot, 0);
 
-  Ref CFInv = To01(OpSize::i64Bit, AndNotGPR);
+  Ref ZeroConst = Constant(0);
+  Ref OneConst = Constant(1);
+
+  Ref CFInv = _Select(IR::COND_NEQ, AndNotGPR, ZeroConst, OneConst, ZeroConst);
 
   // As in PTest, this sets Z appropriately while zeroing the rest of NZCV.
   SetNZ_ZeroCV(OpSize::i32Bit, AndGPR);
@@ -5016,7 +5007,7 @@ void OpDispatchBuilder::VFMAddSubImpl(OpcodeArgs, bool AddSub, uint8_t Src1Idx,
 }
 
 OpDispatchBuilder::RefVSIB OpDispatchBuilder::LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags) {
-  const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
+  [[maybe_unused]] const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
   LOGMAN_THROW_A_FMT(Operand.IsSIB() && IsVSIB, "Trying to load VSIB for something that isn't the correct type!");
 
   // VSIB is a very special case which has a ton of encoded data.
@@ -5093,7 +5084,7 @@ void OpDispatchBuilder::VPGATHER(OpcodeArgs) {
     ///< BaseAddr doesn't need to exist, calculate that here.
     Ref BaseAddr = VSIB.BaseAddr;
     if (BaseAddr && VSIB.Displacement) {
-      BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement);
+      BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement));
     } else if (VSIB.Displacement) {
       BaseAddr = Constant(VSIB.Displacement);
     } else if (!BaseAddr) {

FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp

@@ -32,27 +32,21 @@ Ref OpDispatchBuilder::GetX87Top() {
 }
 
 void OpDispatchBuilder::SetX87FTW(Ref FTW) {
-  _StackForceSlow(); // Invalidate x87 FTW register cache
+  Ref X87Empty = Constant(static_cast<uint8_t>(FPState::X87Tag::Empty));
+  Ref NewAbridgedFTW {};
 
-  // For the output, we want a 1-bit for each pair not equal to 11 (Empty).
-  static_assert(static_cast<uint8_t>(FPState::X87Tag::Empty) == 0b11);
+  for (int i = 0; i < 8; i++) {
+    Ref RegTag = _Bfe(OpSize::i32Bit, 2, i * 2, FTW);
+    Ref RegValid = _Select(FEXCore::IR::COND_NEQ, RegTag, X87Empty, Constant(1), Constant(0));
 
-  // Make even bits 1 if the pair is equal to 11, and 0 otherwise.
-  FTW = _AndShift(OpSize::i32Bit, FTW, FTW, ShiftType::LSR, 1);
+    if (i) {
+      NewAbridgedFTW = _Orlshl(OpSize::i32Bit, NewAbridgedFTW, RegValid, i);
+    } else {
+      NewAbridgedFTW = RegValid;
+    }
+  }
 
-  // Invert FTW and clear the odd bits. Even bits are 1 if the pair
-  // is not equal to 11, and odd bits are 0.
-  FTW = _Andn(OpSize::i32Bit, Constant(0x55555555), FTW);
-
-  // All that's left is to compact away the odd bits. That is a Morton
-  // deinterleave operation, which has a standard solution. See
-  // https://stackoverflow.com/questions/3137266/how-to-de-interleave-bits-unmortonizing
-  FTW = _And(OpSize::i32Bit, _Orlshr(OpSize::i32Bit, FTW, FTW, 1), Constant(0x33333333));
-  FTW = _And(OpSize::i32Bit, _Orlshr(OpSize::i32Bit, FTW, FTW, 2), Constant(0x0f0f0f0f));
-  FTW = _Orlshr(OpSize::i32Bit, FTW, FTW, 4);
-
-  // ...and that's it. StoreContext implicitly does the final masking.
-  _StoreContext(OpSize::i8Bit, GPRClass, FTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
+  StoreContext(AbridgedFTWIndex, NewAbridgedFTW);
 }
 
 void OpDispatchBuilder::SetX87Top(Ref Value) {
@@ -116,10 +110,10 @@ void OpDispatchBuilder::FILD(OpcodeArgs) {
   auto absolute = _Neg(OpSize::i64Bit, Data, CondClassType {COND_MI});
 
   // left justify the absolute integer
-  auto shift = Sub(OpSize::i64Bit, Constant(63), _FindMSB(IR::OpSize::i64Bit, absolute));
+  auto shift = _Sub(OpSize::i64Bit, Constant(63), _FindMSB(IR::OpSize::i64Bit, absolute));
   auto shifted = _Lshl(OpSize::i64Bit, absolute, shift);
 
-  auto adjusted_exponent = Sub(OpSize::i64Bit, Constant(0x3fff + 63), shift);
+  auto adjusted_exponent = _Sub(OpSize::i64Bit, Constant(0x3fff + 63), shift);
   auto zeroed_exponent = _Select(COND_EQ, absolute, zero, zero, adjusted_exponent);
   auto upper = _Or(OpSize::i64Bit, sign, zeroed_exponent);
 
@@ -166,12 +160,12 @@ void OpDispatchBuilder::FIST(OpcodeArgs, bool Truncate) {
     // Check for NaN/Infinity: exponent = 0x7fff
     SaveNZCV();
     _TestNZ(OpSize::i64Bit, Exponent, Constant(0x7fff));
-    Ref IsSpecial = _NZCVSelect01({COND_EQ});
+    Ref IsSpecial = _NZCVSelect(OpSize::i64Bit, {COND_EQ}, Constant(1), Constant(0));
 
     // For overflow detection, check if exponent indicates a value >= 2^15
     // Biased exponent for 2^15 is 0x3fff + 15 = 0x400e
-    SubWithFlags(OpSize::i64Bit, Exponent, 0x400e);
-    Ref IsOverflow = _NZCVSelect01({COND_UGE});
+    _SubWithFlags(OpSize::i64Bit, Exponent, Constant(0x400e));
+    Ref IsOverflow = _NZCVSelect(OpSize::i64Bit, {COND_UGE}, Constant(1), Constant(0));
 
     // Set Invalid Operation flag if overflow or special value
     Ref InvalidFlag = _Or(OpSize::i64Bit, IsSpecial, IsOverflow);
@@ -340,7 +334,7 @@ Ref OpDispatchBuilder::GetX87FTW_Helper() {
   // bytes, we use the well-known bit twiddling algorithm:
   //
   // https://graphics.stanford.edu/~seander/bithacks.html#InterleaveBMN
-  Ref X = _LoadContext(OpSize::i8Bit, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
+  Ref X = LoadContext(AbridgedFTWIndex);
   X = _Orlshl(OpSize::i32Bit, X, X, 4);
   X = _And(OpSize::i32Bit, X, Constant(0x0f0f0f0f));
   X = _Orlshl(OpSize::i32Bit, X, X, 2);
@@ -427,13 +421,11 @@ Ref OpDispatchBuilder::ReconstructX87StateFromFSW_Helper(Ref FSW) {
   auto C1 = _Bfe(OpSize::i32Bit, 1, 9, FSW);
   auto C2 = _Bfe(OpSize::i32Bit, 1, 10, FSW);
   auto C3 = _Bfe(OpSize::i32Bit, 1, 14, FSW);
-  auto IE = _Bfe(OpSize::i32Bit, 1, 0, FSW);
 
   SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(C0);
   SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(C1);
   SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(C2);
   SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(C3);
-  SetRFLAG<FEXCore::X86State::X87FLAG_IE_LOC>(IE);
   return Top;
 }
 
@@ -447,13 +439,13 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) {
   auto NewFCW = _LoadMem(GPRClass, OpSize::i16Bit, Mem, OpSize::i16Bit);
   _StoreContext(OpSize::i16Bit, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
-  Ref MemLocation = Add(OpSize::i64Bit, Mem, IR::OpSizeToSize(Size) * 1);
+  Ref MemLocation = _Add(OpSize::i64Bit, Mem, Constant(IR::OpSizeToSize(Size) * 1));
   auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
   ReconstructX87StateFromFSW_Helper(NewFSW);
 
   {
     // FTW
-    Ref MemLocation = Add(OpSize::i64Bit, Mem, IR::OpSizeToSize(Size) * 2);
+    Ref MemLocation = _Add(OpSize::i64Bit, Mem, Constant(IR::OpSizeToSize(Size) * 2));
     SetX87FTW(_LoadMem(GPRClass, Size, MemLocation, Size));
   }
 }
@@ -516,6 +508,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
     _StoreMem(GPRClass, Size, ZeroConst, Mem, Constant(IR::OpSizeToSize(Size) * 6), Size, MEM_OFFSET_SXTX, 1);
   }
 
+  auto OneConst = Constant(1);
   auto SevenConst = Constant(7);
   const auto LoadSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit;
   for (int i = 0; i < 7; ++i) {
@@ -524,7 +517,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
       data = _F80CVTTo(data, OpSize::i64Bit);
     }
     _StoreMem(FPRClass, OpSize::i128Bit, data, Mem, Constant((IR::OpSizeToSize(Size) * 7) + (10 * i)), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
-    Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst);
+    Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -568,7 +561,9 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
     SetX87FTW(_LoadMem(GPRClass, Size, Mem, Constant(IR::OpSizeToSize(Size) * 2), Size, MEM_OFFSET_SXTX, 1));
   }
 
+  auto OneConst = Constant(1);
   auto SevenConst = Constant(7);
+
   auto low = Constant(~0ULL);
   auto high = Constant(0xFFFF);
   Ref Mask = _VLoadTwoGPRs(low, high);
@@ -583,7 +578,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
     }
     _StoreContextIndexed(Reg, Top, StoreSize, MMBaseOffset(), IR::OpSizeToSize(OpSize::i128Bit), FPRClass);
 
-    Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst);
+    Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -591,7 +586,8 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
   // Lower 64bits [63:0]
   // upper 16 bits [79:64]
   Ref Reg = _LoadMem(FPRClass, OpSize::i64Bit, Mem, Constant((IR::OpSizeToSize(Size) * 7) + (10 * 7)), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
-  Ref RegHigh = _LoadMem(FPRClass, OpSize::i16Bit, Mem, Constant((IR::OpSizeToSize(Size) * 7) + (10 * 7) + 8), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
+  Ref RegHigh =
+    _LoadMem(FPRClass, OpSize::i16Bit, Mem, Constant((IR::OpSizeToSize(Size) * 7) + (10 * 7) + 8), OpSize::i8Bit, MEM_OFFSET_SXTX, 1);
   Reg = _VInsElement(OpSize::i128Bit, OpSize::i16Bit, 4, 0, Reg, RegHigh);
   if (ReducedPrecisionMode) {
     Reg = _F80CVT(OpSize::i64Bit, Reg); // Convert to double precision
@@ -681,9 +677,6 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs, IR::OpSize Width, bool Integer, OpDisp
     SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(PF);
   }
 
-  // Set Invalid Operation flag when unordered (NaN comparison)
-  SetRFLAG<FEXCore::X86State::X87FLAG_IE_LOC>(HostFlag_Unordered);
-
   if (PopTwice) {
     _PopStackDestroy();
     _PopStackDestroy();
@@ -705,9 +698,6 @@ void OpDispatchBuilder::FTST(OpcodeArgs) {
   SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Constant(0));
   SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(HostFlag_Unordered);
   SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(HostFlag_ZF);
-
-  // Set Invalid Operation flag when unordered (NaN comparison)
-  SetRFLAG<FEXCore::X86State::X87FLAG_IE_LOC>(HostFlag_Unordered);
 }
 
 void OpDispatchBuilder::X87OpHelper(OpcodeArgs, FEXCore::IR::IROps IROp, bool ZeroC2) {
@@ -769,14 +759,7 @@ void OpDispatchBuilder::X87FNSTSW(OpcodeArgs) {
   StoreResult(GPRClass, Op, StatusWord, OpSize::iInvalid);
 }
 
-void OpDispatchBuilder::FNCLEX(OpcodeArgs) {
-  // Clear the exception flag bit
-  SetRFLAG<FEXCore::X86State::X87FLAG_IE_LOC>(_Constant(0));
-}
-
 void OpDispatchBuilder::FNINIT(OpcodeArgs) {
-  _SyncStackToSlow(); // Invalidate x87 register caches
-
   auto Zero = Constant(0);
 
   if (ReducedPrecisionMode) {
@@ -790,7 +773,7 @@ void OpDispatchBuilder::FNINIT(OpcodeArgs) {
   // Set top to zero
   SetX87Top(Zero);
   // Tags all get marked as invalid
-  _StoreContext(OpSize::i8Bit, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
+  StoreContext(AbridgedFTWIndex, Zero);
 
   // Reinits the simulated stack
   _InitStack();
@@ -799,7 +782,6 @@ void OpDispatchBuilder::FNINIT(OpcodeArgs) {
   SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Zero);
   SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(Zero);
   SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(Zero);
-  SetRFLAG<FEXCore::X86State::X87FLAG_IE_LOC>(Zero);
 }
 
 void OpDispatchBuilder::X87FFREE(OpcodeArgs) {
@@ -845,7 +827,11 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
   default: LOGMAN_MSG_A_FMT("Unhandled FCMOV op: 0x{:x}", Opcode); break;
   }
 
-  Ref VecCond = _VDupFromGPR(OpSize::i128Bit, OpSize::i64Bit, SelectCC0All1(CC));
+  auto ZeroConst = Constant(0);
+  auto AllOneConst = Constant(0xffff'ffff'ffff'ffffull);
+
+  Ref SrcCond = SelectCC(CC, OpSize::i64Bit, AllOneConst, ZeroConst);
+  Ref VecCond = _VDupFromGPR(OpSize::i128Bit, OpSize::i64Bit, SrcCond);
   _F80VBSLStack(OpSize::i128Bit, VecCond, Op->OP & 7, 0);
 }
 
@@ -861,9 +847,11 @@ void OpDispatchBuilder::X87FXAM(OpcodeArgs) {
   // Claim this is a normal number
   // We don't support anything else
   auto TopValid = _StackValidTag(0);
+  auto ZeroConst = Constant(0);
+  auto OneConst = Constant(1);
 
   // In the case of top being invalid then C3:C2:C0 is 0b101
-  auto C3 = Select01(OpSize::i32Bit, CondClassType {COND_NEQ}, TopValid, Constant(1));
+  auto C3 = _Select(FEXCore::IR::COND_NEQ, TopValid, OneConst, OneConst, ZeroConst);
 
   auto C2 = TopValid;
   auto C0 = C3; // Mirror C3 until something other than zero is supported

FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp

@@ -60,7 +60,7 @@ void OpDispatchBuilder::X87FLDCWF64(OpcodeArgs) {
 // Float load op with memory operand
 void OpDispatchBuilder::FLDF64(OpcodeArgs, IR::OpSize Width) {
   const auto ReadWidth = (Width == OpSize::f80Bit) ? OpSize::i128Bit : Width;
-  Ref Data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], Width, Op->Flags);
+  Ref Data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], ReadWidth, Op->Flags);
   // Convert to 64bit float
   Ref ConvertedData = Data;
   if (Width == OpSize::i32Bit) {
@@ -73,7 +73,7 @@ void OpDispatchBuilder::FLDF64(OpcodeArgs, IR::OpSize Width) {
 
 void OpDispatchBuilder::FBLDF64(OpcodeArgs) {
   // Read from memory
-  Ref Data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], OpSize::f80Bit, Op->Flags);
+  Ref Data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], OpSize::i128Bit, Op->Flags);
   Ref ConvertedData = _F80BCDLoad(Data);
   ConvertedData = _F80CVT(OpSize::i64Bit, ConvertedData);
   _PushStack(ConvertedData, Data, OpSize::i64Bit, true);
@@ -382,7 +382,7 @@ void OpDispatchBuilder::X87FXTRACTF64(OpcodeArgs) {
 
   // non zero case
   Ref ExpNZ = _Bfe(OpSize::i64Bit, 11, 52, Gpr);
-  ExpNZ = Sub(OpSize::i64Bit, ExpNZ, Constant(1023));
+  ExpNZ = _Sub(OpSize::i64Bit, ExpNZ, Constant(1023));
   Ref ExpNZV = _Float_FromGPR_S(OpSize::i64Bit, OpSize::i64Bit, ExpNZ);
 
   Ref SigNZ = _And(OpSize::i64Bit, Gpr, Constant(0x800f'ffff'ffff'ffffLL));

FEXCore/Source/Interface/Core/X86HelperGen.cpp

@@ -33,7 +33,7 @@ X86GeneratedCode::X86GeneratedCode() {
 
   CallbackReturn = reinterpret_cast<uint64_t>(CodePtr);
 
-  memcpy(reinterpret_cast<void*>(CallbackReturn), SignalReturnCode.data(), SignalReturnCode.size());
+  memcpy(reinterpret_cast<void*>(CallbackReturn), &SignalReturnCode.at(0), SignalReturnCode.size());
 
   mprotect(CodePtr, CODE_SIZE, PROT_READ);
 #endif

FEXCore/Source/Interface/Core/X86Tables.cpp

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: MIT
+/*
+$info$
+meta: frontend|x86-tables ~ Metadata that drives the frontend x86/64 decoding
+tags: frontend|x86-tables
+$end_info$
+*/
+
+#include "Interface/Core/X86Tables/X86Tables.h"
+
+#include <FEXCore/Core/Context.h>
+
+namespace FEXCore::X86Tables {
+
+void InitializeBaseTables(Context::OperatingMode Mode);
+void InitializeSecondaryTables(Context::OperatingMode Mode);
+void InitializeSecondaryGroupTables(Context::OperatingMode Mode);
+void InitializePrimaryGroupTables(Context::OperatingMode Mode);
+void InitializeH0F3ATables(Context::OperatingMode Mode);
+
+void InitializeInfoTables(Context::OperatingMode Mode) {
+  InitializeBaseTables(Mode);
+  InitializeSecondaryTables(Mode);
+  InitializeSecondaryGroupTables(Mode);
+  InitializePrimaryGroupTables(Mode);
+  InitializeH0F3ATables(Mode);
+}
+
+} // namespace FEXCore::X86Tables

FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp

@@ -15,425 +15,300 @@ $end_info$
 namespace FEXCore::X86Tables {
 using namespace InstFlags;
 
-enum Primary_LUT {
-  ENTRY_06,
-  ENTRY_07,
-  ENTRY_0E,
-  ENTRY_16,
-  ENTRY_17,
-  ENTRY_1E,
-  ENTRY_1F,
-  ENTRY_27,
-  ENTRY_2F,
-  ENTRY_37,
-  ENTRY_3F,
-  ENTRY_40,
-  ENTRY_48,
-  ENTRY_60,
-  ENTRY_61,
-  ENTRY_63,
-  ENTRY_9A,
-  ENTRY_A0,
-  ENTRY_A1,
-  ENTRY_A2,
-  ENTRY_A3,
-  ENTRY_CE,
-  ENTRY_D4,
-  ENTRY_D5,
-  ENTRY_D6,
-  ENTRY_EA,
-  ENTRY_MAX,
-};
-
-constexpr std::array<X86InstInfo[2], ENTRY_MAX> Primary_ArchSelect_LUT = {{
-  // ENTRY_06
-  {
-    {"PUSH ES",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_07
-  {
-    {"POP ES",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_0E
-  {
-    {"PUSH CS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_CS_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_16
-  {
-    {"PUSH SS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_17
-  {
-    {"POP SS",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_1E
-  {
-    {"PUSH DS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::PUSHSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_1F
-  {
-    {"POP DS",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::POPSegmentOp, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX> } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_27
-  {
-    {"DAA",      TYPE_INST, GenFlagsDstSize(SIZE_8BIT) | FLAGS_SF_DST_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::DAAOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_2F
-  {
-    {"DAS",      TYPE_INST, GenFlagsDstSize(SIZE_8BIT) | FLAGS_SF_DST_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::DASOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_37
-  {
-    {"AAA",      TYPE_INST, GenFlagsDstSize(SIZE_16BIT) | FLAGS_SF_DST_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::AAAOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_3F
-  {
-    {"AAS",      TYPE_INST, GenFlagsDstSize(SIZE_16BIT) | FLAGS_SF_DST_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::AASOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_40
-  {
-    {"INC",    TYPE_INST, FLAGS_SF_REX_IN_BYTE, 0, { .OpDispatch = &IR::OpDispatchBuilder::INCOp } },
-    // REX
-    {"", TYPE_REX_PREFIX, FLAGS_NONE, 0},
-  },
-  // ENTRY_48
-  {
-    {"DEC",    TYPE_INST, FLAGS_SF_REX_IN_BYTE, 0, { .OpDispatch = &IR::OpDispatchBuilder::DECOp } },
-    {"", TYPE_REX_PREFIX, FLAGS_NONE, 0},
-  },
-  // ENTRY_60
-  {
-    {"PUSHA",  TYPE_INST, FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::PUSHAOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_61
-  {
-    {"POPA",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS, 0, { .OpDispatch = &IR::OpDispatchBuilder::POPAOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_63
-  {
-    {"ARPL",   TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-    {"MOVSXD", TYPE_INST, GenFlagsDstSize(SIZE_64BIT) | FLAGS_MODRM, 0, { .OpDispatch = &IR::OpDispatchBuilder::MOVSXDOp } },
-  },
-  // ENTRY_9A
-  {
-    {"CALLF",  TYPE_INST, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_A0
-  {
-    {"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-    {"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-  },
-  // ENTRY_A1
-  {
-    {"MOV",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-    {"MOV",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-  },
-  // ENTRY_A2
-  {
-    {"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-    {"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-  },
-  // ENTRY_A3
-  {
-    {"MOV",    TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-    {"MOV",    TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } },
-  },
-  // ENTRY_CE
-  {
-    {"INTO",   TYPE_INST, FLAGS_NONE, 0, { .OpDispatch = &IR::OpDispatchBuilder::INTOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_D4
-  {
-    {"AAM",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX, 1, { .OpDispatch = &IR::OpDispatchBuilder::AAMOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_D5
-  {
-    {"AAD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX, 1, { .OpDispatch = &IR::OpDispatchBuilder::AADOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_D6
-  {
-    {"SALC",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::SALCOp } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-  // ENTRY_EA
-  {
-    {"JMPF",   TYPE_INST, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-  },
-}};
-
-const std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> BaseOps = []() consteval {
+std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> BaseOps = []() consteval {
   std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> Table{};
 
   constexpr U8U8InfoStruct BaseOpTable[] = {
     // Prefixes
     // Operand size overide
-    {0x66, 1, X86InstInfo{"",      TYPE_PREFIX, FLAGS_NONE,        0}},
+    {0x66, 1, X86InstInfo{"",      TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
     // Address size override
-    {0x67, 1, X86InstInfo{"",      TYPE_PREFIX, FLAGS_NONE,        0}},
-    {0x26, 1, X86InstInfo{"ES",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0}},
-    {0x2E, 1, X86InstInfo{"CS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0}},
-    {0x36, 1, X86InstInfo{"SS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0}},
-    {0x3E, 1, X86InstInfo{"DS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0}},
+    {0x67, 1, X86InstInfo{"",      TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0x26, 1, X86InstInfo{"ES",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0, nullptr}},
+    {0x2E, 1, X86InstInfo{"CS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0, nullptr}},
+    {0x36, 1, X86InstInfo{"SS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0, nullptr}},
+    {0x3E, 1, X86InstInfo{"DS",    TYPE_LEGACY_PREFIX, FLAGS_NONE, 0, nullptr}},
     // These are still invalid on 64bit
-    {0x64, 1, X86InstInfo{"FS",    TYPE_PREFIX, FLAGS_NONE,        0}},
-    {0x65, 1, X86InstInfo{"GS",    TYPE_PREFIX, FLAGS_NONE,        0}},
-    {0xF0, 1, X86InstInfo{"LOCK",  TYPE_PREFIX, FLAGS_NONE,        0}},
-    {0xF2, 1, X86InstInfo{"REPNE", TYPE_PREFIX, FLAGS_NONE,        0}},
-    {0xF3, 1, X86InstInfo{"REP",   TYPE_PREFIX, FLAGS_NONE,        0}},
+    {0x64, 1, X86InstInfo{"FS",    TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0x65, 1, X86InstInfo{"GS",    TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0xF0, 1, X86InstInfo{"LOCK",  TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0xF2, 1, X86InstInfo{"REPNE", TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0xF3, 1, X86InstInfo{"REP",   TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
 
     // Instructions
-    {0x00, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x01, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0}},
-    {0x02, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x03, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x04, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x05, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
+    {0x00, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x01, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0, nullptr}},
+    {0x02, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x03, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x04, 1, X86InstInfo{"ADD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x05, 1, X86InstInfo{"ADD",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x06, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_06] }}},
-    {0x07, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_07] }}},
+    {0x08, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x09, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0, nullptr}},
+    {0x0A, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x0B, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x0C, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                              1, nullptr}},
+    {0x0D, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x08, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x09, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0}},
-    {0x0A, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x0B, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x0C, 1, X86InstInfo{"OR",     TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                              1}},
-    {0x0D, 1, X86InstInfo{"OR",     TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
-    {0x0E, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_0E] }}},
+    {0x10, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x11, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0, nullptr}},
+    {0x12, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x13, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x14, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x15, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x10, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x11, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0}},
-    {0x12, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x13, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x14, 1, X86InstInfo{"ADC",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x15, 1, X86InstInfo{"ADC",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
-    {0x16, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_16] }}},
-    {0x17, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_17] }}},
+    {0x18, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x19, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0, nullptr}},
+    {0x1A, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x1B, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x1C, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x1D, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x18, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x19, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2,                                       0}},
-    {0x1A, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x1B, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x1C, 1, X86InstInfo{"SBB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x1D, 1, X86InstInfo{"SBB",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
-    {0x1E, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_1E] }}},
-    {0x1F, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_1F] }}},
+    {0x20, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x21, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0, nullptr}},
+    {0x22, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x23, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x24, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x25, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x20, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x21, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0}},
-    {0x22, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x23, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x24, 1, X86InstInfo{"AND",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x25, 1, X86InstInfo{"AND",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
+    {0x28, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x29, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0, nullptr}},
+    {0x2A, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x2B, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x2C, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                              1, nullptr}},
+    {0x2D, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x27, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_27] }}},
-    {0x28, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x29, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0}},
-    {0x2A, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x2B, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x2C, 1, X86InstInfo{"SUB",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                              1}},
-    {0x2D, 1, X86InstInfo{"SUB",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
-    {0x2F, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_2F] }}},
+    {0x30, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x31, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0, nullptr}},
+    {0x32, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x33, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x34, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x35, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x30, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x31, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0}},
-    {0x32, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x33, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x34, 1, X86InstInfo{"XOR",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x35, 1, X86InstInfo{"XOR",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
+    {0x38, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0, nullptr}},
+    {0x39, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0, nullptr}},
+    {0x3A, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0, nullptr}},
+    {0x3B, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_MODRM,                                                                   0, nullptr}},
+    {0x3C, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1, nullptr}},
+    {0x3D, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4, nullptr}},
 
-    {0x37, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_37] }}},
-    {0x38, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                   0}},
-    {0x39, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                                                                   0}},
-    {0x3A, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,                                                   0}},
-    {0x3B, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_MODRM,                                                                   0}},
-    {0x3C, 1, X86InstInfo{"CMP",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX  ,                              1}},
-    {0x3D, 1, X86InstInfo{"CMP",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2, 4}},
-    {0x3F, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_3F] }}},
+    {0x50, 8, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SF_REX_IN_BYTE | FLAGS_DEBUG_MEM_ACCESS ,                    0, nullptr}},
+    {0x58, 8, X86InstInfo{"POP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SF_REX_IN_BYTE | FLAGS_DEBUG_MEM_ACCESS ,                    0, nullptr}},
 
-    {0x40, 8, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_40] }}},
-    {0x48, 8, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_48] }}},
+    {0x62, 1, X86InstInfo{"",       TYPE_GROUP_EVEX, FLAGS_NONE,                                                                           0, nullptr}},
 
-    {0x50, 8, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SF_REX_IN_BYTE | FLAGS_DEBUG_MEM_ACCESS ,                    0}},
-    {0x58, 8, X86InstInfo{"POP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SF_REX_IN_BYTE | FLAGS_DEBUG_MEM_ACCESS ,                    0}},
-
-
-    {0x60, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_60] }}},
-    {0x61, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_61] }}},
-    {0x62, 1, X86InstInfo{"",       TYPE_GROUP_EVEX, FLAGS_NONE,                                                                           0}},
-    {0x63, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_63] }}},
-
-    {0x68, 1, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_SRC_SEXT, 4}},
-    {0x69, 1, X86InstInfo{"IMUL",   TYPE_INST, FLAGS_MODRM | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,        4}},
-    {0x6A, 1, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SRC_SEXT ,            1}},
-    {0x6B, 1, X86InstInfo{"IMUL",   TYPE_INST, FLAGS_MODRM | FLAGS_SRC_SEXT ,                                    1}},
+    {0x68, 1, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_SRC_SEXT, 4, nullptr}},
+    {0x69, 1, X86InstInfo{"IMUL",   TYPE_INST, FLAGS_MODRM | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,        4, nullptr}},
+    {0x6A, 1, X86InstInfo{"PUSH",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SRC_SEXT ,            1, nullptr}},
+    {0x6B, 1, X86InstInfo{"IMUL",   TYPE_INST, FLAGS_MODRM | FLAGS_SRC_SEXT ,                                    1, nullptr}},
 
     // This should just throw a GP
-    {0x6C, 1, X86InstInfo{"INSB",   TYPE_INST, FLAGS_BLOCK_END, 0}},
-    {0x6D, 1, X86InstInfo{"INSW",   TYPE_INST, FLAGS_BLOCK_END, 0}},
-    {0x6E, 1, X86InstInfo{"OUTS",   TYPE_INST, FLAGS_BLOCK_END, 0}},
-    {0x6F, 1, X86InstInfo{"OUTS",   TYPE_INST, FLAGS_BLOCK_END, 0}},
+    {0x6C, 1, X86InstInfo{"INSB",   TYPE_INST, FLAGS_BLOCK_END, 0, nullptr}},
+    {0x6D, 1, X86InstInfo{"INSW",   TYPE_INST, FLAGS_BLOCK_END, 0, nullptr}},
+    {0x6E, 1, X86InstInfo{"OUTS",   TYPE_INST, FLAGS_BLOCK_END, 0, nullptr}},
+    {0x6F, 1, X86InstInfo{"OUTS",   TYPE_INST, FLAGS_BLOCK_END, 0, nullptr}},
 
-    {0x70, 1, X86InstInfo{"JO",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x71, 1, X86InstInfo{"JNO",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x72, 1, X86InstInfo{"JB",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x73, 1, X86InstInfo{"JNB",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x74, 1, X86InstInfo{"JZ",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x75, 1, X86InstInfo{"JNZ",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x76, 1, X86InstInfo{"JBE",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x77, 1, X86InstInfo{"JNBE",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x78, 1, X86InstInfo{"JS",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x79, 1, X86InstInfo{"JNS",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7A, 1, X86InstInfo{"JP",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7B, 1, X86InstInfo{"JNP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7C, 1, X86InstInfo{"JL",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7D, 1, X86InstInfo{"JNL",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7E, 1, X86InstInfo{"JLE",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
-    {0x7F, 1, X86InstInfo{"JNLE",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1}},
+    {0x70, 1, X86InstInfo{"JO",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x71, 1, X86InstInfo{"JNO",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x72, 1, X86InstInfo{"JB",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x73, 1, X86InstInfo{"JNB",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x74, 1, X86InstInfo{"JZ",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x75, 1, X86InstInfo{"JNZ",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x76, 1, X86InstInfo{"JBE",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x77, 1, X86InstInfo{"JNBE",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x78, 1, X86InstInfo{"JS",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x79, 1, X86InstInfo{"JNS",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7A, 1, X86InstInfo{"JP",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7B, 1, X86InstInfo{"JNP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7C, 1, X86InstInfo{"JL",     TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7D, 1, X86InstInfo{"JNL",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7E, 1, X86InstInfo{"JLE",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
+    {0x7F, 1, X86InstInfo{"JNLE",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT , 1, nullptr}},
 
-    {0x84, 1, X86InstInfo{"TEST",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0}},
-    {0x85, 1, X86InstInfo{"TEST",   TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0}},
-    {0x86, 1, X86InstInfo{"XCHG",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0}},
-    {0x87, 1, X86InstInfo{"XCHG",   TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0}},
+    {0x84, 1, X86InstInfo{"TEST",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0, nullptr}},
+    {0x85, 1, X86InstInfo{"TEST",   TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0, nullptr}},
+    {0x86, 1, X86InstInfo{"XCHG",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0, nullptr}},
+    {0x87, 1, X86InstInfo{"XCHG",   TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0, nullptr}},
 
-    {0x88, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0}},
-    {0x89, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0}},
-    {0x8A, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,         0}},
-    {0x8B, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_MODRM,                         0}},
-    {0x8C, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                      0}},
-    {0x8D, 1, X86InstInfo{"LEA",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM,                         0}},
-    {0x8E, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_16BIT) | FLAGS_MODRM,                      0}},
-    {0x8F, 1, X86InstInfo{"POP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_ZERO_REG | FLAGS_DEBUG_MEM_ACCESS, 0}},
-    {0x90, 8, X86InstInfo{"XCHG",   TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_SF_SRC_RAX, 0}},
-    {0x98, 1, X86InstInfo{"CDQE",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX,     0}},
-    {0x99, 1, X86InstInfo{"CQO",    TYPE_INST, FLAGS_SF_DST_RDX | FLAGS_SF_SRC_RAX,     0}},
+    {0x88, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,         0, nullptr}},
+    {0x89, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST,                         0, nullptr}},
+    {0x8A, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM,         0, nullptr}},
+    {0x8B, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_MODRM,                         0, nullptr}},
+    {0x8C, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                      0, nullptr}},
+    {0x8D, 1, X86InstInfo{"LEA",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM,                         0, nullptr}},
+    {0x8E, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_16BIT) | FLAGS_MODRM,                      0, nullptr}},
+    {0x8F, 1, X86InstInfo{"POP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_ZERO_REG | FLAGS_DEBUG_MEM_ACCESS, 0, nullptr}},
+    {0x90, 8, X86InstInfo{"XCHG",   TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_SF_SRC_RAX, 0, nullptr}},
+    {0x98, 1, X86InstInfo{"CDQE",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX,     0, nullptr}},
+    {0x99, 1, X86InstInfo{"CQO",    TYPE_INST, FLAGS_SF_DST_RDX | FLAGS_SF_SRC_RAX,     0, nullptr}},
 
     // These three are all X87 instructions
-    {0x9B, 1, X86InstInfo{"FWAIT",  TYPE_INST, FLAGS_NONE,                              0}},
-    {0x9C, 1, X86InstInfo{"PUSHF",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF),         0}},
-    {0x9D, 1, X86InstInfo{"POPF",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_BLOCK_END,         0}},
+    {0x9B, 1, X86InstInfo{"FWAIT",  TYPE_INST, FLAGS_NONE,                              0, nullptr}},
+    {0x9C, 1, X86InstInfo{"PUSHF",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF),         0, nullptr}},
+    {0x9D, 1, X86InstInfo{"POPF",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_BLOCK_END,         0, nullptr}},
 
-    {0x9E, 1, X86InstInfo{"SAHF",   TYPE_INST, FLAGS_NONE,                              0}},
-    {0x9F, 1, X86InstInfo{"LAHF",   TYPE_INST, FLAGS_NONE,                              0}},
+    {0x9E, 1, X86InstInfo{"SAHF",   TYPE_INST, FLAGS_NONE,                              0, nullptr}},
+    {0x9F, 1, X86InstInfo{"LAHF",   TYPE_INST, FLAGS_NONE,                              0, nullptr}},
 
-    {0xA0, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_A0] }}},
-    {0xA1, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_A1] }}},
-    {0xA2, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_A2] }}},
-    {0xA3, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_A3] }}},
+    {0xA4, 1, X86InstInfo{"MOVSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS,                                            0, nullptr}},
+    {0xA5, 1, X86InstInfo{"MOVS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                            0, nullptr}},
+    {0xA6, 1, X86InstInfo{"CMPSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS,                                            0, nullptr}},
+    {0xA7, 1, X86InstInfo{"CMPS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                            0, nullptr}},
 
-    {0xA4, 1, X86InstInfo{"MOVSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS,                                            0}},
-    {0xA5, 1, X86InstInfo{"MOVS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                            0}},
-    {0xA6, 1, X86InstInfo{"CMPSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS,                                            0}},
-    {0xA7, 1, X86InstInfo{"CMPS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                            0}},
+    {0xA8, 1, X86InstInfo{"TEST",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                                             1, nullptr}},
+    {0xA9, 1, X86InstInfo{"TEST",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,                4, nullptr}},
+    {0xAA, 1, X86InstInfo{"STOS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                   0, nullptr}},
+    {0xAB, 1, X86InstInfo{"STOS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0, nullptr}},
+    {0xAC, 1, X86InstInfo{"LODS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_DEBUG_MEM_ACCESS,                                                      0, nullptr}},
+    {0xAD, 1, X86InstInfo{"LODS",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_DEBUG_MEM_ACCESS,                                                      0, nullptr}},
+    {0xAE, 1, X86InstInfo{"SCAS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0, nullptr}},
+    {0xAF, 1, X86InstInfo{"SCAS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0, nullptr}},
 
-    {0xA8, 1, X86InstInfo{"TEST",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                                             1}},
-    {0xA9, 1, X86InstInfo{"TEST",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,                4}},
-    {0xAA, 1, X86InstInfo{"STOS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                   0}},
-    {0xAB, 1, X86InstInfo{"STOS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0}},
-    {0xAC, 1, X86InstInfo{"LODS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_DEBUG_MEM_ACCESS,                                                      0}},
-    {0xAD, 1, X86InstInfo{"LODS",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_DEBUG_MEM_ACCESS,                                                      0}},
-    {0xAE, 1, X86InstInfo{"SCAS",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0}},
-    {0xAF, 1, X86InstInfo{"SCAS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SF_SRC_RAX,                                   0}},
+    {0xB0, 8, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_REX_IN_BYTE ,                                         1, nullptr}},
+    {0xB8, 8, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_DISPLACE_SIZE_MUL_2, 4, nullptr}},
 
-    {0xB0, 8, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_REX_IN_BYTE ,                                         1}},
-    {0xB8, 8, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_DISPLACE_SIZE_MUL_2, 4}},
+    {0xC2, 1, X86InstInfo{"RET",    TYPE_INST, FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                             2, nullptr}},
+    {0xC3, 1, X86InstInfo{"RET",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END ,                                                0, nullptr}},
+    {0xC8, 1, X86InstInfo{"ENTER",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS ,                                      3, nullptr}},
+    {0xC9, 1, X86InstInfo{"LEAVE",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS ,                                                0, nullptr}},
+    {0xCA, 2, X86InstInfo{"RETF",   TYPE_PRIV, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                              0, nullptr}},
+    {0xCC, 1, X86InstInfo{"INT3",   TYPE_INST, FLAGS_BLOCK_END,                                                                                      0, nullptr}},
+    {0xCD, 1, X86InstInfo{"INT",    TYPE_INST, DEFAULT_SYSCALL_FLAGS,                                                                  1, nullptr}},
+    {0xCF, 1, X86InstInfo{"IRET",   TYPE_INST, FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                                                    0, nullptr}},
 
-    {0xC2, 1, X86InstInfo{"RET",    TYPE_INST, FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                             2}},
-    {0xC3, 1, X86InstInfo{"RET",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END ,                                                0}},
-    {0xC8, 1, X86InstInfo{"ENTER",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS ,                                      3}},
-    {0xC9, 1, X86InstInfo{"LEAVE",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS ,                                                0}},
-    {0xCA, 1, X86InstInfo{"RETF",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                              2}},
-    {0xCB, 1, X86InstInfo{"RETF",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                              0}},
-    {0xCC, 1, X86InstInfo{"INT3",   TYPE_INST, FLAGS_BLOCK_END,                                                                                      0}},
-    {0xCD, 1, X86InstInfo{"INT",    TYPE_INST, DEFAULT_SYSCALL_FLAGS,                                                                  1}},
-    {0xCE, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_CE] }}},
-    {0xCF, 1, X86InstInfo{"IRET",   TYPE_INST, FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                                                    0}},
+    {0xD7, 1, X86InstInfo{"XLAT",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                                           0, nullptr}},
 
-    {0xD4, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_D4] }}},
-    {0xD5, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_D5] }}},
-    {0xD6, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_D6] }}},
-    {0xD7, 1, X86InstInfo{"XLAT",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                                           0}},
-
-    {0xE0, 1, X86InstInfo{"LOOPNE", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1}},
-    {0xE1, 1, X86InstInfo{"LOOPE",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1}},
-    {0xE2, 1, X86InstInfo{"LOOP",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1}},
-    {0xE3, 1, X86InstInfo{"JrCXZ",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT ,                             1}},
+    {0xE0, 1, X86InstInfo{"LOOPNE", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1, nullptr}},
+    {0xE1, 1, X86InstInfo{"LOOPE",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1, nullptr}},
+    {0xE2, 1, X86InstInfo{"LOOP",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1, nullptr}},
+    {0xE3, 1, X86InstInfo{"JrCXZ",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT ,                             1, nullptr}},
 
     // Should just throw GP
-    {0xE4, 2, X86InstInfo{"IN",     TYPE_INST, FLAGS_BLOCK_END,                                                                                                      1}},
-    {0xE6, 2, X86InstInfo{"OUT",    TYPE_INST, FLAGS_BLOCK_END,                                                                                                      1}},
+    {0xE4, 2, X86InstInfo{"IN",     TYPE_INST, FLAGS_BLOCK_END,                                                                                                      1, nullptr}},
+    {0xE6, 2, X86InstInfo{"OUT",    TYPE_INST, FLAGS_BLOCK_END,                                                                                                      1, nullptr}},
 
-    {0xE8, 1, X86InstInfo{"CALL",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_BLOCK_END | FLAGS_CALL , 4}},
-    {0xE9, 1, X86InstInfo{"JMP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_BLOCK_END , 4}},
-    {0xEB, 1, X86InstInfo{"JMP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_BLOCK_END ,                             1}},
+    {0xE8, 1, X86InstInfo{"CALL",   TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_BLOCK_END | FLAGS_CALL , 4, nullptr}},
+    {0xE9, 1, X86InstInfo{"JMP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_BLOCK_END , 4, nullptr}},
+    {0xEB, 1, X86InstInfo{"JMP",    TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_BLOCK_END ,                             1, nullptr}},
 
     // Should just throw GP
-    {0xEC, 2, X86InstInfo{"IN",     TYPE_INST, FLAGS_BLOCK_END,             0}},
-    {0xEE, 2, X86InstInfo{"OUT",    TYPE_INST, FLAGS_BLOCK_END,             0}},
+    {0xEC, 2, X86InstInfo{"IN",     TYPE_INST, FLAGS_BLOCK_END,             0, nullptr}},
+    {0xEE, 2, X86InstInfo{"OUT",    TYPE_INST, FLAGS_BLOCK_END,             0, nullptr}},
 
-    {0xF1, 1, X86InstInfo{"INT1",   TYPE_INST, FLAGS_BLOCK_END,               0}},
-    {0xF4, 1, X86InstInfo{"HLT",    TYPE_INST, FLAGS_BLOCK_END,               0}},
-    {0xF5, 1, X86InstInfo{"CMC",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xF8, 1, X86InstInfo{"CLC",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xF9, 1, X86InstInfo{"STC",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xFA, 1, X86InstInfo{"CLI",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xFB, 1, X86InstInfo{"STI",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xFC, 1, X86InstInfo{"CLD",    TYPE_INST, FLAGS_NONE,                0}},
-    {0xFD, 1, X86InstInfo{"STD",    TYPE_INST, FLAGS_NONE,                0}},
+    {0xF1, 1, X86InstInfo{"INT1",   TYPE_INST, FLAGS_BLOCK_END,               0, nullptr}},
+    {0xF4, 1, X86InstInfo{"HLT",    TYPE_INST, FLAGS_BLOCK_END,               0, nullptr}},
+    {0xF5, 1, X86InstInfo{"CMC",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xF8, 1, X86InstInfo{"CLC",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xF9, 1, X86InstInfo{"STC",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xFA, 1, X86InstInfo{"CLI",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xFB, 1, X86InstInfo{"STI",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xFC, 1, X86InstInfo{"CLD",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
+    {0xFD, 1, X86InstInfo{"STD",    TYPE_INST, FLAGS_NONE,                0, nullptr}},
 
     // Two Byte table
-    {0x0F, 1, X86InstInfo{"",   TYPE_SECONDARY_TABLE_PREFIX, FLAGS_NONE,  0}},
+    {0x0F, 1, X86InstInfo{"",   TYPE_SECONDARY_TABLE_PREFIX, FLAGS_NONE,  0, nullptr}},
 
     // x87 table
-    {0xD8, 8, X86InstInfo{"",   TYPE_X87_TABLE_PREFIX, FLAGS_MODRM,        0}},
+    {0xD8, 8, X86InstInfo{"",   TYPE_X87_TABLE_PREFIX, FLAGS_MODRM,        0, nullptr}},
 
     // ModRM table
     // MoreBytes field repurposed for valid bits mask
-    {0x80, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 0}},
-    {0x81, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 1}},
-    {0x82, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 2}},
-    {0x83, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 3}},
-    {0xC0, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 0}},
-    {0xC1, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 1}},
-    {0xD0, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 2}},
-    {0xD1, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 3}},
-    {0xD2, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 4}},
-    {0xD3, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 5}},
-    {0xF6, 1, X86InstInfo{"",   TYPE_GROUP_3, FLAGS_MODRM, 0}},
-    {0xF7, 1, X86InstInfo{"",   TYPE_GROUP_3, FLAGS_MODRM, 1}},
-    {0xFE, 1, X86InstInfo{"",   TYPE_GROUP_4, FLAGS_MODRM, 0}},
-    {0xFF, 1, X86InstInfo{"",   TYPE_GROUP_5, FLAGS_MODRM, 0}},
+    {0x80, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 0, nullptr}},
+    {0x81, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 1, nullptr}},
+    {0x82, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 2, nullptr}},
+    {0x83, 1, X86InstInfo{"",   TYPE_GROUP_1, FLAGS_MODRM, 3, nullptr}},
+    {0xC0, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 0, nullptr}},
+    {0xC1, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 1, nullptr}},
+    {0xD0, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 2, nullptr}},
+    {0xD1, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 3, nullptr}},
+    {0xD2, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 4, nullptr}},
+    {0xD3, 1, X86InstInfo{"",   TYPE_GROUP_2, FLAGS_MODRM, 5, nullptr}},
+    {0xF6, 1, X86InstInfo{"",   TYPE_GROUP_3, FLAGS_MODRM, 0, nullptr}},
+    {0xF7, 1, X86InstInfo{"",   TYPE_GROUP_3, FLAGS_MODRM, 1, nullptr}},
+    {0xFE, 1, X86InstInfo{"",   TYPE_GROUP_4, FLAGS_MODRM, 0, nullptr}},
+    {0xFF, 1, X86InstInfo{"",   TYPE_GROUP_5, FLAGS_MODRM, 0, nullptr}},
 
     // Group 11
-    {0xC6, 1, X86InstInfo{"",   TYPE_GROUP_11, FLAGS_MODRM, 0}},
-    {0xC7, 1, X86InstInfo{"",   TYPE_GROUP_11, FLAGS_MODRM, 1}},
+    {0xC6, 1, X86InstInfo{"",   TYPE_GROUP_11, FLAGS_MODRM, 0, nullptr}},
+    {0xC7, 1, X86InstInfo{"",   TYPE_GROUP_11, FLAGS_MODRM, 1, nullptr}},
 
     // VEX table
-    {0xC4, 2, X86InstInfo{"",   TYPE_VEX_TABLE_PREFIX, FLAGS_NONE, 0}},
+    {0xC4, 2, X86InstInfo{"",   TYPE_VEX_TABLE_PREFIX, FLAGS_NONE, 0, nullptr}},
   };
 
-  GenerateTable(Table.data(), BaseOpTable, std::size(BaseOpTable));
+  GenerateTable(&Table.at(0), BaseOpTable, std::size(BaseOpTable));
   IR::InstallToTable(Table, IR::OpDispatch_BaseOpTable);
 
   return Table;
 }();
 
+void InitializeBaseTables(Context::OperatingMode Mode) {
+  static constexpr U8U8InfoStruct BaseOpTable_64[] = {
+    {0x06, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x0E, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x16, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x1E, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x27, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x2F, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x37, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+    {0x3F, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
+
+    // REX
+    {0x40, 16, X86InstInfo{"", TYPE_REX_PREFIX, FLAGS_NONE,        0, nullptr}},
+    {0x60, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                           0, nullptr}},
+    {0x63, 1, X86InstInfo{"MOVSXD", TYPE_INST, GenFlagsDstSize(SIZE_64BIT) | FLAGS_MODRM,                                                                         0, nullptr}},
+    {0x9A, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                           0, nullptr}},
+    {0xA0, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 8, nullptr}},
+    {0xA2, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, nullptr}},
+    {0xA1, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 8, nullptr}},
+    {0xA3, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, nullptr}},
+    {0xCE, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
+    {0xD4, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
+    // `L1OM` Larrabee instructions used this as an escape byte.
+    // FEX will never support this.
+    {0xD6, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
+    {0xEA, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                                      0, nullptr}},
+  };
+
+  static constexpr U8U8InfoStruct BaseOpTable_32[] = {
+    {0x06, 1, X86InstInfo{"PUSH ES",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS,            0, nullptr}},
+    {0x07, 1, X86InstInfo{"POP ES",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS,    0, nullptr}},
+    {0x0E, 1, X86InstInfo{"PUSH CS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS,            0, nullptr}},
+    {0x16, 1, X86InstInfo{"PUSH SS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS,            0, nullptr}},
+    {0x17, 1, X86InstInfo{"POP SS",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS,    0, nullptr}},
+    {0x1E, 1, X86InstInfo{"PUSH DS",  TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS,            0, nullptr}},
+    {0x1F, 1, X86InstInfo{"POP DS",   TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS,    0, nullptr}},
+    {0x27, 1, X86InstInfo{"DAA",      TYPE_INST, GenFlagsDstSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                   0, nullptr}},
+    {0x2F, 1, X86InstInfo{"DAS",      TYPE_INST, GenFlagsDstSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                   0, nullptr}},
+    {0x37, 1, X86InstInfo{"AAA",      TYPE_INST, GenFlagsDstSize(SIZE_16BIT) | FLAGS_SF_DST_RAX,                  0, nullptr}},
+    {0x3F, 1, X86InstInfo{"AAS",      TYPE_INST, GenFlagsDstSize(SIZE_16BIT) | FLAGS_SF_DST_RAX,                  0, nullptr}},
+
+    {0x40, 8, X86InstInfo{"INC",    TYPE_INST, FLAGS_SF_REX_IN_BYTE,                                              0, nullptr}},
+    {0x48, 8, X86InstInfo{"DEC",    TYPE_INST, FLAGS_SF_REX_IN_BYTE,                                              0, nullptr}},
+    {0x60, 1, X86InstInfo{"PUSHA",  TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                            0, nullptr}},
+    {0x61, 1, X86InstInfo{"POPA",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                            0, nullptr}},
+    {0x63, 1, X86InstInfo{"ARPL",   TYPE_INVALID, FLAGS_NONE,                                                     0, nullptr}},
+
+    {0x9A, 1, X86InstInfo{"CALLF",  TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
+    {0xA0, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET, 4, nullptr}},
+    {0xA2, 1, X86InstInfo{"MOV",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 4, nullptr}},
+    {0xA1, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_MEM_OFFSET,                               4, nullptr}},
+    {0xA3, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET,                               4, nullptr}},
+    {0xCE, 1, X86InstInfo{"INTO",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
+    {0xD4, 1, X86InstInfo{"AAM",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                    1, nullptr}},
+    {0xD5, 1, X86InstInfo{"AAD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                    1, nullptr}},
+    {0xD6, 1, X86InstInfo{"SALC",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX, 0, nullptr}},
+    {0xEA, 1, X86InstInfo{"JMPF",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
+  };
+
+  if (Mode == Context::MODE_64BIT) {
+    GenerateTable(&BaseOps.at(0), BaseOpTable_64, std::size(BaseOpTable_64));
+    IR::InstallToTable(BaseOps, IR::OpDispatch_BaseOpTable_64);
+  }
+  else {
+    GenerateTable(&BaseOps.at(0), BaseOpTable_32, std::size(BaseOpTable_32));
+    IR::InstallToTable(BaseOps, IR::OpDispatch_BaseOpTable_32);
+  }
+}
 }
 

FEXCore/Source/Interface/Core/X86Tables/DDDTables.cpp

@@ -13,48 +13,48 @@ $end_info$
 namespace FEXCore::X86Tables {
 using namespace InstFlags;
 
-constexpr std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> DDDNowOps = []() consteval {
+std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> DDDNowOps = []() consteval {
   std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> Table{};
   constexpr U8U8InfoStruct DDDNowOpTable[] = {
-    {0x0C, 1, X86InstInfo{"PI2FW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x0D, 1, X86InstInfo{"PI2FD",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x1C, 1, X86InstInfo{"PF2IW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x1D, 1, X86InstInfo{"PF2ID",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0x0C, 1, X86InstInfo{"PI2FW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x0D, 1, X86InstInfo{"PI2FD",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x1C, 1, X86InstInfo{"PF2IW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x1D, 1, X86InstInfo{"PF2ID",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
     // Inverse 3DNow! These two instructions are Geode product line specific
     // No CPUID for these, you're expected to read ID_CONFIG_MSR (1250h) bit 1
-    {0x86, 1, X86InstInfo{"PFRCPV",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x87, 1, X86InstInfo{"PFRSQRTV", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0x86, 1, X86InstInfo{"PFRCPV",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x87, 1, X86InstInfo{"PFRSQRTV", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0x8A, 1, X86InstInfo{"PFNACC",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x8E, 1, X86InstInfo{"PFPNACC",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0x8A, 1, X86InstInfo{"PFNACC",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x8E, 1, X86InstInfo{"PFPNACC",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0x90, 1, X86InstInfo{"PFCMPGE",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x94, 1, X86InstInfo{"PFMIN",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x96, 1, X86InstInfo{"PFRCP",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x97, 1, X86InstInfo{"PFRSQRT",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0x90, 1, X86InstInfo{"PFCMPGE",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x94, 1, X86InstInfo{"PFMIN",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x96, 1, X86InstInfo{"PFRCP",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x97, 1, X86InstInfo{"PFRSQRT",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0x9A, 1, X86InstInfo{"PFSUB",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0x9E, 1, X86InstInfo{"PFADD",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0x9A, 1, X86InstInfo{"PFSUB",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0x9E, 1, X86InstInfo{"PFADD",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0xA0, 1, X86InstInfo{"PFCMPGT",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xA4, 1, X86InstInfo{"PFMAX",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xA6, 1, X86InstInfo{"PFRCPIT1", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xA7, 1, X86InstInfo{"PFRSQIT1", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0xA0, 1, X86InstInfo{"PFCMPGT",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xA4, 1, X86InstInfo{"PFMAX",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xA6, 1, X86InstInfo{"PFRCPIT1", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xA7, 1, X86InstInfo{"PFRSQIT1", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0xAA, 1, X86InstInfo{"PFSUBR",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xAE, 1, X86InstInfo{"PFACC",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0xAA, 1, X86InstInfo{"PFSUBR",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xAE, 1, X86InstInfo{"PFACC",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0xB0, 1, X86InstInfo{"PFCMPEQ",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xB4, 1, X86InstInfo{"PFMUL",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xB6, 1, X86InstInfo{"PFRCPIT2", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xB7, 1, X86InstInfo{"PMULHRW",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0xB0, 1, X86InstInfo{"PFCMPEQ",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xB4, 1, X86InstInfo{"PFMUL",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xB6, 1, X86InstInfo{"PFRCPIT2", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xB7, 1, X86InstInfo{"PMULHRW",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
 
-    {0xBB, 1, X86InstInfo{"PSWAPD",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {0xBF, 1, X86InstInfo{"PAVGUSB",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
+    {0xBB, 1, X86InstInfo{"PSWAPD",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {0xBF, 1, X86InstInfo{"PAVGUSB",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
   };
 
-  GenerateTable(Table.data(), DDDNowOpTable, std::size(DDDNowOpTable));
+  GenerateTable(&Table.at(0), DDDNowOpTable, std::size(DDDNowOpTable));
 
   IR::InstallToTable(Table, IR::OpDispatch_DDDTable);
   return Table;

FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp

@@ -13,7 +13,7 @@ $end_info$
 
 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-constexpr std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> H0F38TableOps = []() consteval {
+std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> H0F38TableOps = []() consteval {
   std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> Table{};
 
 #define OPD(prefix, opcode) (((prefix) << 8) | opcode)
@@ -23,103 +23,103 @@ constexpr std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> H0F38TableOps = []() con
   constexpr uint16_t PF_38_F3   = (1U << 2);
 
   constexpr U16U8InfoStruct H0F38Table[] = {
-    {OPD(PF_38_NONE, 0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x01), 1, X86InstInfo{"PHADDW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x01), 1, X86InstInfo{"PHADDW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x02), 1, X86InstInfo{"PHADDD",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x02), 1, X86InstInfo{"PHADDD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x03), 1, X86InstInfo{"PHADDSW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x03), 1, X86InstInfo{"PHADDSW",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x04), 1, X86InstInfo{"PMADDUBSW",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x04), 1, X86InstInfo{"PMADDUBSW",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x05), 1, X86InstInfo{"PHSUBW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x05), 1, X86InstInfo{"PHSUBW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x06), 1, X86InstInfo{"PHSUBD",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x06), 1, X86InstInfo{"PHSUBD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x07), 1, X86InstInfo{"PHSUBSW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x07), 1, X86InstInfo{"PHSUBSW",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x08), 1, X86InstInfo{"PSIGNB",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x08), 1, X86InstInfo{"PSIGNB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x09), 1, X86InstInfo{"PSIGNW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x09), 1, X86InstInfo{"PSIGNW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x0A), 1, X86InstInfo{"PSIGND",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x0A), 1, X86InstInfo{"PSIGND",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_NONE, 0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x01), 1, X86InstInfo{"PHADDW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x01), 1, X86InstInfo{"PHADDW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x02), 1, X86InstInfo{"PHADDD",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x02), 1, X86InstInfo{"PHADDD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x03), 1, X86InstInfo{"PHADDSW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x03), 1, X86InstInfo{"PHADDSW",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x04), 1, X86InstInfo{"PMADDUBSW",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x04), 1, X86InstInfo{"PMADDUBSW",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x05), 1, X86InstInfo{"PHSUBW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x05), 1, X86InstInfo{"PHSUBW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x06), 1, X86InstInfo{"PHSUBD",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x06), 1, X86InstInfo{"PHSUBD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x07), 1, X86InstInfo{"PHSUBSW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x07), 1, X86InstInfo{"PHSUBSW",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x08), 1, X86InstInfo{"PSIGNB",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x08), 1, X86InstInfo{"PSIGNB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x09), 1, X86InstInfo{"PSIGNW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x09), 1, X86InstInfo{"PSIGNW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x0A), 1, X86InstInfo{"PSIGND",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x0A), 1, X86InstInfo{"PSIGND",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0}},
-    {OPD(PF_38_66,   0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
+    {OPD(PF_38_66,   0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x37), 1, X86InstInfo{"PCMPGTQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x37), 1, X86InstInfo{"PCMPGTQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_NONE, 0xC8), 1, X86InstInfo{"SHA1NEXTE",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0xC9), 1, X86InstInfo{"SHA1MSG1",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0xCA), 1, X86InstInfo{"SHA1MSG2",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_NONE, 0xC8), 1, X86InstInfo{"SHA1NEXTE",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xC9), 1, X86InstInfo{"SHA1MSG1",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xCA), 1, X86InstInfo{"SHA1MSG2",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_NONE, 0xCB), 1, X86InstInfo{"SHA256RNDS2", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0xCC), 1, X86InstInfo{"SHA256MSG1",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_NONE, 0xCD), 1, X86InstInfo{"SHA256MSG2",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_NONE, 0xCB), 1, X86InstInfo{"SHA256RNDS2", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xCC), 1, X86InstInfo{"SHA256MSG1",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xCD), 1, X86InstInfo{"SHA256MSG2",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0xDB), 1, X86InstInfo{"AESIMC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0xDC), 1, X86InstInfo{"AESENC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0xDD), 1, X86InstInfo{"AESENCLAST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0xDE), 1, X86InstInfo{"AESDEC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
-    {OPD(PF_38_66,   0xDF), 1, X86InstInfo{"AESDECLAST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0}},
+    {OPD(PF_38_66,   0xDB), 1, X86InstInfo{"AESIMC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0xDC), 1, X86InstInfo{"AESENC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0xDD), 1, X86InstInfo{"AESENCLAST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0xDE), 1, X86InstInfo{"AESDEC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0xDF), 1, X86InstInfo{"AESDECLAST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_NONE, 0xF0), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY, 0}},
-    {OPD(PF_38_NONE, 0xF1), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0}},
+    {OPD(PF_38_NONE, 0xF0), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xF1), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
 
-    {OPD(PF_38_66, 0xF0), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY, 0}},
-    {OPD(PF_38_66, 0xF1), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0}},
+    {OPD(PF_38_66, 0xF0), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
+    {OPD(PF_38_66, 0xF1), 1, X86InstInfo{"MOVBE",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
 
-    {OPD(PF_38_F2,   0xF0), 1, X86InstInfo{"CRC32",      TYPE_INST, GenFlagsSizes(SIZE_DEF, SIZE_8BIT) | FLAGS_MODRM, 0}},
-    {OPD(PF_38_F2,   0xF1), 1, X86InstInfo{"CRC32",      TYPE_INST, FLAGS_MODRM, 0}},
-    {OPD(PF_38_66 | PF_38_F2,   0xF0), 1, X86InstInfo{"CRC32",      TYPE_INST, GenFlagsSizes(SIZE_DEF, SIZE_8BIT) | FLAGS_MODRM, 0}},
-    {OPD(PF_38_66 | PF_38_F2,   0xF1), 1, X86InstInfo{"CRC32",      TYPE_INST, FLAGS_MODRM, 0}},
+    {OPD(PF_38_F2,   0xF0), 1, X86InstInfo{"CRC32",      TYPE_INST, GenFlagsSizes(SIZE_DEF, SIZE_8BIT) | FLAGS_MODRM, 0, nullptr}},
+    {OPD(PF_38_F2,   0xF1), 1, X86InstInfo{"CRC32",      TYPE_INST, FLAGS_MODRM, 0, nullptr}},
+    {OPD(PF_38_66 | PF_38_F2,   0xF0), 1, X86InstInfo{"CRC32",      TYPE_INST, GenFlagsSizes(SIZE_DEF, SIZE_8BIT) | FLAGS_MODRM, 0, nullptr}},
+    {OPD(PF_38_66 | PF_38_F2,   0xF1), 1, X86InstInfo{"CRC32",      TYPE_INST, FLAGS_MODRM, 0, nullptr}},
 
-    {OPD(PF_38_66,   0xF6), 1, X86InstInfo{"ADCX",       TYPE_INST, FLAGS_MODRM | FLAGS_NO_OVERLAY66, 0}},
-    {OPD(PF_38_F3,   0xF6), 1, X86InstInfo{"ADOX",       TYPE_INST, FLAGS_MODRM, 0}},
+    {OPD(PF_38_66,   0xF6), 1, X86InstInfo{"ADCX",       TYPE_INST, FLAGS_MODRM | FLAGS_NO_OVERLAY66, 0, nullptr}},
+    {OPD(PF_38_F3,   0xF6), 1, X86InstInfo{"ADOX",       TYPE_INST, FLAGS_MODRM, 0, nullptr}},
   };
 #undef OPD
 
-  GenerateTable(Table.data(), H0F38Table, std::size(H0F38Table));
+  GenerateTable(&Table.at(0), H0F38Table, std::size(H0F38Table));
 
   IR::InstallToTable(Table, IR::OpDispatch_H0F38Table);
   return Table;

FEXCore/Source/Interface/Core/X86Tables/H0F3ATables.cpp

@@ -19,82 +19,71 @@ using namespace InstFlags;
 constexpr uint16_t PF_3A_NONE = 0;
 constexpr uint16_t PF_3A_66   = 1;
 
-enum H0F3A_LUT {
-  ENTRY_1_3A_66_16,
-  ENTRY_1_3A_66_22,
-  ENTRY_MAX,
-};
-
-constexpr std::array<X86InstInfo[2], ENTRY_MAX> H0F3A_ArchSelect_LUT = {{
-  // ENTRY_1_3A_66_16
-  {
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-    {"PEXTRQ",          TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::PExtrOp, IR::OpSize::i64Bit> }},
-  },
-  // ENTRY_1_3A_66_22
-  {
-    {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } },
-    {"PINSRQ",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, { .OpDispatch = &IR::OpDispatchBuilder::PINSROp<IR::OpSize::i64Bit> }},
-  },
-}};
-
-constexpr std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> H0F3ATableOps = []() consteval {
+std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> H0F3ATableOps = []() consteval {
   std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> Table{};
   auto TableGen = []<uint16_t REX>() consteval {
     constexpr U16U8InfoStruct Table[] = {
-      {OPD(REX, PF_3A_NONE, 0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1}},
-      {OPD(REX, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1}},
-      {OPD(REX, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1}},
-      {OPD(REX, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1}},
-      {OPD(REX, PF_3A_66,   0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_NONE, 0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-      {OPD(REX, PF_3A_66,   0x14), 1, X86InstInfo{"PEXTRB",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x15), 1, X86InstInfo{"PEXTRW",          TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_66,   0x14), 1, X86InstInfo{"PEXTRB",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x15), 1, X86InstInfo{"PEXTRW",          TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-      {OPD(REX, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1}},
-      {OPD(REX, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1}},
-      {OPD(REX, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x44), 1, X86InstInfo{"PCLMULQDQ",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x44), 1, X86InstInfo{"PCLMULQDQ",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-      {OPD(REX, PF_3A_66,   0x60), 1, X86InstInfo{"PCMPESTRM",       TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x61), 1, X86InstInfo{"PCMPESTRI",       TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x62), 1, X86InstInfo{"PCMPISTRM",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
-      {OPD(REX, PF_3A_66,   0x63), 1, X86InstInfo{"PCMPISTRI",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_66,   0x60), 1, X86InstInfo{"PCMPESTRM",       TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x61), 1, X86InstInfo{"PCMPESTRI",       TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x62), 1, X86InstInfo{"PCMPISTRM",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+      {OPD(REX, PF_3A_66,   0x63), 1, X86InstInfo{"PCMPISTRI",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-      {OPD(REX, PF_3A_NONE, 0xCC), 1, X86InstInfo{"SHA1RNDS4",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_NONE, 0xCC), 1, X86InstInfo{"SHA1RNDS4",       TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-      {OPD(REX, PF_3A_66,   0xDF), 1, X86InstInfo{"AESKEYGENASSIST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1}},
+      {OPD(REX, PF_3A_66,   0xDF), 1, X86InstInfo{"AESKEYGENASSIST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
     };
     return std::to_array(Table);
   };
   constexpr auto H0F3ATable_IgnoresREX0 = TableGen.template operator()<0>();
   constexpr auto H0F3ATable_IgnoresREX1 = TableGen.template operator()<1>();
 
-  GenerateTable(Table.data(), H0F3ATable_IgnoresREX0.data(), H0F3ATable_IgnoresREX0.size());
-  GenerateTable(Table.data(), H0F3ATable_IgnoresREX1.data(), H0F3ATable_IgnoresREX1.size());
+  GenerateTable(&Table.at(0), &H0F3ATable_IgnoresREX0.at(0), H0F3ATable_IgnoresREX0.size());
+  GenerateTable(&Table.at(0), &H0F3ATable_IgnoresREX1.at(0), H0F3ATable_IgnoresREX1.size());
 
-  constexpr U16U8InfoStruct TableNeedsREX0[] = {
-    {OPD(0, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRD",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1}},
-    {OPD(0, PF_3A_66,   0x22), 1, X86InstInfo{"PINSRD",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1}},
+  constexpr U16U8InfoStruct TableNeedsREX[] = {
+    {OPD(0, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRD",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x22), 1, X86InstInfo{"PINSRD",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
   };
-  GenerateTable(Table.data(), TableNeedsREX0, std::size(TableNeedsREX0));
-
-  constexpr U16U8InfoStruct TableNeedsREX1[] = {
-    {OPD(1, PF_3A_66,   0x16), 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = H0F3A_ArchSelect_LUT[ENTRY_1_3A_66_16] }}},
-    {OPD(1, PF_3A_66,   0x22), 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = H0F3A_ArchSelect_LUT[ENTRY_1_3A_66_22] }}},
-  };
-  GenerateTable(Table.data(), TableNeedsREX1, std::size(TableNeedsREX1));
+  GenerateTable(&Table.at(0), TableNeedsREX, std::size(TableNeedsREX));
 
   IR::InstallToTable(Table, IR::OpDispatch_H0F3ATableIgnoreREX);
   IR::InstallToTable(Table, IR::OpDispatch_H0F3ATableNeedsREX0);
 
   return Table;
 }();
+
+void InitializeH0F3ATables(Context::OperatingMode Mode) {
+  static constexpr U16U8InfoStruct H0F3ATable_64[] = {
+    {OPD(1, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRQ",          TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(1, PF_3A_66,   0x22), 1, X86InstInfo{"PINSRQ",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
+  };
+
+#undef OPD
+
+  if (Mode == Context::MODE_64BIT) {
+    GenerateTable(&H0F3ATableOps.at(0), H0F3ATable_64, std::size(H0F3ATable_64));
+    IR::InstallToTable(H0F3ATableOps, IR::OpDispatch_H0F3ATable_64);
+  }
+}
 }