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FEX-2609_1
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FEX-2508.1
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93c428ae53 | ||
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5836309525 | ||
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43092ce48b | ||
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e5d51a20b2 |
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@@ -149,8 +149,20 @@ private:
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bool HasSource(IROp_Header* I, PhysicalRegister Reg) {
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for (auto s = 0; s < IR::GetRAArgs(I->Op); ++s) {
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if (I->Args[s].IsImmediate() && PhysicalRegister(I->Args[s]) == Reg) {
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return true;
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if (I->Args[s].IsImmediate()) {
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// When spilling for a destination, we'll see register sources
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if (PhysicalRegister(I->Args[s]) == Reg) {
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return true;
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}
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} else {
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// When spilling for SRA correctness, we'll see SSA sources. This is
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// pretty obscure.
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auto V = I->Args[s];
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V.ClearKill();
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if (IsValidArg(V) && SSAToReg[V.ID().Value] == Reg) {
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return true;
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}
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}
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}
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@@ -230,11 +242,11 @@ private:
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const uint8_t NumArgs = IR::GetRAArgs(IROp->Op);
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for (int i = NumArgs - 1; i >= 0; --i) {
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auto& Arg = IROp->Args[i];
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Arg.ClearKill();
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auto V = IROp->Args[i];
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V.ClearKill();
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if (!Arg.IsInvalid()) {
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const uint32_t Index = Arg.ID().Value;
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if (IsValidArg(V)) {
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const uint32_t Index = V.ID().Value;
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SourcesNextUses.push_back(NextUses[Index]);
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NextUses[Index] = IP;
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@@ -684,13 +696,22 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) {
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//
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// This happens before freeing killed sources, since we need all sources in
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// the register file simultaneously.
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//
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// Also update next-use info, again only relevant if we've spilled.
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if (AnySpilledBeforeThisInstruction) {
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for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
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if (!IsValidArg(IROp->Args[s])) {
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auto V = IROp->Args[s];
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V.ClearKill();
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if (!IsValidArg(V)) {
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continue;
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}
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Ref Old = IR->GetNode(IROp->Args[s]);
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Ref Old = IR->GetNode(V);
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SourceIndex--;
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LOGMAN_THROW_A_FMT(SourceIndex >= 0, "Consistent source count");
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NextUses[V.ID().Value] = SourcesNextUses[SourceIndex];
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if (!IsInRegisterFile(Old)) {
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IREmit->SetWriteCursorBefore(CodeNode);
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@@ -702,50 +723,26 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) {
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RemapReg(Old, PhysicalRegister(Fill));
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}
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}
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}
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for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
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if (IROp->Args[s].IsInvalid()) {
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continue;
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}
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Ref Node = IR->GetNode(IROp->Args[s]);
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auto ID = IR->GetID(Node).Value;
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auto Reg = SSAToReg[ID];
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SourceIndex--;
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LOGMAN_THROW_A_FMT(SourceIndex >= 0, "Consistent source count");
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if (!Reg.IsInvalid()) {
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IROp->Args[s].SetImmediate(Reg.Raw);
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if (!SourcesNextUses[SourceIndex]) {
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LOGMAN_THROW_A_FMT(IsInRegisterFile(Node), "sources in file");
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FreeReg(Reg);
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}
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}
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NextUses[ID] = SourcesNextUses[SourceIndex];
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for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
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if (IROp->Args[s].IsInvalid()) {
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continue;
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}
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} else {
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for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
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if (IROp->Args[s].IsInvalid()) {
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continue;
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bool Kill = IROp->Args[s].HasKill();
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IROp->Args[s].ClearKill();
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Ref Node = IR->GetNode(IROp->Args[s]);
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auto ID = IR->GetID(Node).Value;
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auto Reg = SSAToReg[ID];
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if (!Reg.IsInvalid()) {
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if (Kill) {
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LOGMAN_THROW_A_FMT(IsInRegisterFile(Node), "sources in file");
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FreeReg(Reg);
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}
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bool Kill = IROp->Args[s].HasKill();
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IROp->Args[s].ClearKill();
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Ref Node = IR->GetNode(IROp->Args[s]);
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auto ID = IR->GetID(Node).Value;
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auto Reg = SSAToReg[ID];
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if (!Reg.IsInvalid()) {
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if (Kill) {
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LOGMAN_THROW_A_FMT(IsInRegisterFile(Node), "sources in file");
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FreeReg(Reg);
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}
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IROp->Args[s].SetImmediate(Reg.Raw);
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}
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IROp->Args[s].SetImmediate(Reg.Raw);
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}
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}
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@@ -1,4 +1,4 @@
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# FEX-2508
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# FEX-2508.1
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## FEXCore
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See [FEXCore/Readme.md](../FEXCore/Readme.md) for more details
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@@ -0,0 +1,56 @@
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%ifdef CONFIG
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{
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}
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%endif
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vblendps ymm3, ymm12, ymm9, 0xcc
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vperm2f128 ymm12, ymm1, ymm2, 0x20
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vmovups [rel .data_result + 0], ymm12
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vunpckhps ymm14, ymm4, ymm5
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vblendps ymm4, ymm8, ymm0, 0xcc
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vunpckhps ymm15, ymm6, ymm7
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vperm2f128 ymm7, ymm3, ymm4, 0x20
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vmovups [rel .data_result + 32], ymm7
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vshufps ymm5, ymm10, ymm13, 0x4e
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vblendps ymm6, ymm5, ymm13, 0xcc
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vshufps ymm13, ymm14, ymm15, 0x4e
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vblendps ymm10, ymm10, ymm5, 0xcc
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vblendps ymm14, ymm14, ymm13, 0xcc
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vperm2f128 ymm8, ymm10, ymm14, 0x20
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vmovups [rel .data_result + (32 * 2)], ymm8
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vblendps ymm15, ymm13, ymm15, 0xcc
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vperm2f128 ymm13, ymm6, ymm15, 0x20
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vmovups [rel .data_result + (32 * 3)], ymm13
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vperm2f128 ymm9, ymm1, ymm2, 0x31
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vperm2f128 ymm11, ymm3, ymm4, 0x31
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vmovups [rel .data_result + (32 * 4)], ymm9
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vperm2f128 ymm14, ymm10, ymm14, 0x31
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vperm2f128 ymm15, ymm6, ymm15, 0x31
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vmovups [rel .data_result + (32 * 5)], ymm11
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vmovups [rel .data_result + (32 * 6)], ymm14
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vmovups [rel .data_result + (32 * 7)], ymm15
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vmovdqa ymm0, [rel .data_stack + (32 * 0)]
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vpaddd ymm1, ymm0, [rel .data_stack + (32 * 1)]
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vmovdqa [rel .data_stack + (32 * 1)], ymm1
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vpxor ymm0, ymm0, [rel .data]
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vpxor ymm2, ymm1, [rel .data + 32]
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hlt
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align 4096
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.data:
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dq 0, 0, 0, 0, 0, 0
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dq 0, 0, 0, 0, 0, 0
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.data_stack:
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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.data_result:
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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dq 0, 0, 0, 0
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