Docs: Update for release FEX-2509.1

This takes an f80 as input and returns an f32. A copy-paste error had
this truncating the input float if !TMP_ABIARGS.

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -757,7 +757,7 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 
     ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
     if (!TMP_ABIARGS) {
-      fmov(VABI1.D(), VTMP1.D());
+      mov(VABI1.Q(), VTMP1.Q());
     }
 
     mov(ARMEmitter::XReg::x1, STATE);

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -273,8 +273,9 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
   default:
     IROp = FEXCore::IR::IROps::OP_LAST;
     AtomicIROp = FEXCore::IR::IROps::OP_LAST;
-    LOGMAN_MSG_A_FMT("Unknown ALU Op: 0x{:x}", Op->OP);
-    break;
+    LogMan::Msg::EFmt("Unknown ALU Op: 0x{:x}", Op->OP);
+    DecodeFailure = true;
+    return;
   };
 #undef OPD
 

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -1179,13 +1179,15 @@ public:
     _StoreContext(Size, Class, Value, Offset);
   }
 
-  void FlushRegisterCache(bool SRAOnly = false) {
+  void FlushRegisterCache(bool SRAOnly = false, bool MMXOnly = false) {
     // At block boundaries, fix up the carry flag.
     if (!SRAOnly) {
       RectifyCarryInvert(CFInvertedABI);
     }
 
-    CalculateDeferredFlags();
+    if (!MMXOnly) {
+      CalculateDeferredFlags();
+    }
 
     const auto GPRSize = GetGPROpSize();
     const auto VectorSize = GetGuestVectorLength();
@@ -1207,6 +1209,11 @@ public:
       Bits &= Mask;
     }
 
+    if (MMXOnly) {
+      Mask &= ((1ull << (MM7Index - MM0Index + 1)) - 1) << MM0Index;
+      Bits &= Mask;
+    }
+
     while (Bits != 0) {
       uint32_t Index = 63 - std::countl_zero(Bits);
       Ref Value = RegCache.Value[Index];
@@ -2356,10 +2363,12 @@ private:
 
   void ChgStateMMX_X87() override {
     LOGMAN_THROW_A_FMT(MMXState == MMXState_MMX, "Expected state to be MMX");
+    // The opcode dispatcher register cache is used for MMX, but the x87 pass register cache is used for x87, spill to
+    // context to ensure coherence.
+    FlushRegisterCache(false, true);
     // We explicitly initialize to x87 state in StartNewBlock.
     // So if we ever change this to do something else, we need to
     // make sure that we consider if we need to explicitly set it there.
-    FlushRegisterCache();
     MMXState = MMXState_X87;
   }
 

Source/Windows/WOW64/Module.cpp

@@ -595,16 +595,17 @@ void BTCpuProcessInit() {
 void BTCpuProcessTerm(HANDLE Handle, BOOL After, ULONG Status) {}
 
 void BTCpuThreadInit() {
+  static constexpr size_t DefaultWow64CS {4};
   std::scoped_lock Lock(ThreadCreationMutex);
   FEX::Windows::InitCRTThread();
   auto* Thread = CTX->CreateThread(0, 0);
 
   // Default segment setup.
   auto Frame = Thread->CurrentFrame;
-  auto NewSegments = new FEXCore::Core::CPUState::gdt_segment[32];
+  auto NewSegments = new FEXCore::Core::CPUState::gdt_segment[32]();
 
   // Setup initial code-segment GDT
-  auto& GDT = NewSegments[FEXCore::Core::CPUState::DEFAULT_USER_CS];
+  auto& GDT = NewSegments[DefaultWow64CS];
   FEXCore::Core::CPUState::SetGDTBase(&GDT, 0);
   FEXCore::Core::CPUState::SetGDTLimit(&GDT, 0xF'FFFFU);
   GDT.L = 0; // L = Long Mode = 32-bit
@@ -614,7 +615,7 @@ void BTCpuThreadInit() {
   // TODO: LDTs are currently unsupported, mirror them to GDT.
   Frame->State.segment_arrays[FEXCore::Core::CPUState::SEGMENT_ARRAY_INDEX_LDT] = &NewSegments[0];
 
-  Frame->State.cs_idx = FEXCore::Core::CPUState::DEFAULT_USER_CS << 3;
+  Frame->State.cs_idx = DefaultWow64CS << 3;
   Frame->State.cs_cached = FEXCore::Core::CPUState::CalculateGDTBase(GDT);
 
   FEX::Windows::CallRetStack::InitializeThread(Thread);

docs/SourceOutline.md

@@ -1,4 +1,4 @@
-# FEX-2509
+# FEX-2509.1
 
 ## FEXCore
 See [FEXCore/Readme.md](../FEXCore/Readme.md) for more details

unittests/ASM/FEX_bugs/X87MMXNZCV.asm

@@ -0,0 +1,13 @@
+%ifdef CONFIG
+{
+  "RegData": {},
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1" }
+}
+%endif
+
+; FEX had a bug where a mmx->x87 switch would flush the saved NZCV value used for ftst, causing a crash in RA
+
+movq mm0, mm1 ; enters mmx state
+ftst ; enters x87 state
+
+hlt