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Author SHA1 Message Date
Ryan Houdek ea20429351 Docs: Update for release FEX-2507.1 2025-07-11 11:37:44 -07:00
Alyssa Rosenzweig 91828efa7a JIT: fix divisor masking
oversight. should fix Steam.

Fixes: de4becc26 ("OpcodeDispatcher: mask certain divisors")
Closes: #4652
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2025-07-11 11:34:45 -07:00
Billy Laws cce605d5e0 PoolBufferWithTimedRetirement: Unclaim in dtor
Buffers are tied to the lifetime of their owned flag, and as that
is a member of PoolBufferWithTimedRetirement we must always unclaim here.

Avoids the need to manually remember this quirk (which was forgot for the
temporary compilation buffer in JIT.cpp) at every use-site.
2025-07-11 11:34:07 -07:00
6 changed files with 11 additions and 12 deletions

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@@ -69,10 +69,6 @@ Decoder::Decoder(FEXCore::Context::ContextImpl* ctx)
, OSABI {ctx->SyscallHandler ? ctx->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN}
, PoolObject {ctx->FrontendAllocator, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize} {}
Decoder::~Decoder() {
PoolObject.UnclaimBuffer();
}
uint8_t Decoder::ReadByte() {
uint8_t Byte = InstStream[InstructionSize];
LOGMAN_THROW_A_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
-1
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@@ -34,7 +34,6 @@ public:
};
Decoder(FEXCore::Context::ContextImpl* ctx);
~Decoder();
void DecodeInstructionsAtEntry(const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst,
std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);
+6 -2
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@@ -969,11 +969,15 @@ DEF_OP(UDiv) {
break;
}
case IR::OpSize::i32Bit: {
// We need to mask divisor if we have Upper bits, since the frontend does
// not on the hope that we can optimize to use the path above.
mov(ARMEmitter::Size::i32Bit, TMP2, Divisor);
// TODO: 32-bit operation should be guaranteed not to leave garbage in the upper bits.
mov(EmitSize, TMP1, Lower);
bfi(EmitSize, TMP1, Upper, 32, 32);
udiv(EmitSize, Quotient, TMP1, Divisor);
msub(EmitSize, Remainder, Quotient, Divisor, TMP1);
udiv(EmitSize, Quotient, TMP1, TMP2);
msub(EmitSize, Remainder, Quotient, TMP2, TMP1);
break;
}
case IR::OpSize::i64Bit: {
@@ -127,10 +127,6 @@ public:
PoolObject.ReownOrClaimBuffer();
}
~DualIntrusiveAllocatorThreadPool() {
PoolObject.UnclaimBuffer();
}
void ReownOrClaimBuffer() {
Data = PoolObject.ReownOrClaimBuffer();
List = Data + MemorySize;
@@ -445,6 +445,10 @@ public:
: ThreadAllocator {Allocator}
, Size {Size} {}
~PoolBufferWithTimedRetirement() {
UnclaimBuffer();
}
/**
* @brief Return the owned buffer or allocate another one from the `Allocator`
*
+1 -1
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@@ -1,4 +1,4 @@
# FEX-2507
# FEX-2507.1
## FEXCore
See [FEXCore/Readme.md](../FEXCore/Readme.md) for more details