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Commits
| Author | SHA1 | Date | |
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 Ryan Houdek
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8991ecb67b | ||
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Tony Wasserka
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91edf6b333 |
No files matched your search
@@ -730,7 +730,7 @@ uint64_t FileManager::Readlinkat(int dirfd, const char *pathname, char *buf, siz
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}
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}
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if (SupportsProcFSInterpreter) {
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if (!SupportsProcFSInterpreter) {
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char PidSelfPath[50];
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snprintf(PidSelfPath, 50, "/proc/%i/exe", CurrentPID);
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+2
-172
@@ -1,176 +1,6 @@
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# FEX-2309
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# FEX-2309.1
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## FEXCore
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See [FEXCore/Readme.md](../FEXCore/Readme.md) for more details
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### Glossary
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- Splatter: a code generator backend that concaternates configurable macros instead of doing isel
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- IR: Intermediate Representation, our high-level opcode representation, loosely modeling arm64
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- SSA: Single Static Assignment, a form of representing IR in memory
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- Basic Block: A block of instructions with no control flow, terminated by control flow
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- Fragment: A Collection of basic blocks, possibly an entire guest function or a subset of it
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### backend
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IR to host code generation
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#### arm64
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- [ALUOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp)
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- [Arm64Relocations.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp): relocation logic of the arm64 splatter backend
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- [AtomicOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp)
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- [BranchOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp)
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- [ConversionOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp)
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- [EncryptionOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp)
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- [FlagOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/FlagOps.cpp)
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- [JIT.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp): Main glue logic of the arm64 splatter backend
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- [JITClass.h](../FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h)
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- [MemoryOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp)
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- [MiscOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp)
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- [MoveOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp)
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- [VectorOps.cpp](../FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp)
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#### interpreter
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- [ALUOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp)
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- [AtomicOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/AtomicOps.cpp)
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- [BranchOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp)
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- [ConversionOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp)
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- [EncryptionOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/EncryptionOps.cpp)
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- [F80Ops.cpp](../FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp)
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- [FlagOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/FlagOps.cpp)
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- [MemoryOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp)
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- [MiscOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/MiscOps.cpp)
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- [MoveOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/MoveOps.cpp)
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- [VectorOps.cpp](../FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp)
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#### shared
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- [CPUBackend.h](../FEXCore/include/FEXCore/Core/CPUBackend.h)
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#### x86-64
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- [ALUOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp)
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- [AtomicOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp)
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- [BranchOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp)
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- [ConversionOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp)
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- [EncryptionOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp)
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- [FlagOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp)
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- [JIT.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp): Main glue logic of the x86-64 splatter backend
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- [JITClass.h](../FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h)
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- [MemoryOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp)
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- [MiscOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp)
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- [MoveOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp)
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- [VectorOps.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp)
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- [x64Relocations.cpp](../FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp): relocation logic of the x86-64 splatter backend
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### frontend
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#### x86-meta-blocks
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- [Frontend.cpp](../FEXCore/Source/Interface/Core/Frontend.cpp): Extracts instruction & block meta info, frontend multiblock logic
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#### x86-tables
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Metadata that drives the frontend x86/64 decoding
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- [BaseTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp)
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- [DDDTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/DDDTables.cpp)
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- [EVEXTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/EVEXTables.cpp)
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- [H0F38Tables.cpp](../FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp)
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- [H0F3ATables.cpp](../FEXCore/Source/Interface/Core/X86Tables/H0F3ATables.cpp)
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- [PrimaryGroupTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp)
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- [SecondaryGroupTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp)
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- [SecondaryModRMTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/SecondaryModRMTables.cpp)
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- [SecondaryTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp)
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- [VEXTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp)
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- [X86Tables.h](../FEXCore/Source/Interface/Core/X86Tables/X86Tables.h)
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- [X87Tables.cpp](../FEXCore/Source/Interface/Core/X86Tables/X87Tables.cpp)
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- [XOPTables.cpp](../FEXCore/Source/Interface/Core/X86Tables/XOPTables.cpp)
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- [X86Tables.cpp](../FEXCore/Source/Interface/Core/X86Tables.cpp)
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#### x86-to-ir
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- [Crypto.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp): Handles x86/64 Crypto instructions to IR
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- [Flags.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp): Handles x86/64 flag generation
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- [Vector.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp): Handles x86/64 Vector instructions to IR
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- [X87.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp): Handles x86/64 x87 to IR
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- [X87F64.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp): Handles x86/64 x87 to IR
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- [OpcodeDispatcher.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp): Handles x86/64 ops to IR, no-pf opt, local-flags opt
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### glue
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Logic that binds various parts together
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#### block-database
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- [LookupCache.cpp](../FEXCore/Source/Interface/Core/LookupCache.cpp): Stores information about blocks, and provides C++ implementations to lookup the blocks
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#### driver
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Emulation mainloop related glue logic
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- [Core.cpp](../FEXCore/Source/Interface/Core/Core.cpp): Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispatcher and provides the Execution loop entrypoint
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#### gdbserver
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- [GdbServer.cpp](../FEXCore/Source/Interface/Core/GdbServer.cpp): Provides a gdb interface to the guest state
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- [GdbServer.h](../FEXCore/Source/Interface/Core/GdbServer.h)
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#### log-manager
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- [LogManager.cpp](../FEXCore/Source/Utils/LogManager.cpp)
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#### thunks
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FEXCore side of thunks: Registration, Lookup
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- [Thunks.cpp](../FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp)
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- [Thunks.h](../FEXCore/Source/Interface/HLE/Thunks/Thunks.h)
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#### x86-guest-code
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- [X86HelperGen.cpp](../FEXCore/Source/Interface/Core/X86HelperGen.cpp): Guest-side assembly helpers used by the backends
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- [X86HelperGen.h](../FEXCore/Source/Interface/Core/X86HelperGen.h)
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### ir
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#### debug
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- [IRDumperPass.cpp](../FEXCore/Source/Interface/IR/Passes/IRDumperPass.cpp): Prints IR
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#### dumper
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IR -> Text
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- [IRDumper.cpp](../FEXCore/Source/Interface/IR/IRDumper.cpp)
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#### emitter
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C++ Functions to generate IR. See IR.json for spec.
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- [IREmitter.cpp](../FEXCore/Source/Interface/IR/IREmitter.cpp)
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#### opts
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IR to IR Optimization
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- [PassManager.cpp](../FEXCore/Source/Interface/IR/PassManager.cpp): Defines which passes are run, and runs them
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- [PassManager.h](../FEXCore/Source/Interface/IR/PassManager.h)
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- [ConstProp.cpp](../FEXCore/Source/Interface/IR/Passes/ConstProp.cpp): ConstProp, ZExt elim, addressgen coalesce, const pooling, fcmp reduction, const inlining
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- [DeadCodeElimination.cpp](../FEXCore/Source/Interface/IR/Passes/DeadCodeElimination.cpp)
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- [DeadContextStoreElimination.cpp](../FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp): Transforms ContextLoad/Store to temporaries, similar to mem2reg
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- [DeadStoreElimination.cpp](../FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp): Cross block store-after-store elimination
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- [IRCompaction.cpp](../FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp): Sorts the ssa storage in memory, needed for RA and others
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- [IRValidation.cpp](../FEXCore/Source/Interface/IR/Passes/IRValidation.cpp): Sanity checking pass
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- [LongDivideRemovalPass.cpp](../FEXCore/Source/Interface/IR/Passes/LongDivideRemovalPass.cpp): Long divide elimination pass
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- [RedundantFlagCalculationElimination.cpp](../FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp): This is not used right now, possibly broken
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- [RegisterAllocationPass.cpp](../FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp)
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- [RegisterAllocationPass.h](../FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.h)
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- [SyscallOptimization.cpp](../FEXCore/Source/Interface/IR/Passes/SyscallOptimization.cpp): Removes unused arguments if known syscall number
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- [ValueDominanceValidation.cpp](../FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp): Sanity Checking
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#### parser
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Text -> IR
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- [IRParser.cpp](../FEXCore/Source/Interface/IR/IRParser.cpp)
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### opcodes
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#### cpuid
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- [CPUID.cpp](../FEXCore/Source/Interface/Core/CPUID.cpp): Handles presented capability bits for guest cpu
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#### dispatcher-implementations
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- [Crypto.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp): Handles x86/64 Crypto instructions to IR
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- [Flags.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp): Handles x86/64 flag generation
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- [Vector.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp): Handles x86/64 Vector instructions to IR
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- [X87.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp): Handles x86/64 x87 to IR
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- [X87F64.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp): Handles x86/64 x87 to IR
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- [OpcodeDispatcher.cpp](../FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp): Handles x86/64 ops to IR, no-pf opt, local-flags opt
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## External/FEXCore
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## ThunkLibs
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See [ThunkLibs/README.md](../ThunkLibs/README.md) for more details
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Reference in new issue
Block a user