Docs: Update for release FEX-2204

Merge pull request #1644 from Sonicadvance1/ldiv_minor_opt
JITArm64: Get long divide out of the hot path
2026-10-07 00:00:17 +02:00 · 2022-04-19 01:19:00 -07:00 · 2022-04-01 18:23:30 -07:00 · 2022-04-01 18:23:13 -07:00 · 2022-04-01 18:08:02 -07:00 · 2022-03-31 09:33:19 -07:00
538 changed files with 41151 additions and 28536 deletions
@@ -0,0 +1,45 @@
+---
+name: Potential Game Bug
+about: A bug in FEX-Emu that causes a problem in a game
+title: "[Game]: [Short Problem Description]"
+labels: Game related
+assignees: ''
+
+---
+
+**What Game**
+The game name.
+A link to the storefront where to get the game. GOG, Steam, Itch.io, etc
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior:
+1. Go to '...'
+2. Click on '....'
+3. Scroll down to '....'
+4. See error
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Screenshots and Video**
+If applicable, add screenshots and video to help explain your problem.
+
+**System information:**
+ - OS: [eg: Ubuntu 21.10]
+ - CPU/SoC: [eg: Snapdragon 888, Intel Core i8-12900k]
+ - Video driver version: [eg: OpenGL ES 3.2 Mesa 22.0.0-devel (git-9ff086052a)]
+ - RootFS used: [eg: Ubuntu 21.10 Official Rootfs]
+ - FEX version: (FEXGetConfig --version) [eg: FEX-2112-155-gc691d709]
+ - Thunks Enabled: [Yes/No]
+
+**Additional context**
+ - Is this an x86 or x86-64 game: [x86/x86-64/Both]
+ - Does this reproduce on x86-64 host with FEX: [Yes/No/Untested]
+ - Does this reproduce on AArch64 with Radeon/Intel/Nvidia: [Yes/No/Untested]
+ - Is this a Vulkan game: [Yes/No/Unknown]
+   - If Yes, What is your Vulkan driver:
+
+Add any other context about the problem here.
@@ -31,7 +31,9 @@ jobs:

    - name : submodule checkout
      # Need to update submodules
-      run: git submodule update --init --depth 1
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1

    - name: Clean Build Environment
      run: rm -Rf ${{runner.workspace}}/build
@@ -49,7 +51,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -140,6 +142,17 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true

+    - name: APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target api_tests
+
+    - name: APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
+
    - name: Truncate test results
      if: ${{ always() }}
      shell: bash
@@ -1,7 +1,7 @@
 [submodule "External/vixl"]
 	shallow = true
 	path = External/vixl
-	url = https://github.com/Sonicadvance1/vixl.git
+	url = https://github.com/FEX-Emu/vixl.git
 [submodule "External/cpp-optparse"]
 	path = External/cpp-optparse
 	url = https://github.com/Sonicadvance1/cpp-optparse
@@ -42,7 +42,10 @@
 [submodule "External/xxhash"]
 	path = External/xxhash
 	url = https://github.com/FEX-Emu/xxHash.git
-[submodule "External/Vulkan-Docs"]
-  shallow = true
-	path = External/Vulkan-Docs
-	url = https://github.com/KhronosGroup/Vulkan-Docs.git
+[submodule "External/Catch2"]
+	path = External/Catch2
+	url = https://github.com/catchorg/Catch2.git
+[submodule "External/robin-map"]
+	shallow = true
+	path = External/robin-map
+	url = https://github.com/Tessil/robin-map.git
@@ -17,11 +17,21 @@ option(ENABLE_WERROR "Enables -Werror" FALSE)
 option(ENABLE_STATIC_PIE "Enables static-pie build" FALSE)
 option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
+option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
+option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
+option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
+option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
+option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)

 set (X86_C_COMPILER "x86_64-linux-gnu-gcc" CACHE STRING "c compiler for compiling x86 guest libs")
 set (X86_CXX_COMPILER "x86_64-linux-gnu-g++" CACHE STRING "c++ compiler for compiling x86 guest libs")
 set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu" CACHE PATH "global data directory")

+# These options are meant for package management
+set (TUNE_CPU "native" CACHE STRING "Override the CPU the build is tuned for")
+set (TUNE_ARCH "generic" CACHE STRING "Override the Arch the build is tuned for")
+set (OVERRIDE_VERSION "detect" CACHE STRING "Override the FEX version in the format of <MMYY>{.<REV>}")
+
 string(TOUPPER "${CMAKE_BUILD_TYPE}" CMAKE_BUILD_TYPE)
 if (CMAKE_BUILD_TYPE MATCHES "DEBUG")
  set(ENABLE_ASSERTIONS TRUE)
@@ -32,6 +42,11 @@ if (ENABLE_ASSERTIONS)
  add_definitions(-DASSERTIONS_ENABLED=1)
 endif()

+if (ENABLE_INTERPRETER)
+  message(STATUS "Interpreter enabled")
+  add_definitions(-DINTERPRETER_ENABLED=1)
+endif()
+
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
@@ -66,10 +81,12 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
  add_definitions(-D_M_ARM_64=1)
 endif()

-find_program(CCACHE_PROGRAM ccache)
-if(CCACHE_PROGRAM)
-  message(STATUS "CCache enabled")
-  set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${CCACHE_PROGRAM}")
+if (ENABLE_CCACHE)
+  find_program(CCACHE_PROGRAM ccache)
+  if(CCACHE_PROGRAM)
+    message(STATUS "CCache enabled")
+    set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${CCACHE_PROGRAM}")
+  endif()
 endif()

 if (ENABLE_XRAY)
@@ -77,17 +94,35 @@ if (ENABLE_XRAY)
  link_libraries(-fxray-instrument)
 endif()

+if (ENABLE_COMPILE_TIME_TRACE)
+  add_compile_options(-ftime-trace)
+  link_libraries(-ftime-trace)
+endif()
+
 set (PTHREAD_LIB pthread)
 if (ENABLE_LLD)
  set (LD_OVERRIDE "-fuse-ld=lld")
  link_libraries(${LD_OVERRIDE})
 endif()

+if (ENABLE_LIBCXX)
+  message(WARNING "This is an unsupported configuration and should only be used for testing")
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -stdlib=libc++")
+  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -stdlib=libc++ -lc++abi")
+endif()
+
 if (NOT ENABLE_OFFLINE_TELEMETRY)
  # Disable FEX offline telemetry entirely if asked
  add_definitions(-DFEX_DISABLE_TELEMETRY=1)
 endif()

+if(DEFINED ENV{TERMUX_VERSION} OR ENABLE_TERMUX_BUILD)
+  add_definitions(-DTERMUX_BUILD=1)
+  set(TERMUX_BUILD 1)
+  # Termux doesn't support Jemalloc due to bad interactions between emutls, jemalloc, and scudo
+  set(ENABLE_JEMALLOC FALSE)
+endif()
+
 if (ENABLE_STATIC_PIE)
  if (_M_ARM_64 AND ENABLE_LLD)
    message (FATAL_ERROR "Static linking does not currently work with AArch64+LLD. Use GNU ld for now.")
@@ -241,6 +276,8 @@ set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fn
 set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")

+include_directories(External/robin-map/include/)
+
 add_subdirectory(External/vixl/)
 include_directories(External/vixl/src/)

@@ -251,17 +288,23 @@ endif()

 find_package(PkgConfig REQUIRED)
 find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)
-pkg_check_modules(XXHASH libxxhash>=0.8.0 QUIET)

-if (NOT XXHASH_FOUND)
-  message(STATUS "xxHash not found. Using Externals")
-  add_subdirectory(External/xxhash/)
-  include_directories(External/xxhash/)
-endif()
+add_subdirectory(External/xxhash/)
+include_directories(External/xxhash/)

 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")

+if (BUILD_TESTS)
+  option(CATCH_BUILD_STATIC_LIBRARY "" ON)
+  set(CATCH_BUILD_STATIC_LIBRARY ON)
+  add_subdirectory(External/Catch2/)
+
+  # Pull in catch_discover_tests definition
+  list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/External/Catch2/contrib/")
+  include(Catch)
+endif()
+
 add_subdirectory(External/cpp-optparse/)
 include_directories(External/cpp-optparse/)

@@ -308,33 +351,51 @@ if(ENABLE_WERROR OR ENABLE_STRICT_WERROR)
  endif()
 endif()

-if(_M_ARM_64)
-  if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
-    # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
-    # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
-    check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
-    if(COMPILER_SUPPORTS_CPU_TYPE)
-      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=native")
+if (NOT TUNE_ARCH STREQUAL "generic")
+  check_cxx_compiler_flag("-march=${TUNE_ARCH}" COMPILER_SUPPORTS_ARCH_TYPE)
+  if(COMPILER_SUPPORTS_ARCH_TYPE)
+    add_compile_options("-march=${TUNE_ARCH}")
+  else()
+    message(FATAL_ERROR "Trying to compile arch type '${TUNE_ARCH}' but the compiler doesn't support this")
+  endif()
+endif()
+
+if (TUNE_CPU STREQUAL "native")
+  if(_M_ARM_64)
+    if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
+      # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
+      # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
+      check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
+      if(COMPILER_SUPPORTS_CPU_TYPE)
+        add_compile_options("-mcpu=native")
+      endif()
+    else()
+      # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
+      # Manually detect newer CPU revisions until clang and llvm fixes their bug
+      # This script will either provide a supported CPU or 'native'
+      # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
+      execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
+        OUTPUT_VARIABLE AARCH64_CPU)
+
+      string(STRIP ${AARCH64_CPU} AARCH64_CPU)
+
+      check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+      if(COMPILER_SUPPORTS_CPU_TYPE)
+        add_compile_options("-mcpu=${AARCH64_CPU}")
+      endif()
    endif()
  else()
-    # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
-    # Manually detect newer CPU revisions until clang and llvm fixes their bug
-    # This script will either provide a supported CPU or 'native'
-    # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
-    execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
-      OUTPUT_VARIABLE AARCH64_CPU)
-
-    string(STRIP ${AARCH64_CPU} AARCH64_CPU)
-
-    check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
-    if(COMPILER_SUPPORTS_CPU_TYPE)
-      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+    check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
+    if(COMPILER_SUPPORTS_MARCH_NATIVE)
+      add_compile_options("-march=native")
    endif()
  endif()
 else()
-  check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
-  if(COMPILER_SUPPORTS_MARCH_NATIVE)
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
+  check_cxx_compiler_flag("-mcpu=${TUNE_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+  if(COMPILER_SUPPORTS_CPU_TYPE)
+    add_compile_options("-mcpu=${TUNE_CPU}")
+  else()
+    message(FATAL_ERROR "Trying to compile cpu type '${TUNE_CPU}' but the compiler doesn't support this")
  endif()
 endif()

@@ -408,6 +469,10 @@ if (BUILD_TESTS)
  enable_testing()
  message(STATUS "Unit tests are enabled")
 endif()
+
+add_subdirectory(FEXHeaderUtils/)
+include_directories(FEXHeaderUtils/)
+
 add_subdirectory(External/FEXCore)

 # Binfmt_misc files must be installed prior to Source/ installs
@@ -426,29 +491,16 @@ if (BUILD_TESTS)
 endif()

 if (BUILD_THUNKS)
+  add_subdirectory(ThunkLibs/Generator)
+
+  # Thunk targets for both host libraries and IDE integration
+  add_subdirectory(ThunkLibs/HostLibs)
+
+  # Thunk targets for IDE integration of guest code, only
+  add_subdirectory(ThunkLibs/GuestLibs)
+
+  # Thunk targets for guest libraries
  include(ExternalProject)
-
-  ExternalProject_Add(host-libs
-    PREFIX host-libs
-    SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/HostLibs"
-    BINARY_DIR "Host"
-    CMAKE_ARGS
-      "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
-      "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
-      "-DVULKAN_XML=${CMAKE_SOURCE_DIR}/External/Vulkan-Docs/xml/vk.xml"
-    INSTALL_COMMAND ""
-    BUILD_ALWAYS ON
-  )
-
-  install(
-    CODE "MESSAGE(\"-- Installing: host-libs\")"
-    CODE "
-    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkHostsInstall
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Host
-    )"
-    DEPENDS host-libs
-  )
-
  ExternalProject_Add(guest-libs
    PREFIX guest-libs
    SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
@@ -459,15 +511,16 @@ if (BUILD_THUNKS)
      "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}"
      "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
      "-DSTRUCT_VERIFIER=${CMAKE_SOURCE_DIR}/Scripts/StructPackVerifier.py"
-      "-DVULKAN_XML=${CMAKE_SOURCE_DIR}/External/Vulkan-Docs/xml/vk.xml"
+      "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
    INSTALL_COMMAND ""
    BUILD_ALWAYS ON
+    DEPENDS thunkgen
  )

  install(
    CODE "MESSAGE(\"-- Installing: guest-libs\")"
    CODE "
-    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkGuestsInstall
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target install
    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
    )"
    DEPENDS guest-libs
@@ -478,59 +531,73 @@ set(FEX_VERSION_MAJOR "0")
 set(FEX_VERSION_MINOR "0")
 set(FEX_VERSION_PATCH "0")

-find_package(Git)
-if (GIT_FOUND)
-  execute_process(
-    COMMAND ${GIT_EXECUTABLE} describe --abbrev=0
-    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-    OUTPUT_VARIABLE GIT_DESCRIBE_STRING
-    RESULT_VARIABLE GIT_ERROR
-    ERROR_QUIET
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-  )
+if (OVERRIDE_VERSION STREQUAL "detect")
+  find_package(Git)
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} describe --abbrev=0
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+      RESULT_VARIABLE GIT_ERROR
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )

-  if (NOT ${GIT_ERROR} EQUAL 0)
-    # Likely built in a way that doesn't have tags
-    # Setup a version tag that is unknown
-    set(GIT_DESCRIBE_STRING "FEX-0000")
+    if (NOT ${GIT_ERROR} EQUAL 0)
+      # Likely built in a way that doesn't have tags
+      # Setup a version tag that is unknown
+      set(GIT_DESCRIBE_STRING "FEX-0000")
+    endif()
  endif()
+else()
+  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
+endif()

-  # Change something like `FEX-2106.1-76-<hash>` in to a list
-  string(REPLACE "-" ";" DESCRIBE_LIST ${GIT_DESCRIBE_STRING})
+# Parse the version here
+# Change something like `FEX-2106.1-76-<hash>` in to a list
+string(REPLACE "-" ";" DESCRIBE_LIST ${GIT_DESCRIBE_STRING})

-  # Extract the `2106.1` element
-  list(GET DESCRIBE_LIST 1 DESCRIBE_LIST)
+# Extract the `2106.1` element
+list(GET DESCRIBE_LIST 1 DESCRIBE_LIST)

-  # Change `2106.1` in to a list
-  string(REPLACE "." ";" DESCRIBE_LIST ${DESCRIBE_LIST})
+# Change `2106.1` in to a list
+string(REPLACE "." ";" DESCRIBE_LIST ${DESCRIBE_LIST})

-  # Calculate list size
-  list(LENGTH DESCRIBE_LIST LIST_SIZE)
+# Calculate list size
+list(LENGTH DESCRIBE_LIST LIST_SIZE)

-  # Pull out the major version
-  list(GET DESCRIBE_LIST 0 FEX_VERSION_MAJOR)
+# Pull out the major version
+list(GET DESCRIBE_LIST 0 FEX_VERSION_MAJOR)

-  # Minor version only exists if there is a .1 at the end
-  # eg: 2106 versus 2106.1
-  if (LIST_SIZE GREATER 1)
-    list(GET DESCRIBE_LIST 1 FEX_VERSION_MINOR)
-  endif()
+# Minor version only exists if there is a .1 at the end
+# eg: 2106 versus 2106.1
+if (LIST_SIZE GREATER 1)
+  list(GET DESCRIBE_LIST 1 FEX_VERSION_MINOR)
 endif()

 # Package creation
 set (CPACK_GENERATOR "DEB")
-set (CPACK_PACKAGE_NAME fex-emu)
-set (CPACK_PACKAGE_CONTACT "team@fex-emu.org")
+if (ENABLE_STATIC_PIE)
+  set (CPACK_PACKAGE_NAME fex-emu-static)
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu")
+else()
+  set (CPACK_PACKAGE_NAME fex-emu)
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu-static")
+endif()
+set (CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${GIT_DESCRIBE_STRING}_${CMAKE_SYSTEM_PROCESSOR}")
+set (CPACK_PACKAGE_CONTACT "FEX-Emu Maintainers <team@fex-emu.org>")
 set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
 set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")
 set (CPACK_PACKAGE_VERSION_PATCH "${FEX_VERSION_PATCH}")
+set (CPACK_PACKAGE_DESCRIPTION_FILE "${CMAKE_CURRENT_SOURCE_DIR}/CPack/Description.txt")

 # Debian defines
-set (CPACK_DEBIAN_PACKAGE_DEPENDS "libstdc++6")
-set (CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_CURRENT_SOURCE_DIR}/CPack/postinst;${CMAKE_CURRENT_SOURCE_DIR}/CPack/prerm")
+set (CPACK_DEBIAN_PACKAGE_DEPENDS "libc6, libstdc++6, libepoxy0, libsdl2-2.0-0, libegl1, libx11-6, squashfuse")
+set (CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA
+  "${CMAKE_CURRENT_SOURCE_DIR}/CPack/postinst;${CMAKE_CURRENT_SOURCE_DIR}/CPack/prerm;${CMAKE_CURRENT_SOURCE_DIR}/CPack/triggers")
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
  # binfmt_misc conflicts with qemu-user-static
  # We also only install binfmt_misc on aarch64 hosts
-  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "qemu-user-static")
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "${CPACK_DEBIAN_PACKAGE_CONFLICTS}, qemu-user-static")
 endif()
 include (CPack)
@@ -0,0 +1,3 @@
+x86 and x86-64 Linux emulator
+
+FEX is very much work in progress, so expect things to change.
@@ -0,0 +1 @@
+activate-noawait ldconfig
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "StallProcess": "1"
-  }
-}
@@ -10,6 +10,10 @@
        "/usr/lib/x86_64-linux-gnu/libGL.so.1",
        "/usr/lib/x86_64-linux-gnu/libGL.so.1.2.0",
        "/usr/lib/x86_64-linux-gnu/libGL.so.1.7.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1.2.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGL.so.1.7.0",
        "/lib/x86_64-linux-gnu/libGL.so",
        "/lib/x86_64-linux-gnu/libGL.so.1",
        "/lib/x86_64-linux-gnu/libGL.so.1.2.0",
@@ -25,6 +29,9 @@
        "/usr/lib/x86_64-linux-gnu/libGLESv2.so",
        "/usr/lib/x86_64-linux-gnu/libGLESv2.so.2",
        "/usr/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0",
        "/lib/x86_64-linux-gnu/libGLESv2.so",
        "/lib/x86_64-linux-gnu/libGLESv2.so.2",
        "/lib/x86_64-linux-gnu/libGLESv2.so.2.0.0"
@@ -36,6 +43,9 @@
        "/usr/lib/x86_64-linux-gnu/libX11.so",
        "/usr/lib/x86_64-linux-gnu/libX11.so.6",
        "/usr/lib/x86_64-linux-gnu/libX11.so.6.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so.6",
+        "/usr/local/lib/x86_64-linux-gnu/libX11.so.6.4.0",
        "/lib/x86_64-linux-gnu/libX11.so",
        "/lib/x86_64-linux-gnu/libX11.so.6",
        "/lib/x86_64-linux-gnu/libX11.so.6.4.0"
@@ -48,6 +58,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_radeon.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_radeon.so",
        "/lib/x86_64-linux-gnu/libvulkan_radeon.so"
      ],
      "Comment": [
@@ -61,6 +72,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_lvp.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_lvp.so",
        "/lib/x86_64-linux-gnu/libvulkan_lvp.so"
      ]
    },
@@ -71,6 +83,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_freedreno.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_freedreno.so",
        "/lib/x86_64-linux-gnu/libvulkan_freedreno.so"
      ]
    },
@@ -81,6 +94,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_intel.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_intel.so",
        "/lib/x86_64-linux-gnu/libvulkan_intel.so"
      ]
    },
@@ -91,6 +105,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_panfrost.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_panfrost.so",
        "/lib/x86_64-linux-gnu/libvulkan_panfrost.so"
      ]
    },
@@ -101,6 +116,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libGLX_nvidia.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libGLX_nvidia.so.0",
        "/lib/x86_64-linux-gnu/libGLX_nvidia.so.0"
      ],
      "Comment": [
@@ -114,6 +130,7 @@
      ],
      "Overlay": [
        "/usr/lib/x86_64-linux-gnu/libvulkan_virtio.so",
+        "/usr/local/lib/x86_64-linux-gnu/libvulkan_virtio.so",
        "/lib/x86_64-linux-gnu/libvulkan_virtio.so"
      ]
    },
@@ -123,6 +140,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb.so",
        "/usr/lib/x86_64-linux-gnu/libxcb.so.1",
        "/usr/lib/x86_64-linux-gnu/libxcb.so.1.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb.so.1.1.0",
        "/lib/x86_64-linux-gnu/libxcb.so",
        "/lib/x86_64-linux-gnu/libxcb.so.1",
        "/lib/x86_64-linux-gnu/libxcb.so.1.1.0"
@@ -134,6 +154,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-dri2.so",
        "/lib/x86_64-linux-gnu/libxcb-dri2.so.0",
        "/lib/x86_64-linux-gnu/libxcb-dri2.so.0.0.0"
@@ -145,6 +168,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-dri3.so",
        "/lib/x86_64-linux-gnu/libxcb-dri3.so.0",
        "/lib/x86_64-linux-gnu/libxcb-dri3.so.0.0.0"
@@ -156,6 +182,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-xfixes.so",
        "/lib/x86_64-linux-gnu/libxcb-xfixes.so.0",
        "/lib/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0"
@@ -167,6 +196,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-shm.so",
        "/lib/x86_64-linux-gnu/libxcb-shm.so.0",
        "/lib/x86_64-linux-gnu/libxcb-shm.so.0.0.0"
@@ -178,6 +210,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so.1",
        "/usr/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0",
        "/lib/x86_64-linux-gnu/libxcb-sync.so",
        "/lib/x86_64-linux-gnu/libxcb-sync.so.1",
        "/lib/x86_64-linux-gnu/libxcb-sync.so.1.0.0"
@@ -189,6 +224,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0",
        "/lib/x86_64-linux-gnu/libxcb-randr.so",
        "/lib/x86_64-linux-gnu/libxcb-randr.so.0",
        "/lib/x86_64-linux-gnu/libxcb-randr.so.0.1.0"
@@ -200,6 +238,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-present.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-present.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-present.so",
        "/lib/x86_64-linux-gnu/libxcb-present.so.0",
        "/lib/x86_64-linux-gnu/libxcb-present.so.0.0.0"
@@ -211,6 +252,9 @@
        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so",
        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so.0",
        "/usr/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0",
        "/lib/x86_64-linux-gnu/libxcb-glx.so",
        "/lib/x86_64-linux-gnu/libxcb-glx.so.0",
        "/lib/x86_64-linux-gnu/libxcb-glx.so.0.0.0"
@@ -222,6 +266,9 @@
        "/usr/lib/x86_64-linux-gnu/libxshmfence.so",
        "/usr/lib/x86_64-linux-gnu/libxshmfence.so.1",
        "/usr/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0",
        "/lib/x86_64-linux-gnu/libxshmfence.so",
        "/lib/x86_64-linux-gnu/libxshmfence.so.1",
        "/lib/x86_64-linux-gnu/libxshmfence.so.1.0.0"
@@ -233,6 +280,9 @@
        "/usr/lib/x86_64-linux-gnu/libdrm.so",
        "/usr/lib/x86_64-linux-gnu/libdrm.so.2",
        "/usr/lib/x86_64-linux-gnu/libdrm.so.2.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libdrm.so.2.4.0",
        "/lib/x86_64-linux-gnu/libdrm.so",
        "/lib/x86_64-linux-gnu/libdrm.so.2",
        "/lib/x86_64-linux-gnu/libdrm.so.2.4.0"
@@ -244,6 +294,9 @@
        "/usr/lib/x86_64-linux-gnu/libasound.so",
        "/usr/lib/x86_64-linux-gnu/libasound.so.2",
        "/usr/lib/x86_64-linux-gnu/libasound.so.2.0.0",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so.2",
+        "/usr/local/lib/x86_64-linux-gnu/libasound.so.2.0.0",
        "/lib/x86_64-linux-gnu/libasound.so",
        "/lib/x86_64-linux-gnu/libasound.so.2",
        "/lib/x86_64-linux-gnu/libasound.so.2.0.0"
@@ -255,6 +308,9 @@
        "/usr/lib/x86_64-linux-gnu/libXrender.so",
        "/usr/lib/x86_64-linux-gnu/libXrender.so.1",
        "/usr/lib/x86_64-linux-gnu/libXrender.so.1.3.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so.1",
+        "/usr/local/lib/x86_64-linux-gnu/libXrender.so.1.3.0",
        "/lib/x86_64-linux-gnu/libXrender.so",
        "/lib/x86_64-linux-gnu/libXrender.so.1",
        "/lib/x86_64-linux-gnu/libXrender.so.1.3.0"
@@ -266,6 +322,9 @@
        "/usr/lib/x86_64-linux-gnu/libXext.so",
        "/usr/lib/x86_64-linux-gnu/libXext.so.6",
        "/usr/lib/x86_64-linux-gnu/libXext.so.6.4.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so.6",
+        "/usr/local/lib/x86_64-linux-gnu/libXext.so.6.4.0",
        "/lib/x86_64-linux-gnu/libXext.so",
        "/lib/x86_64-linux-gnu/libXext.so.6",
        "/lib/x86_64-linux-gnu/libXext.so.6.4.0"
@@ -277,6 +336,9 @@
        "/usr/lib/x86_64-linux-gnu/libXfixes.so",
        "/usr/lib/x86_64-linux-gnu/libXfixes.so.3",
        "/usr/lib/x86_64-linux-gnu/libXfixes.so.3.1.0",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so.3",
+        "/usr/local/lib/x86_64-linux-gnu/libXfixes.so.3.1.0",
        "/lib/x86_64-linux-gnu/libXfixes.so",
        "/lib/x86_64-linux-gnu/libXfixes.so.3",
        "/lib/x86_64-linux-gnu/libXfixes.so.3.1.0"
@@ -37,27 +37,32 @@ endif()
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)

-# Find our git hash
-find_package(Git)
-
 set(GIT_SHORT_HASH "Unknown")
 set(GIT_DESCRIBE_STRING "FEX-Unknown")

-if (GIT_FOUND)
-  execute_process(
-    COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
-    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-    OUTPUT_VARIABLE GIT_SHORT_HASH
-    ERROR_QUIET
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-  )
-  execute_process(
-    COMMAND ${GIT_EXECUTABLE} describe
-    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-    OUTPUT_VARIABLE GIT_DESCRIBE_STRING
-    ERROR_QUIET
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-  )
+if (OVERRIDE_VERSION STREQUAL "detect")
+# Find our git hash
+  find_package(Git)
+
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_SHORT_HASH
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} describe
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE
+    )
+  endif()
+else()
+  set(GIT_SHORT_HASH "${OVERRIDE_VERSION}")
+  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
 endif()

 configure_file(
@@ -18,14 +18,8 @@ This project aims to provide a fast and functional x86-64 emulation library that
 * Portable library implementation in order to support easy integration in to applications
 ### Target Host Architecture
 The target host architecture for this library is AArch64. Specifically the ARMv8.1 version or newer.
-The CPU IR is designed with AArch64 in mind but there is a desire to run the recompiled code on other architectures as well.
-Multiple architecture support is desired for easier bringup and debugging, performance isn't as much of a priority there (ex. x86-64(guest) translated to x86-64(host))
-### Not currently goals but will be in the future
-* 32bit x86 support
-  * This will be a desire in the future, but to lower the amount of work required, decided to push this off for now.
-* Integration in to WINE
-* Later generation of x86-64 instruction sets
-  * Including AVX, F16C, XOP, FMA, AVX2, etc
+The CPU IR is designed with AArch64 in mind but should allow for other architectures as well.
+x86-64 host support is available for ease of development, but is not a priority.
 ### Not desired
 * Kernel space emulation
 * CPL0-2 emulation
@@ -33,7 +27,3 @@ Multiple architecture support is desired for easier bringup and debugging, perfo
 * IRQs
 * SVM
 * "Cycle Accurate" emulation
-### Dependencies
- * clang-tidy if you want to ensure the code stays tidy
- * cmake
- * A C++17 compliant compiler (There are assumptions made about using Clang and LTO)
@@ -7,17 +7,12 @@ OpClasses = collections.OrderedDict()
 def get_ir_classes(ops, defines):
    global OpClasses

-    for op_key, op_vals in ops.items():
-        if not ("Last" in op_vals):
-            OpClass = "#Unknown"
+    for op_class, opslist in ops.items():
+        if not (op_class in OpClasses):
+            OpClasses[op_class] = []

-            if ("OpClass" in op_vals):
-                OpClass = op_vals["OpClass"]
-
-            if not (OpClass in OpClasses):
-                OpClasses[OpClass] = []
-
-            OpClasses[OpClass].append([op_key, op_vals])
+        for op, op_val in opslist.items():
+            OpClasses[op_class].append([op, op_val])

    # Sort the dictionary after we are done parsing it
    OpClasses = collections.OrderedDict(sorted(OpClasses.items()))
@@ -38,41 +33,9 @@ def print_ir_ops():
            op_key = op[0]
            op_vals = op[1]
            output_file.write("## %s\n" % (op_key))
-            HasDest = ("HasDest" in op_vals and op_vals["HasDest"] == True)
-            HasSSAArgs = ("SSAArgs" in op_vals and len(op_vals["SSAArgs"]) > 0)
-            HasSSAArgNames = "SSANames" in op_vals
-            HasArgs = "Args" in op_vals
-            SSAArgsCount = 0
-            ArgCount = 0
-            if (HasSSAArgs):
-                SSAArgsCount = int(op_vals["SSAArgs"])
-            if (HasArgs):
-                ArgCount = len(op_vals["Args"])
-
-            TotalArgsCount = SSAArgsCount + (ArgCount / 2)

            output_file.write(">")
-            if (HasDest):
-                output_file.write("%dest = ")
-
-            output_file.write("%s " % op_key)
-
-            ArgComma = (", ", "")
-            if (HasSSAArgs):
-                for i in range(0, SSAArgsCount):
-                    FinalArg = (i + 1) == TotalArgsCount
-                    if (HasSSAArgNames):
-                        output_file.write("%%%s%s" % (op_vals["SSANames"][i], ArgComma[FinalArg]))
-                    else:
-                        output_file.write("%%ssa%d%s" % (i, ArgComma[FinalArg]))
-
-            if (HasArgs):
-                Args = op_vals["Args"]
-                for i in range(0, ArgCount, 2):
-                    FinalArg = ((i / 2) + SSAArgsCount + 1) == TotalArgsCount
-                    data_type = Args[i]
-                    data_name = Args[i + 1]
-                    output_file.write("\<%s %s\>%s" % (data_type, data_name, ArgComma[FinalArg]))
+            output_file.write(op_key)

            output_file.write("\n\n")

@@ -1,9 +1,15 @@
 set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")

-set (SRCS
+set (FEXCORE_BASE_SRCS
  Common/Paths.cpp
+  Interface/Config/Config.cpp
+  Utils/FileLoading.cpp
+  Utils/ForcedAssert.cpp
+  Utils/LogManager.cpp
+  )
+
+set (SRCS
  Common/JitSymbols.cpp
-  Common/NetStream.cpp
  Common/SoftFloat-3e/extF80_add.c
  Common/SoftFloat-3e/extF80_div.c
  Common/SoftFloat-3e/extF80_sub.c
@@ -71,7 +77,6 @@ set (SRCS
  Common/SoftFloat-3e/f32_to_extF80.c
  Common/SoftFloat-3e/s_normSubnormalF32Sig.c
  Common/SoftFloat-3e/s_f32UIToCommonNaN.c
-  Interface/Config/Config.cpp
  Interface/Context/Context.cpp
  Interface/Core/LookupCache.cpp
  Interface/Core/BlockSamplingData.cpp
@@ -95,19 +100,7 @@ set (SRCS
  Interface/Core/Dispatcher/Dispatcher.cpp
  Interface/Core/Dispatcher/X86Dispatcher.cpp
  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
-  Interface/Core/Interpreter/InterpreterCore.cpp
-  Interface/Core/Interpreter/InterpreterOps.cpp
-  Interface/Core/Interpreter/ALUOps.cpp
-  Interface/Core/Interpreter/AtomicOps.cpp
-  Interface/Core/Interpreter/BranchOps.cpp
-  Interface/Core/Interpreter/ConversionOps.cpp
-  Interface/Core/Interpreter/EncryptionOps.cpp
-  Interface/Core/Interpreter/F80Ops.cpp
-  Interface/Core/Interpreter/FlagOps.cpp
-  Interface/Core/Interpreter/MemoryOps.cpp
-  Interface/Core/Interpreter/MiscOps.cpp
-  Interface/Core/Interpreter/MoveOps.cpp
-  Interface/Core/Interpreter/VectorOps.cpp
+  Interface/Core/Interpreter/InterpreterFallbacks.cpp
  Interface/Core/X86Tables/BaseTables.cpp
  Interface/Core/X86Tables/DDDTables.cpp
  Interface/Core/X86Tables/EVEXTables.cpp
@@ -121,6 +114,7 @@ set (SRCS
  Interface/Core/X86Tables/X87Tables.cpp
  Interface/Core/X86Tables/XOPTables.cpp
  Interface/HLE/Thunks/Thunks.cpp
+  Interface/IR/AOTIR.cpp
  Interface/IR/IRDumper.cpp
  Interface/IR/IRParser.cpp
  Interface/IR/IREmitter.cpp
@@ -141,12 +135,28 @@ set (SRCS
  Interface/IR/Passes/SyscallOptimization.cpp
  Utils/Allocator.cpp
  Utils/Allocator/64BitAllocator.cpp
-  Utils/FileLoading.cpp
-  Utils/LogManager.cpp
+  Utils/NetStream.cpp
  Utils/Telemetry.cpp
  Utils/Threads.cpp
  )

+if (ENABLE_INTERPRETER)
+  list(APPEND SRCS
+    Interface/Core/Interpreter/InterpreterCore.cpp
+    Interface/Core/Interpreter/InterpreterOps.cpp
+    Interface/Core/Interpreter/ALUOps.cpp
+    Interface/Core/Interpreter/AtomicOps.cpp
+    Interface/Core/Interpreter/BranchOps.cpp
+    Interface/Core/Interpreter/ConversionOps.cpp
+    Interface/Core/Interpreter/EncryptionOps.cpp
+    Interface/Core/Interpreter/F80Ops.cpp
+    Interface/Core/Interpreter/FlagOps.cpp
+    Interface/Core/Interpreter/MemoryOps.cpp
+    Interface/Core/Interpreter/MiscOps.cpp
+    Interface/Core/Interpreter/MoveOps.cpp
+    Interface/Core/Interpreter/VectorOps.cpp)
+endif()
+
 if(_M_ARM_64)
  list(APPEND SRCS
    Interface/Core/ArchHelpers/Arm64.cpp)
@@ -194,7 +204,7 @@ if (ENABLE_JIT_ARM64)
    Interface/Core/JIT/Arm64/VectorOps.cpp)
 endif()

-set (LIBS vixl dl fmt::fmt xxhash tiny-json)
+set (LIBS vixl dl xxhash tiny-json)
 if (ENABLE_JEMALLOC)
  list (APPEND LIBS FEX_jemalloc)
 endif()
@@ -248,6 +258,7 @@ set(OUTPUT_CONFIG_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigValues.inl")
 set(OUTPUT_CONFIG_OPTION_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigOptions.inl")
 set(INPUT_CONFIG_NAME "${CMAKE_BINARY_DIR}/generated/Config/Config.json")
 set(OUTPUT_MAN_NAME "${CMAKE_BINARY_DIR}/generated/FEX.1")
+set(OUTPUT_MAN_NAME_COMPRESS "${CMAKE_BINARY_DIR}/generated/FEX.1.gz")

 add_custom_target(CREATE_CONFIG_FOLDER ALL
  COMMAND ${CMAKE_COMMAND} -E make_directory "${OUTPUT_CONFIG_FOLDER}")
@@ -263,6 +274,12 @@ add_custom_command(
  "${OUTPUT_CONFIG_OPTION_NAME}"
  )

+add_custom_command(
+  OUTPUT "${OUTPUT_MAN_NAME_COMPRESS}"
+  DEPENDS "${OUTPUT_MAN_NAME}"
+  COMMAND "gzip" "-kf9n" "${OUTPUT_MAN_NAME}"
+  )
+
 set_source_files_properties(${OUTPUT_CONFIG_NAME} PROPERTIES
  GENERATED TRUE)
 set_source_files_properties(${OUTPUT_CONFIG_OPTION_NAME} PROPERTIES
@@ -270,32 +287,28 @@ set_source_files_properties(${OUTPUT_CONFIG_OPTION_NAME} PROPERTIES

 set_source_files_properties(${OUTPUT_MAN_NAME} PROPERTIES
  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_MAN_NAME_COMPRESS} PROPERTIES
+  GENERATED TRUE)

 # Create the target
 add_custom_target(CONFIG_INC
  DEPENDS "${OUTPUT_CONFIG_NAME}"
  DEPENDS "${OUTPUT_CONFIG_OPTION_NAME}"
-  DEPENDS "${OUTPUT_MAN_NAME}")
+  DEPENDS "${OUTPUT_MAN_NAME}"
+  DEPENDS "${OUTPUT_MAN_NAME_COMPRESS}")

-# Install the man page
-install(FILES ${OUTPUT_MAN_NAME} DESTINATION ${MAN_DIR}/man1)
+# Install the compressed man page
+install(FILES ${OUTPUT_MAN_NAME_COMPRESS} DESTINATION ${MAN_DIR}/man1)

 # Add in diagnostic colours if the option is available.
 # Ninja code generator will kill colours if this isn't here
 check_cxx_compiler_flag(-fdiagnostics-color=always GCC_COLOR)
 check_cxx_compiler_flag(-fcolor-diagnostics CLANG_COLOR)

-function(AddObject Name Type)
-  add_library(${Name} ${Type} ${SRCS})
-  add_dependencies(${Name} IR_INC)
-  add_dependencies(${Name} CONFIG_INC)
-
-  target_link_libraries(${Name} ${LIBS})
-  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+function(AddDefaultOptionsToTarget Name)
  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
-
  target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")

  target_include_directories(${Name} PRIVATE IncludePrivate/)
@@ -305,6 +318,7 @@ function(AddObject Name Type)
  target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")

  target_compile_definitions(${Name} PRIVATE ${DEFINES})
+  add_dependencies(${Name} CONFIG_INC)

  target_compile_options(${Name}
    PRIVATE
@@ -327,19 +341,6 @@ function(AddObject Name Type)
      PRIVATE
      "-fcolor-diagnostics")
  endif()
-endfunction()
-
-function(AddLibrary Name Type)
-  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
-  target_link_libraries(${Name} ${LIBS})
-  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
-  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
-  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
-  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
-
-  target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
-  target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
-  target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")

  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
    target_link_options(${Name}
@@ -351,6 +352,29 @@ function(AddLibrary Name Type)
  endif()
 endfunction()

+# Build FEXCore_Config static library
+add_library(FEXCore_Base STATIC ${FEXCORE_BASE_SRCS})
+target_link_libraries(FEXCore_Base fmt::fmt tiny-json)
+AddDefaultOptionsToTarget(FEXCore_Base)
+
+function(AddObject Name Type)
+  add_library(${Name} ${Type} ${SRCS})
+  add_dependencies(${Name} IR_INC)
+
+  target_link_libraries(${Name} FEXCore_Base ${LIBS})
+  AddDefaultOptionsToTarget(${Name})
+
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+endfunction()
+
+function(AddLibrary Name Type)
+  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
+  target_link_libraries(${Name} FEXCore_Base ${LIBS})
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+
+  AddDefaultOptionsToTarget(${Name})
+endfunction()
+
 AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
@@ -1,13 +1,16 @@
 #pragma once
-#include "Common/MathUtils.h"
+
 #include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/Utils/MathUtils.h>
 #include <FEXCore/Utils/LogManager.h>

+#include <cstdint>
+#include <cstdlib>
 #include <cstring>
-#include <stdint.h>
-#include <stdlib.h>
 #include <type_traits>

+namespace FEXCore {
+
 template<typename T>
 struct BitSet final {
  using ElementType = T;
@@ -17,12 +20,12 @@ struct BitSet final {
  ElementType *Memory;
  void Allocate(size_t Elements) {
    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
  }
  void Realloc(size_t Elements) {
    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
  }
  void Free() {
@@ -61,8 +64,8 @@ struct BitSetView final {
  ElementType *Memory;

  void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LOGMAN_THROW_A((ElementOffset % MinimumSize) == 0,
-        "Bitset view offset needs to be aligned to size of backing element");
+    LOGMAN_THROW_A_FMT((ElementOffset % MinimumSize) == 0,
+                       "Bitset view offset needs to be aligned to size of backing element");
    Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
  }

@@ -87,11 +90,12 @@ struct BitSetView final {
  bool operator[](T Element) {
    return Get(Element);
  }
-
 };

 static_assert(sizeof(BitSet<uint32_t>) == sizeof(uintptr_t), "Needs to just be a pointer");
-static_assert(std::is_trivially_copyable<BitSet<uint32_t>>::value, "Needs to trivially copyable");
+static_assert(std::is_trivially_copyable_v<BitSet<uint32_t>>, "Needs to trivially copyable");

 static_assert(sizeof(BitSetView<uint32_t>) == sizeof(uintptr_t), "Needs to just be a pointer");
-static_assert(std::is_trivially_copyable<BitSetView<uint32_t>>::value, "Needs to trivially copyable");
+static_assert(std::is_trivially_copyable_v<BitSetView<uint32_t>>, "Needs to trivially copyable");
+
+} // namespace FEXCore
@@ -1,66 +1,53 @@
 #include "Common/JitSymbols.h"

 #include <string>
-#include <sstream>
 #include <unistd.h>

-namespace FEXCore {
-  JITSymbols::JITSymbols() {
-    std::stringstream PerfMap;
-    PerfMap << "/tmp/perf-" << getpid() << ".map";
+#include <fmt/format.h>

-    fp = fopen(PerfMap.str().c_str(), "wb");
+namespace FEXCore {
+  JITSymbols::JITSymbols() : fp{nullptr, std::fclose} {
+    const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
+
+    fp.reset(fopen(PerfMap.c_str(), "wb"));
    if (fp) {
      // Disable buffering on this file
-      setvbuf(fp, nullptr, _IONBF, 0);
+      setvbuf(fp.get(), nullptr, _IONBF, 0);
    }
  }

-  JITSymbols::~JITSymbols() {
-    if (fp) {
-      fclose(fp);
-    }
-  }
+  JITSymbols::~JITSymbols() = default;

-  void JITSymbols::Register(void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
+  void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
    if (!fp) return;

    // Linux perf format is very straightforward
    // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " " << "JIT_0x" << GuestAddr << "_" << HostAddr << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
  }

-  void JITSymbols::Register(void *HostAddr, uint32_t CodeSize, std::string const &Name) {
+  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
    if (!fp) return;

    // Linux perf format is very straightforward
    // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " " << Name << "_" << HostAddr << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
  }

-  void JITSymbols::RegisterNamedRegion(void *HostAddr, uint32_t CodeSize, std::string const &Name) {
+  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
    if (!fp) return;

    // Linux perf format is very straightforward
    // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " " << Name << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} {}\n", HostAddr, CodeSize, Name);
  }

-  void JITSymbols::RegisterJITSpace(void *HostAddr, uint32_t CodeSize) {
+  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
    if (!fp) return;

    // Linux perf format is very straightforward
    // `<HostPtr> <Size> <Name>\n`
-    std::stringstream String;
-    String << std::hex << HostAddr << " " << CodeSize << " FEXJIT" << std::endl;
-    fwrite(String.str().c_str(), 1, String.str().size(), fp);
+    fmt::print(fp.get(), "{} {:x} FEXJIT\n", HostAddr, CodeSize);
  }

-}
-
+} // namespace FEXCore
@@ -1,19 +1,24 @@
 #pragma once
+
 #include <cstdint>
 #include <cstdio>
-#include <string>
+#include <memory>
+#include <string_view>

 namespace FEXCore {
 class JITSymbols final {
 public:
  JITSymbols();
  ~JITSymbols();
-  void Register(void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
-  void Register(void *HostAddr, uint32_t CodeSize, std::string const &Name);
-  void RegisterNamedRegion(void *HostAddr, uint32_t CodeSize, std::string const &Name);
-  void RegisterJITSpace(void *HostAddr, uint32_t CodeSize);
+
+  void Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
+  void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);

 private:
-  FILE* fp{};
+  using FILEPtr = std::unique_ptr<FILE, decltype(&std::fclose)>;
+
+  FILEPtr fp;
 };
 }
@@ -1,13 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-
-static inline uint64_t AlignUp(uint64_t value, uint64_t size) {
-  return value + (size - value % size) % size;
-};
-
-static inline uint64_t AlignDown(uint64_t value, uint64_t size) {
-  return value - value % size;
-};
-
-
@@ -1,42 +0,0 @@
-#pragma once
-
-#include <array>
-#include <iostream>
-#include <iterator>
-#include <string.h>
-
-class NetStream : public std::iostream {
-public:
-    NetStream(int socketfd) : std::iostream(new NetBuf(socketfd)) {}
-    virtual ~NetStream();
-
-private:
-    class NetBuf : public std::streambuf {
-
-    public:
-        NetBuf(int socketfd) {
-            socket = socketfd;
-            reset_output_buffer();
-        }
-        virtual ~NetBuf();
-
-    protected:
-        virtual std::streamsize xsputn(const char* buffer, std::streamsize size);
-
-        virtual std::streambuf::int_type underflow();
-        virtual std::streambuf::int_type overflow(std::streambuf::int_type ch);
-        virtual int sync();
-
-    private:
-        void reset_output_buffer() {
-            // we always leave room for one extra char
-            setp(std::begin(output_buffer), std::end(output_buffer) -1);
-        }
-
-        int flushBuffer(const char *buffer, size_t size);
-
-        int socket;
-        std::array<char, 1400> output_buffer;
-        std::array<char, 1500> input_buffer; // enough for a typical packet
-    };
-};
@@ -72,7 +72,7 @@ namespace FEXCore::Paths {
    // Ensure the folder structure is created for our Data
    if (!std::filesystem::exists(*EntryCache, ec) &&
        !std::filesystem::create_directories(*EntryCache, ec)) {
-      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache->c_str());
+      LogMan::Msg::DFmt("Couldn't create EntryCache directory: '{}'", *EntryCache);
    }
  }

@@ -57,51 +57,183 @@ struct X80SoftFloat {

  // Ops
  static X80SoftFloat FADD(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    faddp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    return extF80_add(lhs, rhs);
+#endif
  }

  static X80SoftFloat FSUB(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fsubp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    return extF80_sub(lhs, rhs);
+#endif
  }

  static X80SoftFloat FMUL(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fmulp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    return extF80_mul(lhs, rhs);
+#endif
  }

  static X80SoftFloat FDIV(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fdivp;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    return extF80_div(lhs, rhs);
+#endif
  }

  static X80SoftFloat FREM(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    X80SoftFloat Rem = extF80_rem(lhs, rhs);
-    if (SignBit(Rem)) {
-      Rem = extF80_add(Rem, rhs);
-    }
-    else {
-      Rem.Sign = SignBit(lhs);
-    }
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fprem;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");

-    return Rem;
+    return Result;
+#else
+    return extF80_rem(lhs, rhs);
+#endif
  }

  static X80SoftFloat FREM1(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fprem1;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    return extF80_rem(lhs, rhs);
+#endif
  }

  static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) {
    return extF80_roundToInt(lhs, softfloat_roundingMode, false);
  }

+  static X80SoftFloat FRNDINT(X80SoftFloat const &lhs, uint_fast8_t RoundMode) {
+    return extF80_roundToInt(lhs, RoundMode, false);
+  }
+
  static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fxtract;
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    X80SoftFloat Tmp = lhs;
    Tmp.Exponent = 0x3FFF;
    Tmp.Sign = lhs.Sign;
    return Tmp;
+#endif
  }

  static X80SoftFloat FXTRACT_EXP(X80SoftFloat const &lhs) {
+#if defined(DEBUG_X86_FLOAT)
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fxtract;
+    ffreep %%st(0);
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    int32_t TrueExp = lhs.Exponent - ExponentBias;
    return i32_to_extF80(TrueExp);
+#endif
  }

  static void FCMP(X80SoftFloat const &lhs, X80SoftFloat const &rhs, bool *eq, bool *lt, bool *nan) {
@@ -111,62 +243,190 @@ struct X80SoftFloat {
  }

  static X80SoftFloat FSCALE(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FSCALE which may have accuracy problems");
-    X80SoftFloat Int = FRNDINT(rhs);
+    WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st1
+    fldt %[lhs]; # st0
+    fscale; # st0 = st0 * 2^(rdint(st1))
+    fstpt %[result];
+    ffreep %%st(0);
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
+    X80SoftFloat Int = FRNDINT(rhs, softfloat_round_minMag);
    BIGFLOAT Src2_d = Int;
    Src2_d = exp2l(Src2_d);
    X80SoftFloat Src2_X80 = Src2_d;
    X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
    return Result;
+#endif
  }

  static X80SoftFloat F2XM1(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used F2XM1 which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    f2xm1; # st0 = 2^st(0) - 1
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
    BIGFLOAT Src1_d = lhs;
    BIGFLOAT Result = exp2l(Src1_d);
    Result -= 1.0;
    return Result;
+#endif
  }

  static X80SoftFloat FYL2X(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FYL2X which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[rhs]; # st(1)
+    fldt %[lhs]; # st(0)
+    fyl2x; # st(1) * log2l(st(0))
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    BIGFLOAT Src1_d = lhs;
    BIGFLOAT Src2_d = rhs;
    BIGFLOAT Tmp = Src2_d * log2l(Src1_d);
    return Tmp;
+#endif
  }

  static X80SoftFloat FATAN(X80SoftFloat const &lhs, X80SoftFloat const &rhs) {
-    WARN_ONCE("x87: Application used FATAN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs];
+    fldt %[rhs];
+    fpatan;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    , [rhs] "m" (rhs)
+    : "st", "st(1)");
+
+    return Result;
+#else
    BIGFLOAT Src1_d = lhs;
    BIGFLOAT Src2_d = rhs;
    BIGFLOAT Tmp = atan2l(Src1_d, Src2_d);
    return Tmp;
+#endif
  }

  static X80SoftFloat FTAN(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FTAN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fptan;
+    ffreep %%st(0);
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
    BIGFLOAT Src_d = lhs;
    Src_d = tanl(Src_d);
    return Src_d;
+#endif
  }

  static X80SoftFloat FSIN(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FSIN which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fsin;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
    BIGFLOAT Src_d = lhs;
    Src_d = sinl(Src_d);
    return Src_d;
+#endif
  }

  static X80SoftFloat FCOS(X80SoftFloat const &lhs) {
-    WARN_ONCE("x87: Application used FCOS which may have accuracy problems");
+    WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems");
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fcos;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
    BIGFLOAT Src_d = lhs;
    Src_d = cosl(Src_d);
    return Src_d;
+#endif
  }

  static X80SoftFloat FSQRT(X80SoftFloat const &lhs) {
+#ifdef DEBUG_X86_FLOAT
+    BIGFLOAT Result;
+    asm (R"(
+    fninit;
+    fldt %[lhs]; # st0
+    fsqrt;
+    fstpt %[result];
+    )"
+    : [result] "=m" (Result)
+    : [lhs] "m" (lhs)
+    : "st");
+
+    return Result;
+#else
    return extF80_sqrt(lhs);
+#endif
  }

  operator float() const {
@@ -0,0 +1,29 @@
+#pragma once
+#include <string>
+
+namespace FEXCore::StringUtils {
+  // Trim the left side of the string of whitespace and new lines
+  [[maybe_unused]] static std::string LeftTrim(std::string String, std::string TrimTokens = " \t\n\r") {
+    size_t pos = std::string::npos;
+    if ((pos = String.find_first_not_of(TrimTokens)) != std::string::npos) {
+      String.erase(0, pos);
+    }
+
+    return String;
+  }
+
+  // Trim the right side of the string of whitespace and new lines
+  [[maybe_unused]] static std::string RightTrim(std::string String, std::string TrimTokens = " \t\n\r") {
+    size_t pos = std::string::npos;
+    if ((pos = String.find_last_not_of(TrimTokens)) != std::string::npos) {
+      String.erase(String.begin() + pos + 1, String.end());
+    }
+
+    return String;
+  }
+
+  // Trim both the left and right of the string of whitespace and new lines
+  [[maybe_unused]] static std::string Trim(std::string String, std::string TrimTokens = " \t\n\r") {
+    return RightTrim(LeftTrim(String, TrimTokens), TrimTokens);
+  }
+}
@@ -1,4 +1,5 @@
 #include "Common/StringConv.h"
+#include "Common/StringUtils.h"
 #include "Common/Paths.h"
 #include "Utils/FileLoading.h"

@@ -74,14 +75,14 @@ namespace JSON {

    json_t const *json = json_createWithPool(&Data.at(0), &Pool.PoolObject);
    if (!json) {
-      LogMan::Msg::E("Couldn't create json");
+      LogMan::Msg::EFmt("Couldn't create json");
      return;
    }

    json_t const* ConfigList = json_getProperty(json, "Config");

    if (!ConfigList) {
-      LogMan::Msg::E("Couldn't get config list");
+      LogMan::Msg::EFmt("Couldn't get config list");
      return;
    }

@@ -92,12 +93,12 @@ namespace JSON {
      const char* ConfigString = json_getValue(ConfigItem);

      if (!ConfigName) {
-        LogMan::Msg::E("Couldn't get config name");
+        LogMan::Msg::EFmt("Couldn't get config name");
        return;
      }

      if (!ConfigString) {
-        LogMan::Msg::E("Couldn't get ConfigString for '%s'", ConfigName);
+        LogMan::Msg::EFmt("Couldn't get ConfigString for '{}'", ConfigName);
        return;
      }

@@ -173,7 +174,7 @@ namespace JSON {
    if (!Global &&
        !std::filesystem::exists(ConfigFile, ec) &&
        !std::filesystem::create_directories(ConfigFile, ec)) {
-      LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigFile.c_str());
+      LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
      // Let's go local in this case
      return "./" + Filename + ".json";
    }
@@ -370,29 +371,6 @@ namespace JSON {
    return {};
  }

-  std::string ltrim(std::string String) {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_first_not_of(" \t\n\r")) != std::string::npos) {
-      String.erase(0, pos);
-    }
-
-    return String;
-  }
-
-  std::string rtrim(std::string String) {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_last_not_of(" \t\n\r")) != std::string::npos) {
-      String.erase(String.begin() + pos + 1, String.end());
-    }
-
-    return String;
-  }
-
-  std::string trim(std::string String) {
-    return rtrim(ltrim(String));
-  }
-
-
  std::string FindContainerPrefix() {
    // We only support pressure-vessel at the moment
    const static std::string ContainerManager = "/run/host/container-manager";
@@ -401,7 +379,7 @@ namespace JSON {
      if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
        // Trim the whitespace, may contain a newline
        std::string ManagerStr = Manager.data();
-        ManagerStr = trim(ManagerStr);
+        ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
        if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
          // We are running inside of pressure vessel
          // Our $CMAKE_INSTALL_PREFIX paths are now inside of /run/host/$CMAKE_INSTALL_PREFIX
@@ -416,7 +394,9 @@ namespace JSON {
    Meta->Load();

    // Do configuration option fix ups after everything is reloaded
-    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THREADS)) {
+    {
+      // Always fix up the number of threads and create the configuration
+      // Otherwise the application could receive zero as the number of threads
      FEX_CONFIG_OPT(Cores, THREADS);
      if (Cores == 0) {
        // When the number of emulated CPU cores is zero then auto detect
@@ -424,6 +404,25 @@ namespace JSON {
      }
    }

+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CORE)) {
+      // Sanitize Core option
+      FEX_CONFIG_OPT(Core, CORE);
+#if (_M_X86_64)
+      constexpr uint32_t MaxCoreNumber = 2;
+#else
+      constexpr uint32_t MaxCoreNumber = 1;
+#endif
+#ifdef INTERPRETER_ENABLED
+      constexpr uint32_t MinCoreNumber = 0;
+#else
+      constexpr uint32_t MinCoreNumber = 1;
+#endif
+      if (Core > MaxCoreNumber || Core < MinCoreNumber) {
+        // Sanitize the core option by setting the core to the JIT if invalid
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, std::to_string(FEXCore::Config::CONFIG_IRJIT));
+      }
+    }
+
    std::string ContainerPrefix { FindContainerPrefix() };
    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, std::string PathName) {
      auto NewPath = ExpandPath(ContainerPrefix, PathName);
@@ -32,7 +32,7 @@
      },
      "Threads": {
        "Type": "uint32",
-        "Default": "1",
+        "Default": "0",
        "ShortArg": "T",
        "Desc": [
          "Number of physical hardware threads to tell the process we have.",
@@ -201,6 +201,15 @@
          "Disables logging"
        ]
      },
+      "OutputSocket": {
+        "Type": "str",
+        "Default": "",
+        "Desc": [
+          "Socket to connect to",
+          "eg: localhost:8087",
+          "If set will override the OutputLog location"
+        ]
+      },
      "OutputLog": {
        "Type": "str",
        "Default": "stderr",
@@ -51,7 +51,7 @@ namespace FEXCore::Context {
    CTX->CustomExitHandler = std::move(handler);
  }

-  ExitHandler GetExitHandler(FEXCore::Context::Context *CTX) {
+  ExitHandler GetExitHandler(const FEXCore::Context::Context *CTX) {
    return CTX->CustomExitHandler;
  }

@@ -71,23 +71,23 @@ namespace FEXCore::Context {
    return CTX->RunUntilExit();
  }

-  int GetProgramStatus(FEXCore::Context::Context *CTX) {
+  int GetProgramStatus(const FEXCore::Context::Context *CTX) {
    return CTX->GetProgramStatus();
  }

-  FEXCore::Context::ExitReason GetExitReason(FEXCore::Context::Context *CTX) {
+  FEXCore::Context::ExitReason GetExitReason(const FEXCore::Context::Context *CTX) {
    return CTX->ParentThread->ExitReason;
  }

-  bool IsDone(FEXCore::Context::Context *CTX) {
+  bool IsDone(const FEXCore::Context::Context *CTX) {
    return CTX->IsPaused();
  }

-  void GetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
+  void GetCPUState(const FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
  }

-  void SetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
+  void SetCPUState(FEXCore::Context::Context *CTX, const FEXCore::Core::CPUState *State) {
    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
  }

@@ -115,11 +115,11 @@ namespace FEXCore::Context {
  }

  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-      CTX->RegisterHostSignalHandler(Signal, Func, Required);
+      CTX->RegisterHostSignalHandler(Signal, std::move(Func), Required);
  }

  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    CTX->RegisterFrontendHostSignalHandler(Signal, Func, Required);
+    CTX->RegisterFrontendHostSignalHandler(Signal, std::move(Func), Required);
  }

  FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
@@ -162,12 +162,20 @@ namespace FEXCore::Context {
    return CTX->CPUID.RunFunction(Function, Leaf);
  }

-  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
-    CTX->AOTIRLoader = CacheReader;
+  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+    return CTX->CPUID.RunFunctionName(Function, Leaf, CPU);
  }

-  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter) {
-    CTX->AOTIRWriter = CacheWriter;
+  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
+    CTX->SetAOTIRLoader(CacheReader);
+  }
+
+  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
+    CTX->SetAOTIRWriter(CacheWriter);
+  }
+
+  void SetAOTIRRenamer(FEXCore::Context::Context *CTX, std::function<void(const std::string&)> CacheRenamer) {
+    CTX->SetAOTIRRenamer(CacheRenamer);
  }

  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
@@ -4,6 +4,7 @@
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/HostFeatures.h"
 #include "Interface/Core/X86HelperGen.h"
+#include "Interface/IR/AOTIR.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
@@ -57,38 +58,6 @@ namespace FEXCore::Context {
    MODE_SINGLESTEP = 1,
  };

-  struct AOTIRInlineEntry {
-    uint64_t GuestHash;
-    uint64_t GuestLength;
-
-    /* RAData followed by IRData */
-    uint8_t InlineData[0];
-
-    IR::RegisterAllocationData *GetRAData();
-    IR::IRListView *GetIRData();
-  };
-
-  struct AOTIRInlineIndexEntry {
-    uint64_t GuestStart;
-    uint64_t DataOffset;
-  };
-
-  struct AOTIRInlineIndex {
-    uint64_t Count;
-    uint64_t DataBase;
-    AOTIRInlineIndexEntry Entries[0];
-
-    AOTIRInlineEntry *Find(uint64_t GuestStart);
-    AOTIRInlineEntry *GetInlineEntry(uint64_t DataOffset);
-  };
-
-  struct AOTIRCaptureCacheEntry {
-    std::unique_ptr<std::ostream> Stream;
-    std::map<uint64_t, uint64_t> Index;
-
-    void AppendAOTIRCaptureCache(uint64_t GuestRIP, uint64_t Start, uint64_t Length, uint64_t Hash, FEXCore::IR::IRListView *IRList, FEXCore::IR::RegisterAllocationData *RAData);
-  };
-
  struct Context {
    friend class FEXCore::HLE::SyscallHandler;
  #ifdef JIT_ARM64
@@ -156,32 +125,6 @@ namespace FEXCore::Context {
    CustomCPUFactoryType CustomCPUFactory;
    FEXCore::Context::ExitHandler CustomExitHandler;

-    struct AOTIRCacheEntry {
-      AOTIRInlineIndex *Array;
-      void *mapping;
-      size_t size;
-    };
-
-    std::unordered_map<std::string, AOTIRCacheEntry> AOTIRCache;
-    std::function<int(const std::string&)> AOTIRLoader;
-    std::function<std::unique_ptr<std::ostream>(const std::string&)> AOTIRWriter;
-    std::unordered_map<std::string, AOTIRCaptureCacheEntry> AOTIRCaptureCache;
-
-    struct AddrToFileEntry {
-      uint64_t Start;
-      uint64_t Len;
-      uint64_t Offset;
-      std::string fileid;
-      std::string filename;
-      void *CachedFileEntry;
-      bool ContainsCode;
-    };
-
-    using AddrToFileMapType = std::map<uint64_t, AddrToFileEntry>;
-    AddrToFileMapType AddrToFile;
-    std::map<std::string, std::string> FilesWithCode;
-
-    AddrToFileMapType::iterator FindAddrForFile(uint64_t Entry, uint64_t Length);
 #ifdef BLOCKSTATS
    std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
 #endif
@@ -253,9 +196,6 @@ namespace FEXCore::Context {
    // same as CompileBlock, but aborts on failure
    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);

-    bool LoadAOTIRCache(int streamfd);
-    void FinalizeAOTIRCache();
-    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer);
    /**
     * @brief Initializes the JIT compilers for the thread
     *
@@ -337,6 +277,26 @@ namespace FEXCore::Context {
    // Public for threading
    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);

+    void FinalizeAOTIRCache() {
+      IRCaptureCache.FinalizeAOTIRCache();
+    }
+
+    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
+      IRCaptureCache.WriteFilesWithCode(Writer);
+    }
+
+    void SetAOTIRLoader(std::function<int(const std::string&)> CacheReader) {
+      IRCaptureCache.SetAOTIRLoader(CacheReader);
+    }
+
+    void SetAOTIRWriter(std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
+      IRCaptureCache.SetAOTIRWriter(CacheWriter);
+    }
+
+    void SetAOTIRRenamer(std::function<void(const std::string&)> CacheRenamer) {
+      IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
+    }
+
  protected:
    void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread, bool AlsoClearIRCache);

@@ -362,13 +322,7 @@ namespace FEXCore::Context {
    std::mutex ExitMutex;
    std::unique_ptr<GdbServer> DebugServer;

-    std::shared_mutex AOTIRCacheLock;
-    std::shared_mutex AOTIRCaptureCacheWriteoutLock;
-    std::atomic<bool> AOTIRCaptureCacheWriteoutFlusing;
-
-    std::queue<std::function<void()>> AOTIRCaptureCacheWriteoutQueue;
-    void AOTIRCaptureCacheWriteoutQueue_Flush();
-    void AOTIRCaptureCacheWriteoutQueue_Append(const std::function<void()> &fn);
+    IR::AOTIRCaptureCache IRCaptureCache;

    bool StartPaused = false;
    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
@@ -535,7 +535,6 @@ uint64_t HandleCASPAL_ARMv8(void *_ucontext, void *_info, uint32_t Instr) {
 }

 bool HandleAtomicVectorStore(void *_ucontext, void *_info, uint32_t Instr) {
-  mcontext_t* mcontext = &reinterpret_cast<ucontext_t*>(_ucontext)->uc_mcontext;
  siginfo_t* info = reinterpret_cast<siginfo_t*>(_info);

  if (info->si_code != BUS_ADRALN) {
@@ -1437,9 +1436,8 @@ bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
        DesiredFunction = SWAPDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", Op);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", Op);
        return false;
-        break;
    }

    auto Res = DoCAS16<true>(
@@ -1499,9 +1497,8 @@ bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
        DesiredFunction = SWAPDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", Op);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", Op);
        return false;
-        break;
    }

    auto Res = DoCAS32<true>(
@@ -1561,9 +1558,8 @@ bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
        DesiredFunction = SWAPDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", Op);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", Op);
        return false;
-        break;
    }

    auto Res = DoCAS64<true>(
@@ -1744,8 +1740,8 @@ static uint64_t HandleCAS_NoAtomics(void *_ucontext, void *_info)
     if ((NextInstr & FEXCore::ArchHelpers::Arm64::STLXR_MASK) == FEXCore::ArchHelpers::Arm64::STLXR_INST) {
       #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
       // Just double check that the memory destination matches
-       uint32_t StoreAddressReg = GetRnReg(NextInstr);
-       LOGMAN_THROW_A(StoreAddressReg == AddressReg, "StoreExclusive memory register didn't match the store exclusive register");
+       const uint32_t StoreAddressReg = GetRnReg(NextInstr);
+       LOGMAN_THROW_A_FMT(StoreAddressReg == AddressReg, "StoreExclusive memory register didn't match the store exclusive register");
       #endif
       DesiredReg = GetRdReg(NextInstr);
     }
@@ -1865,8 +1861,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::STLXR_MASK) == FEXCore::ArchHelpers::Arm64::STLXR_INST) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
      // Just double check that the memory destination matches
-      uint32_t StoreAddressReg = GetRnReg(NextInstr);
-      LOGMAN_THROW_A(StoreAddressReg == AddressReg, "StoreExclusive memory register didn't match the store exclusive register");
+      const uint32_t StoreAddressReg = GetRnReg(NextInstr);
+      LOGMAN_THROW_A_FMT(StoreAddressReg == AddressReg, "StoreExclusive memory register didn't match the store exclusive register");
 #endif
      uint32_t StatusReg = GetRmReg(NextInstr);
      uint32_t StoreResultReg = GetRdReg(NextInstr);
@@ -1885,7 +1881,7 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
      break;
    }
    else {
-      LogMan::Msg::A("Unknown instruction 0x%08x", NextInstr);
+      LogMan::Msg::AFmt("Unknown instruction 0x{:08x}", NextInstr);
    }
  }

@@ -1951,9 +1947,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
        DesiredFunction = NEGDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
        return false;
-        break;
    }

    auto Res = DoCAS16<DoRetry>(
@@ -2028,9 +2023,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
        DesiredFunction = NEGDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
        return false;
-        break;
    }

    auto Res = DoCAS32<DoRetry>(
@@ -2105,9 +2099,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
        DesiredFunction = NEGDesired;
        break;
      default:
-        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
        return false;
-        break;
    }

    auto Res = DoCAS64<DoRetry>(
@@ -1,7 +1,9 @@
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Context/Context.h"

-#include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>

 #include "aarch64/cpu-aarch64.h"
 #include "cpu-features.h"
@@ -14,53 +16,44 @@ namespace FEXCore::CPU {
 #define STATE x28

 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
-Arm64Emitter::Arm64Emitter(size_t size) : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode) {
+Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size) : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode) {
  CPU.SetUp();

  auto Features = vixl::CPUFeatures::InferFromOS();
-  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
-  // RCPC is bugged on Snapdragon 865
-  // Causes glibc cond16 test to immediately throw assert
-  // __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
-  SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
-
-  if (SupportsAtomics) {
+  if (ctx->HostFeatures.SupportsAtomics) {
    // Hypervisor can hide this on the c630?
    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
  }

  SetCPUFeatures(Features);
-
-  if (!SupportsAtomics) {
-    WARN_ONCE("Host CPU doesn't support atomics. Expect bad performance");
-  }
-
-#ifdef _M_ARM_64
-  // We need to get the CPU's cache line size
-  // We expect sane targets that have correct cacheline sizes across clusters
-  uint64_t CTR;
-  __asm volatile ("mrs %[ctr], ctr_el0"
-    : [ctr] "=r"(CTR));
-
-  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
-  ICacheLineSize = 4 << (CTR & 0xF);
-#endif
 }

-void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
+void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad) {
  bool Is64Bit = Reg.IsX();
  int Segments = Is64Bit ? 4 : 2;

  if (Is64Bit && ((~Constant)>> 16) == 0) {
    movn(Reg, (~Constant) & 0xFFFF);
+
+    if (NOPPad) {
+      nop(); nop(); nop();
+    }
    return;
  }

+  int NumMoves = 1;
  movz(Reg, (Constant) & 0xFFFF, 0);
  for (int i = 1; i < Segments; ++i) {
    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
    if (Part) {
      movk(Reg, Part, i * 16);
+      ++NumMoves;
+    }
+  }
+
+  if (NOPPad) {
+    for (int i = NumMoves; i < Segments; ++i) {
+      nop();
    }
  }
 }
@@ -69,7 +62,7 @@ void Arm64Emitter::PushCalleeSavedRegisters() {
  // We need to save pairs of registers
  // We save r19-r30
  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
    {x19, x20},
    {x21, x22},
    {x23, x24},
@@ -132,7 +125,7 @@ void Arm64Emitter::PopCalleeSavedRegisters() {
  }

  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
    {x29, x30},
    {x27, x28},
    {x25, x26},
@@ -147,26 +140,76 @@ void Arm64Emitter::PopCalleeSavedRegisters() {
 }


-void Arm64Emitter::SpillStaticRegs() {
+void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
  if (StaticRegisterAllocation()) {
    for (size_t i = 0; i < SRA64.size(); i+=2) {
-        stp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      auto Reg1 = SRA64[i];
+      auto Reg2 = SRA64[i+1];
+      if (((1U << Reg1.GetCode()) & GPRSpillMask) &&
+          ((1U << Reg2.GetCode()) & GPRSpillMask)) {
+        stp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg1.GetCode()) & GPRSpillMask)) {
+        str(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg2.GetCode()) & GPRSpillMask)) {
+        str(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
+      }
    }

-    for (size_t i = 0; i < SRAFPR.size(); i+=2) {
-      stp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+    if (FPRs) {
+      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+        auto Reg1 = SRAFPR[i];
+        auto Reg2 = SRAFPR[i+1];
+
+        if (((1U << Reg1.GetCode()) & FPRSpillMask) &&
+            ((1U << Reg2.GetCode()) & FPRSpillMask)) {
+          stp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+        }
+        else if (((1U << Reg1.GetCode()) & FPRSpillMask)) {
+          str(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+        }
+        else if (((1U << Reg2.GetCode()) & FPRSpillMask)) {
+          str(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i+1][0])));
+        }
+      }
    }
  }
 }

-void Arm64Emitter::FillStaticRegs() {
+void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) {
  if (StaticRegisterAllocation()) {
    for (size_t i = 0; i < SRA64.size(); i+=2) {
-      ldp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      auto Reg1 = SRA64[i];
+      auto Reg2 = SRA64[i+1];
+      if (((1U << Reg1.GetCode()) & GPRFillMask) &&
+          ((1U << Reg2.GetCode()) & GPRFillMask)) {
+        ldp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg1.GetCode()) & GPRFillMask)) {
+        ldr(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+      }
+      else if (((1U << Reg2.GetCode()) & GPRFillMask)) {
+        ldr(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
+      }
    }

-    for (size_t i = 0; i < SRAFPR.size(); i+=2) {
-      ldp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+    if (FPRs) {
+      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+        auto Reg1 = SRAFPR[i];
+        auto Reg2 = SRAFPR[i+1];
+
+        if (((1U << Reg1.GetCode()) & FPRFillMask) &&
+            ((1U << Reg2.GetCode()) & FPRFillMask)) {
+          ldp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+        }
+        else if (((1U << Reg1.GetCode()) & FPRFillMask)) {
+          ldr(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+        }
+        else if (((1U << Reg2.GetCode()) & FPRFillMask)) {
+          ldr(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i+1][0])));
+        }
+      }
    }
  }
 }
@@ -58,15 +58,18 @@ const std::array<aarch64::VRegister, 12> RAFPR = {
 // be used by both Arm64 JIT and ARM64 Dispatcher
 class Arm64Emitter : public vixl::aarch64::Assembler {
 protected:
-  Arm64Emitter(size_t size);
+  Arm64Emitter(FEXCore::Context::Context *ctx, size_t size);

  vixl::aarch64::CPU CPU;
-  bool SupportsAtomics{};
-  bool SupportsRCPC{};
+  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad = false);
+  void SpillStaticRegs(bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
+  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);

-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-  void SpillStaticRegs();
-  void FillStaticRegs();
+  static constexpr uint32_t CALLER_GPR_MASK = 0b0011'1111'1111'1111'1111;
+
+  // This isn't technically true because the lower 64-bits of v8..v15 are callee saved
+  // We can't guarantee only the lower 64bits are used so flush everything
+  static constexpr uint32_t CALLER_FPR_MASK = ~0U;

  void PushDynamicRegsAndLR();
  void PopDynamicRegsAndLR();
@@ -79,9 +82,6 @@ protected:

  uint32_t SpillSlots{};

-  uint32_t DCacheLineSize{};
-  uint32_t ICacheLineSize{};
-
  FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
 };

@@ -12,15 +12,15 @@ namespace FEXCore::ArchHelpers::Arm64 {
 // Obvously such a configuration can't do the actual arm64-specific stuff

 bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr) {
-    ERROR_AND_DIE("HandleCASPAL Not Implemented");
+    ERROR_AND_DIE_FMT("HandleCASPAL Not Implemented");
 }

 bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr) {
-    ERROR_AND_DIE("HandleCASAL Not Implemented");
+    ERROR_AND_DIE_FMT("HandleCASAL Not Implemented");
 }

 bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
-    ERROR_AND_DIE("HandleAtomicMemOp Not Implemented");
+    ERROR_AND_DIE_FMT("HandleAtomicMemOp Not Implemented");
 }
 #endif

@@ -13,17 +13,27 @@

 namespace FEXCore::ArchHelpers::Context {

+enum ContextFlags : uint32_t {
+  CONTEXT_FLAG_INJIT = (1U << 0),
+  CONTEXT_FLAG_32BIT = (1U << 1),
+};
+
 struct X86ContextBackup {
  // Host State
  // RIP and RSP is stored in GPRs here
  uint64_t GPRs[23];
  FEXCore::x86_64::_libc_fpstate FPRState;
  uint64_t sa_mask;
+  bool FaultToTopAndGeneratedException;

  // Guest state
  int Signal;
+  uint32_t Flags;
+  uint64_t OriginalRIP;
+  uint64_t FPStateLocation;
+  uint64_t UContextLocation;
+  uint64_t SigInfoLocation;
  FEXCore::Core::CPUState GuestState;
-
  static constexpr int RedZoneSize = 128;
 };

@@ -37,9 +47,15 @@ struct ArmContextBackup {
  uint32_t FPCR;
  __uint128_t FPRs[32];
  uint64_t sa_mask;
+  bool FaultToTopAndGeneratedException;

  // Guest state
  int Signal;
+  uint32_t Flags;
+  uint64_t OriginalRIP;
+  uint64_t FPStateLocation;
+  uint64_t UContextLocation;
+  uint64_t SigInfoLocation;
  FEXCore::Core::CPUState GuestState;

  // Arm64 doesn't have a red zone
@@ -108,7 +124,7 @@ static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
 static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
  auto MContext = GetMContext(ucontext);
  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&MContext->__reserved[0]);
-  LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+  LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);

  return HostState->FPRs[id];
 }
@@ -127,7 +143,7 @@ static inline void BackupContext(void* ucontext, T *Backup) {

    // Host FPR state starts at _mcontext->reserved[0];
    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
    Backup->FPSR = HostState->FPSR;
    Backup->FPCR = HostState->FPCR;
    memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
@@ -135,7 +151,8 @@ static inline void BackupContext(void* ucontext, T *Backup) {
    // Save the signal mask so we can restore it
    memcpy(&Backup->sa_mask, &_ucontext->uc_sigmask, sizeof(uint64_t));
  } else {
-      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
  }
 }

@@ -146,7 +163,7 @@ static inline void RestoreContext(void* ucontext, T *Backup) {
   auto _mcontext = GetMContext(ucontext);

    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
    memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t));
    HostState->FPCR = Backup->FPCR;
    HostState->FPSR = Backup->FPSR;
@@ -160,7 +177,8 @@ static inline void RestoreContext(void* ucontext, T *Backup) {
    // Restore the signal mask now
    memcpy(&_ucontext->uc_sigmask, &Backup->sa_mask, sizeof(uint64_t));
  } else {
-      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
  }
 }

@@ -193,15 +211,15 @@ static inline void SetState(void* ucontext, uint64_t val) {
 }

 static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
-  ERROR_AND_DIE("Not impelented for x86 host");
+  ERROR_AND_DIE_FMT("Not impelented for x86 host");
 }

 static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
-  ERROR_AND_DIE("Not impelented for x86 host");
+  ERROR_AND_DIE_FMT("Not impelented for x86 host");
 }

 static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
-  ERROR_AND_DIE("Not implemented for x86 host");
+  ERROR_AND_DIE_FMT("Not implemented for x86 host");
 }

 using ContextBackup = X86ContextBackup;
@@ -220,7 +238,8 @@ static inline void BackupContext(void* ucontext, T *Backup) {
    // Save the signal mask so we can restore it
    memcpy(&Backup->sa_mask, &_ucontext->uc_sigmask, sizeof(uint64_t));
  } else {
-    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
  }
 }

@@ -238,7 +257,8 @@ static inline void RestoreContext(void* ucontext, T *Backup) {
    // Restore the signal mask now
    memcpy(&_ucontext->uc_sigmask, &Backup->sa_mask, sizeof(uint64_t));
  } else {
-    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+    // This must be a runtime error
+    ERROR_AND_DIE_FMT("Wrong context type");
  }
 }

@@ -27,7 +27,7 @@ namespace FEXCore {
             << std::endl;
    }
    Output.close();
-    LogMan::Msg::D("Dumped %d blocks of sampling data", SamplingMap.size());
+    LogMan::Msg::DFmt("Dumped {} blocks of sampling data", SamplingMap.size());
  }

  BlockSamplingData::BlockData *BlockSamplingData::GetBlockData(uint64_t RIP) {
@@ -5,14 +5,16 @@ desc: Handles presented capability bits for guest cpu
 $end_info$
 */

-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CPUID.h>
 #include "Common/StringConv.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/HostFeatures.h"
 #include "Utils/FileLoading.h"

+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Core/CPUID.h>
+#include <FEXHeaderUtils/Syscalls.h>
+
 #include "git_version.h"

 #include <cstring>
@@ -21,6 +23,66 @@ $end_info$
 #endif

 namespace FEXCore {
+namespace ProductNames {
+#ifdef _M_ARM_64
+  static const char ARM_UNKNOWN[] = "Unknown ARM CPU";
+  static const char ARM_A57[] = "Cortex-A57";
+  static const char ARM_A72[] = "Cortex-A72";
+  static const char ARM_A73[] = "Cortex-A73";
+  static const char ARM_A75[] = "Cortex-A75";
+  static const char ARM_A76[] = "Cortex-A76";
+  static const char ARM_A76AE[] = "Cortex-A76AE";
+  static const char ARM_V1[] = "Neoverse V1";
+  static const char ARM_A77[] = "Cortex-A77";
+  static const char ARM_A78[] = "Cortex-A78";
+  static const char ARM_A78AE[] = "Cortex-A78AE";
+  static const char ARM_A78C[] = "Cortex-A78C";
+  static const char ARM_A710[] = "Cortex-A710";
+  static const char ARM_X1[] = "Cortex-X1";
+  static const char ARM_X2[] = "Cortex-X2";
+  static const char ARM_N1[] = "Neoverse N1";
+  static const char ARM_N2[] = "Neoverse N2";
+  static const char ARM_E1[] = "Neoverse E1";
+  static const char ARM_A35[] = "Cortex-A35";
+  static const char ARM_A53[] = "Cortex-A53";
+  static const char ARM_A55[] = "Cortex-A55";
+  static const char ARM_A65[] = "Cortex-A65";
+  static const char ARM_A510[] = "Cortex-A510";
+
+  static const char ARM_Kryo200[] = "Kryo 2xx";
+  static const char ARM_Kryo300[] = "Kryo 3xx";
+  static const char ARM_Kryo400[] = "Kryo 4xx/5xx";
+
+  static const char ARM_Kryo200S[] = "Kryo 2xx S";
+  static const char ARM_Kryo300S[] = "Kryo 3xx S";
+  static const char ARM_Kryo400S[] = "Kryo 4xx/5xx S";
+
+  static const char ARM_Denver[] = "Nvidia Denver";
+  static const char ARM_Carmel[] = "Nvidia Carmel";
+
+  static const char ARM_Firestorm[] = "Apple Firestorm";
+  static const char ARM_Icestorm[] = "Apple Icestorm";
+#else
+  static const char UNKNOWN[] = "Unknown CPU";
+#endif
+}
+
+static uint32_t GetCPUID() {
+  uint32_t CPU{};
+  FHU::Syscalls::getcpu(&CPU, nullptr);
+  return CPU;
+}
+
+static uint32_t CalculateNumberOfCPUs() {
+  size_t CPUs = 1;
+
+  while(std::filesystem::exists("/sys/devices/system/cpu/cpu" + std::to_string(CPUs))) {
+    CPUs++;
+  }
+
+  return CPUs;
+}
+
 constexpr uint32_t SUPPORTS_AVX = 0;
 // #define CPUID_AMD
 #ifdef CPUID_AMD
@@ -49,60 +111,242 @@ static uint32_t GetCycleCounterFrequency() {
  return Result;
 }

-static bool GetHostHybridFlag() {
-  int MaxCPUs = 64;
-  size_t AllocSize = CPU_ALLOC_SIZE(MaxCPUs);
-  cpu_set_t *Set = CPU_ALLOC(MaxCPUs);
-  CPU_ZERO_S(AllocSize, Set);
+void CPUIDEmu::SetupHostHybridFlag() {
+  size_t CPUs = CalculateNumberOfCPUs();
+  PerCPUData.resize(CPUs);

-  int Result{};
-  for (;;) {
-    Result = sched_getaffinity(0, AllocSize, Set);
-    if (Result == 0 ||
-        (Result == -1 && errno != EINVAL)) {
-      break;
-    }
-
-    MaxCPUs <<= 1;
-    CPU_FREE(Set);
-    Set = CPU_ALLOC(MaxCPUs);
-    AllocSize = CPU_ALLOC_SIZE(MaxCPUs);
-    CPU_ZERO_S(AllocSize, Set);
-  }
-
-  if (Result != 0) {
-    return false;
-  }
-
-  int CPUs = CPU_COUNT_S(AllocSize, Set);
-
-  bool Hybrid = false;
  uint64_t MIDR{};
-  for (int i = 0; i < CPUs; ++i) {
-    if (CPU_ISSET_S(i, AllocSize, Set)) {
-      std::error_code ec{};
-      std::string MIDRPath = "/sys/devices/system/cpu/cpu" + std::to_string(i) + "/regs/identification/midr_el1";
-      if (std::filesystem::exists(MIDRPath, ec)) {
-        std::vector<char> Data{};
-        // Needs to be a fixed size since depending on kernel it will try to read a full page of data and fail
-        // Only read 18 bytes for a 64bit value prefixed with 0x
-        if (FEXCore::FileLoading::LoadFile(Data, MIDRPath, 18)) {
-          uint64_t NewMIDR{};
-          if (FEXCore::StrConv::Conv(&Data.at(0), &NewMIDR)) {
-            if (MIDR != 0 && MIDR != NewMIDR) {
-              // CPU mismatch, claim hybrid
-              Hybrid = true;
-              break;
-            }
-            MIDR = NewMIDR;
+  for (size_t i = 0; i < CPUs; ++i) {
+    std::error_code ec{};
+    std::string MIDRPath = "/sys/devices/system/cpu/cpu" + std::to_string(i) + "/regs/identification/midr_el1";
+    if (std::filesystem::exists(MIDRPath, ec)) {
+      std::vector<char> Data{};
+      // Needs to be a fixed size since depending on kernel it will try to read a full page of data and fail
+      // Only read 18 bytes for a 64bit value prefixed with 0x
+      if (FEXCore::FileLoading::LoadFile(Data, MIDRPath, 18)) {
+        uint64_t NewMIDR{};
+        std::string_view MIDRView(&Data.at(0), 18);
+        if (FEXCore::StrConv::Conv(MIDRView, &NewMIDR)) {
+          if (MIDR != 0 && MIDR != NewMIDR) {
+            // CPU mismatch, claim hybrid
+            Hybrid = true;
          }
+
+          // Truncate to 32-bits, top 32-bits are all reserved in MIDR
+          PerCPUData[i].ProductName = ProductNames::ARM_UNKNOWN;
+          PerCPUData[i].MIDR = NewMIDR;
+          MIDR = NewMIDR;
        }
      }
    }
  }

-  CPU_FREE(Set);
-  return Hybrid;
+  struct CPUMIDR {
+    uint8_t Implementer;
+    uint16_t Part;
+    bool DefaultBig; // Defaults to a big core
+    const char *ProductName{};
+  };
+
+  // CPU priority order
+  // This is mostly arbitrary but will sort by some sort of CPU priority by performance
+  // Relative list so things they will commonly end up in big.little configurations sort of relate
+  static constexpr std::array<CPUMIDR, 35> CPUMIDRs = {{
+    // Typically big CPU cores
+    {0x61, 0x023, 1, ProductNames::ARM_Firestorm}, // Apple M1 Firestorm
+
+    {0x41, 0xd49, 1, ProductNames::ARM_N2}, // N2
+    {0x41, 0xd4b, 1, ProductNames::ARM_A78C}, // A78C
+    {0x41, 0xd4a, 1, ProductNames::ARM_E1}, // E1
+    {0x41, 0xd49, 1, ProductNames::ARM_N2}, // N2
+    {0x41, 0xd48, 1, ProductNames::ARM_X2}, // X2
+    {0x41, 0xd47, 1, ProductNames::ARM_A710}, // A710
+    {0x41, 0xd44, 1, ProductNames::ARM_X1}, // X1
+    {0x41, 0xd42, 1, ProductNames::ARM_A78AE}, // A78AE
+    {0x41, 0xd41, 1, ProductNames::ARM_A78}, // A78
+    {0x41, 0xd40, 1, ProductNames::ARM_V1}, // V1
+    {0x41, 0xd0e, 1, ProductNames::ARM_A76AE}, // A76AE
+    {0x41, 0xd0d, 1, ProductNames::ARM_A77}, // A77
+    {0x41, 0xd0c, 1, ProductNames::ARM_N1}, // N1
+    {0x41, 0xd0b, 1, ProductNames::ARM_A76}, // A76
+    {0x51, 0x804, 1, ProductNames::ARM_Kryo400}, // Kryo 4xx Gold (A76 based)
+    {0x41, 0xd0a, 1, ProductNames::ARM_A75}, // A75
+    {0x51, 0x802, 1, ProductNames::ARM_Kryo300}, // Kryo 3xx Gold (A75 based)
+    {0x41, 0xd09, 1, ProductNames::ARM_A73}, // A73
+    {0x51, 0x800, 1, ProductNames::ARM_Kryo200}, // Kryo 2xx Gold (A73 based)
+    {0x41, 0xd08, 1, ProductNames::ARM_A72}, // A72
+
+    {0x4e, 0x004, 1, ProductNames::ARM_Carmel}, // Carmel
+
+    // Denver rated above A57 to match TX2 weirdness
+    {0x4e, 0x003, 1, ProductNames::ARM_Denver}, // Denver
+
+    {0x41, 0xd07, 1, ProductNames::ARM_A57}, // A57
+
+    // Typically Little CPU cores
+    {0x61, 0x022, 0, ProductNames::ARM_Icestorm}, // Apple M1 Icestorm
+    {0x41, 0xd46, 0, ProductNames::ARM_A510}, // A510
+    {0x41, 0xd06, 0, ProductNames::ARM_A65}, // A65
+    {0x41, 0xd05, 0, ProductNames::ARM_A55}, // A55
+    {0x51, 0x805, 0, ProductNames::ARM_Kryo400S}, // Kryo 4xx/5xx Silver (A55 based)
+    {0x51, 0x803, 0, ProductNames::ARM_Kryo300S}, // Kryo 3xx Silver (A55 based)
+    {0x41, 0xd03, 0, ProductNames::ARM_A53}, // A53
+    {0x51, 0x801, 0, ProductNames::ARM_Kryo200S}, // Kryo 2xx Silver (A53 based)
+    {0x41, 0xd04, 0, ProductNames::ARM_A35}, // A35
+
+    {0x41, 0, 0, ProductNames::ARM_UNKNOWN}, // Invalid CPU or Apple CPU inside Parallels VM
+    {0x0, 0, 0, ProductNames::ARM_UNKNOWN}, // Invalid starting point is lowest ranked
+  }};
+
+  auto FindDefinedMIDR = [](uint32_t MIDR) -> const CPUMIDR* {
+    uint8_t Implementer = MIDR >> 24;
+    uint16_t Part = (MIDR >> 4) & 0xFFF;
+
+    for (auto &MIDROption : CPUMIDRs) {
+      if (MIDROption.Implementer == Implementer &&
+          MIDROption.Part == Part) {
+        return &MIDROption;
+      }
+    }
+
+    return nullptr;
+  };
+
+  if (Hybrid) {
+    // Walk the MIDRs and calculate big little designs
+    std::vector<const CPUMIDR*> BigCores;
+    std::vector<const CPUMIDR*> LittleCores;
+
+    // Separate CPU cores out to big or little selected
+    for (size_t i = 0; i < CPUs; ++i) {
+      uint32_t MIDR = PerCPUData[i].MIDR;
+      auto MIDROption = FindDefinedMIDR(MIDR);
+      if (MIDROption) {
+        // Found one
+        if (MIDROption->DefaultBig) {
+          BigCores.emplace_back(MIDROption);
+        }
+        else {
+          LittleCores.emplace_back(MIDROption);
+        }
+      }
+      else {
+        // If we didn't insert this MIDR then claim it is a little core.
+        LittleCores.emplace_back(&CPUMIDRs.back());
+      }
+    }
+
+    if (LittleCores.empty()) {
+      // If we only ended up with big cores then we need to move some to be little cores
+      uint32_t LowestMIDR = ~0U;
+      uint32_t LowestMIDRIdx = 0;
+      // Walk all the big cores
+      for (size_t i = 0; i < BigCores.size(); ++i) {
+        uint8_t Implementer = BigCores[i]->Implementer;
+        uint16_t Part = BigCores[i]->Part;
+
+        // Walk our list of CPUMIDRs to find the most little core
+        for (size_t j = LowestMIDRIdx; j < CPUMIDRs.size(); ++j) {
+          auto &MIDROption = CPUMIDRs[i];
+          if ((MIDROption.Implementer == Implementer &&
+              MIDROption.Part == Part) ||
+              (MIDROption.Implementer == 0 &&
+               MIDROption.Part == 0)) {
+
+            LowestMIDRIdx = j;
+            LowestMIDR = MIDR;
+            break;
+          }
+        }
+      }
+
+      // Now we WILL have found a big core to demote to little status
+      // Demote them
+      std::erase_if(BigCores, [&LittleCores, LowestMIDR](auto *Entry) {
+        // Demote by erase copy to little array
+        uint8_t Implementer = LowestMIDR >> 24;
+        uint16_t Part = (LowestMIDR >> 4) & 0xFFF;
+
+        if (Entry->Implementer == Implementer &&
+            Entry->Part == Part) {
+          // Add it to the BigCore list
+          LittleCores.emplace_back(Entry);
+          return true;
+        }
+        return false;
+      });
+    }
+
+    if (BigCores.empty()) {
+      // We never found a CPU core we understand
+      // Grab the first core, consider it as little, move everything else to Big
+      uint32_t LittleMIDR = PerCPUData[0].MIDR;
+      // Now walk the little cores and move them to Big if they don't match
+      std::erase_if(LittleCores, [&BigCores, LittleMIDR](auto *Entry) {
+        // You're promoted now
+        uint8_t Implementer = LittleMIDR >> 24;
+        uint16_t Part = (LittleMIDR >> 4) & 0xFFF;
+
+        if (Entry->Implementer != Implementer ||
+            Entry->Part != Part) {
+          // Add it to the BigCore list
+          BigCores.emplace_back(Entry);
+          return true;
+        }
+        return false;
+      });
+    }
+
+    // Now walk the per CPU data one more time and set if it is big or little
+    for (auto &Data : PerCPUData) {
+      uint8_t Implementer = Data.MIDR >> 24;
+      uint16_t Part = (Data.MIDR >> 4) & 0xFFF;
+
+      bool FoundBig{};
+      const CPUMIDR *MIDR{};
+      for (auto Big : BigCores) {
+        if (Big->Implementer == Implementer &&
+            Big->Part == Part) {
+          FoundBig = true;
+          MIDR = Big;
+          break;
+        }
+      }
+
+      if (!FoundBig) {
+        for (auto Little : LittleCores) {
+          if (Little->Implementer == Implementer &&
+              Little->Part == Part) {
+            MIDR = Little;
+            break;
+          }
+        }
+      }
+
+      Data.IsBig = FoundBig;
+      if (MIDR) {
+        Data.ProductName = MIDR->ProductName ?: ProductNames::ARM_UNKNOWN;
+      }
+      else {
+        Data.ProductName = ProductNames::ARM_UNKNOWN;
+      }
+    }
+  }
+  else {
+    // If we aren't hybrid then just claim everything is big
+    for (size_t i = 0; i < CPUs; ++i) {
+      uint32_t MIDR = PerCPUData[i].MIDR;
+      auto MIDROption = FindDefinedMIDR(MIDR);
+
+      PerCPUData[i].IsBig = true;
+      if (MIDROption) {
+        PerCPUData[i].ProductName = MIDROption->ProductName ?: ProductNames::ARM_UNKNOWN;
+      }
+      else {
+        PerCPUData[i].ProductName = ProductNames::ARM_UNKNOWN;
+      }
+    }
+  }
 }

 #else
@@ -119,16 +363,21 @@ static uint32_t GetCycleCounterFrequency() {
  return 0;
 }

-static bool GetHostHybridFlag() {
+void CPUIDEmu::SetupHostHybridFlag() {
  uint32_t eax, ebx, ecx, edx;
  __cpuid(0, eax, ebx, ecx, edx);
  if (eax >= 0x7) {
    __cpuid(0x7, eax, ebx, ecx, edx);
    // Bit 15 of edx claims hybrid CPU
-    return (edx & (1U << 15)) != 0;
+    Hybrid = (edx & (1U << 15)) != 0;
  }

-  return false;
+  size_t CPUs = CalculateNumberOfCPUs();
+  PerCPUData.resize(CPUs);
+  for (size_t i = 0; i < CPUs; ++i) {
+    PerCPUData[i].IsBig = true;
+    PerCPUData[i].ProductName = ProductNames::UNKNOWN;
+  }
 }

 #endif
@@ -155,6 +404,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h(uint32_t Leaf) {
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
  FEXCore::CPUID::FunctionResults Res{};
  uint32_t CoreCount = Cores();
+  // XXX: Enable once the rest of the SSE4.2 instructions are emulated
+  uint32_t SupportsSSE42 = CTX->HostFeatures.SupportsCRC && false ? 1 : 0;

  Res.eax = FAMILY_IDENTIFIER;

@@ -184,7 +435,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
    (0 << 17) | // Process-context identifiers
    (0 << 18) | // Prefetching from memory mapped device
    (1 << 19) | // SSE4.1
-    (0 << 20) | // SSE4.2
+    (SupportsSSE42 << 20) | // SSE4.2
    (0 << 21) | // X2APIC
    (1 << 22) | // MOVBE
    (1 << 23) | // POPCNT
@@ -194,7 +445,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
    (0 << 27) | // OSXSAVE
    (SUPPORTS_AVX << 28) | // AVX
    (0 << 29) | // F16C
-    (0 << 30) | // RDRAND
+    (CTX->HostFeatures.SupportsRAND << 30) | // RDRAND
    (0 << 31);  // Hypervisor always returns zero

  Res.edx =
@@ -386,7 +637,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
      (0 <<  5) | // AVX2 support
      (1 <<  6) | // FPU data pointer updated only on exception
      (1 <<  7) | // SMEP support
-      (0 <<  8) | // BMI2
+      (1 <<  8) | // BMI2
      (0 <<  9) | // Enhanced REP MOVSB/STOSB
      (1 << 10) | // INVPCID for system software control of process-context
      (0 << 11) | // Restricted transactional memory
@@ -396,8 +647,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
      (0 << 15) | // Intel Resource Directory Technology Allocation
      (0 << 16) | // Reserved
      (0 << 17) | // Reserved
-      (0 << 18) | // RDSEED
-      (0 << 19) | // ADCX and ADOX instructions
+      (CTX->HostFeatures.SupportsRAND << 18) | // RDSEED
+      (1 << 19) | // ADCX and ADOX instructions
      (0 << 20) | // SMAP Supervisor mode access prevention and CLAC/STAC instructions
      (0 << 21) | // Reserved
      (0 << 22) | // Reserved
@@ -549,6 +800,59 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_15h(uint32_t Leaf) {
  return Res;
 }

+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_1Ah(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  if (Hybrid) {
+    uint32_t CPU = GetCPUID();
+    auto &Data = PerCPUData[CPU];
+    // 0x40 is a big CPU
+    // 0x20 is a little CPU
+    Res.eax |= (Data.IsBig ? 0x40 : 0x20) << 24;
+  }
+  return Res;
+}
+
+// Hypervisor CPUID information leaf
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_4000_0000h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  // Maximum supported hypervisor leafs
+  // We only expose the information leaf
+  //
+  // Common courtesy to follow VMWare's "Hypervisor CPUID Interface proposal"
+  // 4000_0000h - Information leaf. Advertising to the software which hypervisor this is
+  // 4000_0001h - 4000_000Fh - Hypervisor specific leafs. FEX can use these for anything
+  // 4000_0010h - 4000_00FFh - "Generic Leafs" - Try not to overwrite, other hypervisors might expect information in these
+  //
+  // CPUID documentation information:
+  // 4000_0000h - 4FFF_FFFFh - No existing or future CPU will return information in this range
+  // Reserved entirely for VMs to do whatever they want.
+  Res.eax = 0x40000001;
+
+  // EBX, EDX, ECX become the hypervisor ID signature
+  constexpr static char HypervisorID[12] = "FEXIFEXIEMU";
+  memcpy(&Res.ebx, HypervisorID, sizeof(HypervisorID));
+  return Res;
+}
+
+// Hypervisor CPUID information leaf
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_4000_0001h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  if (Leaf == 0) {
+    // EAX[3:0] Is the host architecture that FEX is running under
+#ifdef _M_X86_64
+    // EAX[3:0] = 1 = x86_64 host architecture
+    Res.eax |= 0b0001;
+#elif defined(_M_ARM_64)
+    // EAX[3:0] = 2 = AArch64 host architecture
+    Res.eax |= 0b0010;
+#else
+    // EAX[3:0] = 0 = Unknown architecture
+#endif
+  }
+
+  return Res;
+}
+
 // Highest extended function implemented
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h(uint32_t Leaf) {
  FEXCore::CPUID::FunctionResults Res{};
@@ -636,35 +940,52 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
    (1 << 24) | // FXSAVE/FXRSTOR
    (1 << 25) | // FXSAVE/FXRSTOR Optimizations
    (0 << 26) | // 1 gigabit pages
-    (0 << 27) | // RDTSCP
+    (1 << 27) | // RDTSCP
    (0 << 28) | // Reserved
    (1 << 29) | // Long Mode
-    (0 << 30) | // 3DNow! Extensions
-    (0 << 31);  // 3DNow!
+    (1 << 30) | // 3DNow! Extensions
+    (1 << 31);  // 3DNow!
  return Res;
 }

-constexpr char ProcessorBrand[48] = {
+constexpr char ProcessorBrand[32] = {
  GIT_DESCRIBE_STRING
-  "\0"
 };

+constexpr ssize_t DESCRIBE_STR_SIZE = std::char_traits<char>::length(GIT_DESCRIBE_STRING);
+static_assert(DESCRIBE_STR_SIZE < 32);
+
 //Processor brand string
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h(uint32_t Leaf) {
-  FEXCore::CPUID::FunctionResults Res{};
-  memcpy(&Res, &ProcessorBrand[0], sizeof(FEXCore::CPUID::FunctionResults));
-  return Res;
+  return Function_8000_0002h(Leaf, GetCPUID());
 }

 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h(uint32_t Leaf) {
-  FEXCore::CPUID::FunctionResults Res{};
-  memcpy(&Res, &ProcessorBrand[16], sizeof(FEXCore::CPUID::FunctionResults));
-  return Res;
+  return Function_8000_0003h(Leaf, GetCPUID());
 }

 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h(uint32_t Leaf) {
+  return Function_8000_0004h(Leaf, GetCPUID());
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h(uint32_t Leaf, uint32_t CPU) {
  FEXCore::CPUID::FunctionResults Res{};
-  memcpy(&Res, &ProcessorBrand[32], sizeof(FEXCore::CPUID::FunctionResults));
+  memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
+  memcpy(&Res, &ProcessorBrand[0], std::min(16L, DESCRIBE_STR_SIZE));
+  return Res;
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h(uint32_t Leaf, uint32_t CPU) {
+  FEXCore::CPUID::FunctionResults Res{};
+  memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
+  memcpy(&Res, &ProcessorBrand[16], std::max(0L, DESCRIBE_STR_SIZE - 16));
+  return Res;
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h(uint32_t Leaf, uint32_t CPU) {
+  FEXCore::CPUID::FunctionResults Res{};
+  auto &Data = PerCPUData[CPU];
+  memcpy(&Res, Data.ProductName, std::min(strlen(Data.ProductName), sizeof(FEXCore::CPUID::FunctionResults)));
  return Res;
 }

@@ -757,7 +1078,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0008h(uint32_t Leaf) {
  Res.ebx =
    (0 << 2) | // XSaveErPtr: Saving and restoring error pointers
    (0 << 1) | // IRPerf: Instructions retired count support
-    (0 << 0);  // CLZERO support
+    (CTX->HostFeatures.SupportsCLZERO << 0);  // CLZERO support

  uint32_t CoreCount = Cores() - 1;
  Res.ecx =
@@ -888,25 +1209,25 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_Reserved(uint32_t Leaf) {

 void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
  CTX = ctx;
-  using namespace std::placeholders;
-  RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this, _1));
-  RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this, _1));
-  RegisterFunction(2, std::bind(&CPUIDEmu::Function_02h, this, _1));
+
+  RegisterFunction(0, &CPUIDEmu::Function_0h);
+  RegisterFunction(1, &CPUIDEmu::Function_01h);
+  RegisterFunction(2, &CPUIDEmu::Function_02h);
  // 3: Serial Number(previously), now reserved
 #ifndef CPUID_AMD
  // Deterministic cache parameters for each level
-  RegisterFunction(0x4, std::bind(&CPUIDEmu::Function_04h, this, _1));
+  RegisterFunction(0x4, &CPUIDEmu::Function_04h);
 #endif
  // 5: Monitor/mwait
  // Thermal and power management
-  RegisterFunction(6, std::bind(&CPUIDEmu::Function_06h, this, _1));
+  RegisterFunction(6, &CPUIDEmu::Function_06h);
  // Extended feature flags
-  RegisterFunction(7, std::bind(&CPUIDEmu::Function_07h, this, _1));
+  RegisterFunction(7, &CPUIDEmu::Function_07h);
  // 9: Direct Cache Access information
  // 0x0A: Architectural performance monitoring
  // 0x0B: Extended topology enumeration
  // 0x0D: Processor extended state enumeration
-  RegisterFunction(0x0D, std::bind(&CPUIDEmu::Function_0Dh, this, _1));
+  RegisterFunction(0x0D, &CPUIDEmu::Function_0Dh);
  // 0x0F: Intel RDT monitoring
  // 0x10: Intel RDT allocation enumeration
  // 0x12: Intel SGX capability enumeration
@@ -915,38 +1236,46 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
 #ifndef CPUID_AMD
  // Timestamp counter information
  // Doesn't exist on AMD hardware
-  RegisterFunction(0x15, std::bind(&CPUIDEmu::Function_15h, this, _1));
+  RegisterFunction(0x15, &CPUIDEmu::Function_15h);
 #endif
  // 0x16: Processor frequency information
  // 0x17: SoC vendor attribute enumeration

+  // 0x1A: Hybrid Information Sub-leaf
+#ifndef CPUID_AMD
+  RegisterFunction(0x1A, &CPUIDEmu::Function_1Ah);
+#endif
+  // Hypervisor CPUID information leaf
+  RegisterFunction(0x4000'0000, &CPUIDEmu::Function_4000_0000h);
+  RegisterFunction(0x4000'0001, &CPUIDEmu::Function_4000_0001h);
+
  // Largest extended function number
-  RegisterFunction(0x8000'0000, std::bind(&CPUIDEmu::Function_8000_0000h, this, _1));
+  RegisterFunction(0x8000'0000, &CPUIDEmu::Function_8000_0000h);
  // Processor vendor
-  RegisterFunction(0x8000'0001, std::bind(&CPUIDEmu::Function_8000_0001h, this, _1));
+  RegisterFunction(0x8000'0001, &CPUIDEmu::Function_8000_0001h);
  // Processor brand string
-  RegisterFunction(0x8000'0002, std::bind(&CPUIDEmu::Function_8000_0002h, this, _1));
+  RegisterFunction(0x8000'0002, &CPUIDEmu::Function_8000_0002h);
  // Processor brand string continued
-  RegisterFunction(0x8000'0003, std::bind(&CPUIDEmu::Function_8000_0003h, this, _1));
+  RegisterFunction(0x8000'0003, &CPUIDEmu::Function_8000_0003h);
  // Processor brand string continued
-  RegisterFunction(0x8000'0004, std::bind(&CPUIDEmu::Function_8000_0004h, this, _1));
+  RegisterFunction(0x8000'0004, &CPUIDEmu::Function_8000_0004h);
  // 0x8000'0005: L1 Cache and TLB identifiers
 #ifdef CPUID_AMD
-  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_8000_0005h, this, _1));
+  RegisterFunction(0x8000'0005, &CPUIDEmu::Function_8000_0005h);
 #else
  // This is full reserved on Intel platforms
-  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_Reserved, this, _1));
+  RegisterFunction(0x8000'0005, &CPUIDEmu::Function_Reserved);
 #endif
  // 0x8000'0006: L2 Cache identifiers
-  RegisterFunction(0x8000'0006, std::bind(&CPUIDEmu::Function_8000_0006h, this, _1));
+  RegisterFunction(0x8000'0006, &CPUIDEmu::Function_8000_0006h);
  // Advanced power management information
-  RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this, _1));
+  RegisterFunction(0x8000'0007, &CPUIDEmu::Function_8000_0007h);
  // Virtual and physical address sizes
-  RegisterFunction(0x8000'0008, std::bind(&CPUIDEmu::Function_8000_0008h, this, _1));
+  RegisterFunction(0x8000'0008, &CPUIDEmu::Function_8000_0008h);

  // 0x8000'000A: SVM Revision
  // TLB 1GB page identifiers
-  RegisterFunction(0x8000'0019, std::bind(&CPUIDEmu::Function_8000_0019h, this, _1));
+  RegisterFunction(0x8000'0019, &CPUIDEmu::Function_8000_0019h);

  // 0x8000'001A: Performance optimization identifiers
  // 0x8000'001B: Instruction based sampling identifiers
@@ -954,13 +1283,13 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
  // 0x8000'001D: Cache properties
 #ifdef CPUID_AMD
  // Deterministic cache parameters for each level
-  RegisterFunction(0x8000'001D, std::bind(&CPUIDEmu::Function_8000_001Dh, this, _1));
+  RegisterFunction(0x8000'001D, &CPUIDEmu::Function_8000_001Dh);
 #endif
  // 0x8000'001E: Extended APIC ID
  // 0x8000'001F: AMD Secure Encryption

  // Setup some state tracking
-  Hybrid = GetHostHybridFlag();
+  SetupHostHybridFlag();
 }
 }

@@ -1,13 +1,13 @@
 #pragma once
-#include <functional>
+
+#include <cstdint>
 #include <unordered_map>
+#include <utility>
+#include <vector>

 #include <FEXCore/Core/CPUID.h>
 #include <FEXCore/Config/Config.h>

-#include <cstdint>
-#include <utility>
-
 namespace FEXCore {
 namespace Context {
  struct Context;
@@ -24,28 +24,50 @@ private:
  constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"

 public:
+  // X86 cacheline size effectively has to be hardcoded to 64
+  // if we report anything differently then applications are likely to break
+  constexpr static uint64_t CACHELINE_SIZE = 64;
+
  void Init(FEXCore::Context::Context *ctx);

  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
-    auto Handler = FunctionHandlers.find(Function);
+    const auto Handler = FunctionHandlers.find(Function);

    if (Handler == FunctionHandlers.end()) {
      return Function_Reserved(Leaf);
    }

-    return Handler->second(Leaf);
+    return (this->*Handler->second)(Leaf);
  }
+
+  FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
+    if (Function == 0x8000'0002U)
+      return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
+    else if (Function == 0x8000'0003U)
+      return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
+    else
+      return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
+  }
+
 private:
  FEXCore::Context::Context *CTX;
  bool Hybrid{};
  FEX_CONFIG_OPT(Cores, THREADS);

-  using FunctionHandler = std::function<FEXCore::CPUID::FunctionResults(uint32_t Leaf)>;
+  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
  void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
-    FunctionHandlers[Function] = Handler;
+    FunctionHandlers.insert_or_assign(Function, Handler);
  }

  std::unordered_map<uint32_t, FunctionHandler> FunctionHandlers;
+  struct CPUData {
+    const char *ProductName{};
+#ifdef _M_ARM_64
+    uint32_t MIDR{};
+#endif
+    bool IsBig{};
+  };
+  std::vector<CPUData> PerCPUData{};

  // Functions
  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
@@ -56,11 +78,19 @@ private:
  FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_1Ah(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_4000_0000h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_4000_0001h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf);
+
+  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf, uint32_t CPU);
+  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf, uint32_t CPU);
+  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf, uint32_t CPU);
+
  FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
@@ -69,5 +99,8 @@ private:
  FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
  FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
+
+  void SetupHostHybridFlag();
+
 };
 }
@@ -35,7 +35,9 @@ namespace FEXCore {
    CTX->InitializeCompiler(CompileThreadData.get(), true);
    CompileThreadData->CPUBackend->CopyNecessaryDataForCompileThread(ParentThread->CPUBackend.get());

+    uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+    FEXCore::Threads::SetSignalMask(OldMask);
  }

  void CompileService::Initialize() {
@@ -58,23 +60,15 @@ namespace FEXCore {
      // Grab the work queue and clear it
      // We don't need to grab the queue mutex since this thread will no longer receive any work events
      // Threads are bounded 1:1
-      while (WorkQueue.size()) {
-        WorkItem *Item = WorkQueue.front();
+      while (!WorkQueue.empty()) {
        WorkQueue.pop();
-        delete Item;
      }

      // Go through the garbage collection array and clear it
      // It's safe to clear things that aren't marked safe since we are clearing cache
-      if (GCArray.size()) {
-        // Clean up our GC array
-        for (auto it = GCArray.begin(); it != GCArray.end();) {
-          delete *it;
-          it = GCArray.erase(it);
-        }
-      }
+      GCArray.clear();

-      LOGMAN_THROW_A(CompileThreadData->LocalIRCache.size() == 0, "Compile service must never have LocalIRCache");
+      LOGMAN_THROW_A_FMT(CompileThreadData->LocalIRCache.empty(), "Compile service must never have LocalIRCache");

      CompileMutex.unlock();
    }
@@ -85,28 +79,26 @@ namespace FEXCore {
    SelectedThread->CPUBackend->ClearCache();
  }

-
  CompileService::WorkItem *CompileService::CompileCode(uint64_t RIP) {
-    // Tell the worker thread to compile code for us
-    WorkItem *Item = new WorkItem{};
-    Item->RIP = RIP;
+    WorkItem* ResultItem = nullptr;

    {
+      // Tell the worker thread to compile code for us
+      auto Item = std::make_unique<WorkItem>();
+      Item->RIP = RIP;
+
      // Fill the threads work queue
-      std::scoped_lock<std::mutex> lk(QueueMutex);
-      WorkQueue.emplace(Item);
+      std::scoped_lock lk(QueueMutex);
+      ResultItem = WorkQueue.emplace(std::move(Item)).get();
    }

    // Notify the thread that it has more work
    StartWork.NotifyAll();

-    return Item;
+    return ResultItem;
  }

  void CompileService::ExecutionThread() {
-    // Ignore signals coming from the guest
-    CTX->SignalDelegation->MaskThreadSignals();
-
    // Set our thread name so we can see its relation
    char ThreadName[16]{};
    snprintf(ThreadName, 16, "%ld-CS", ParentThread->ThreadManager.TID.load());
@@ -118,18 +110,18 @@ namespace FEXCore {
      if (ShuttingDown.load()) {
        break;
      }
-      std::scoped_lock<std::mutex> lk(CompileMutex);

+      std::scoped_lock lk(CompileMutex);
      size_t WorkItems{};

      do {
        // Grab a work item
-        WorkItem *Item{};
+        std::unique_ptr<WorkItem> Item{};
        {
-          std::scoped_lock<std::mutex> lk(QueueMutex);
+          std::scoped_lock lk(QueueMutex);
          WorkItems = WorkQueue.size();
-          if (WorkItems) {
-            Item = WorkQueue.front();
+          if (WorkItems != 0) {
+            Item = std::move(WorkQueue.front());
            WorkQueue.pop();
          }
        }
@@ -137,7 +129,7 @@ namespace FEXCore {
        // If we had a work item then work on it
        if (Item) {
          // Make sure it's not in lookup cache by accident
-          LOGMAN_THROW_A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
+          LOGMAN_THROW_A_FMT(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");

          // Code isn't in cache, compile now
          // Set our thread state's RIP
@@ -145,11 +137,11 @@ namespace FEXCore {

          auto [CodePtr, IRList, DebugData, RAData, Generated, StartAddr, Length] = CTX->CompileCode(CompileThreadData.get(), Item->RIP);

-          LOGMAN_THROW_A(Generated == true, "Compile Service doesn't have IR Cache");
+          LOGMAN_THROW_A_FMT(Generated == true, "Compile Service doesn't have IR Cache");

          if (!CodePtr) {
            // XXX: We currently have the expectation that compile service code will be significantly smaller than regular thread's code
-            ERROR_AND_DIE("Couldn't compile code for thread at RIP: 0x%lx", Item->RIP);
+            ERROR_AND_DIE_FMT("Couldn't compile code for thread at RIP: 0x{:x}", Item->RIP);
          }

          Item->CodePtr = CodePtr;
@@ -159,23 +151,15 @@ namespace FEXCore {
          Item->StartAddr = StartAddr;
          Item->Length = Length;

-          GCArray.emplace_back(Item);
-          Item->ServiceWorkDone.NotifyAll();
+          auto& GCItem = GCArray.emplace_back(std::move(Item));
+          GCItem->ServiceWorkDone.NotifyAll();
        }
      } while (WorkItems != 0);

-      if (GCArray.size()) {
-        // Clean up our GC array
-        for (auto it = GCArray.begin(); it != GCArray.end();) {
-          if ((*it)->SafeToClear) {
-            delete *it;
-            it = GCArray.erase(it);
-          }
-          else {
-            ++it;
-          }
-        }
-      }
+      // Clean up any safe entries in our GC array if we have any.
+      std::erase_if(GCArray, [](const auto& Entry) {
+        return Entry->SafeToClear.load(std::memory_order_relaxed);
+      });
    }
  }
 }
@@ -48,6 +48,9 @@ class CompileService final {
    // Public for threading
    void ExecutionThread();

+    bool IsAddressInJITCode(uint64_t Address) const {
+      return CompileThreadData->CPUBackend->IsAddressInJITCode(Address, false, false);
+    }
  private:
    FEXCore::Context::Context *CTX;
    FEXCore::Core::InternalThreadState *ParentThread;
@@ -57,8 +60,8 @@ class CompileService final {

    std::mutex QueueMutex{};
    std::mutex CompileMutex{};
-    std::queue<WorkItem*> WorkQueue{};
-    std::vector<WorkItem*> GCArray{};
+    std::queue<std::unique_ptr<WorkItem>> WorkQueue{};
+    std::vector<std::unique_ptr<WorkItem>> GCArray{};
    Event StartWork{};
    std::atomic_bool ShuttingDown{false};
 };
@@ -41,6 +41,7 @@ $end_info$
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXHeaderUtils/Syscalls.h>

 #include <algorithm>
 #include <array>
@@ -50,6 +51,7 @@ $end_info$
 #include <cstdint>
 #include <filesystem>
 #include <functional>
+#include <fstream>
 #include <map>
 #include <memory>
 #include <mutex>
@@ -61,7 +63,6 @@ $end_info$
 #include <string.h>
 #include <string>
 #include <string_view>
-#include <sstream>
 #include <sys/mman.h>
 #include <sys/stat.h>
 #include <sys/syscall.h>
@@ -141,63 +142,11 @@ std::string_view const& GetGRegName(unsigned Reg) {
 } // namespace FEXCore::Core

 namespace FEXCore::Context {
-  void Context::AOTIRCaptureCacheWriteoutQueue_Flush() {
-    {
-      std::shared_lock lk{AOTIRCaptureCacheWriteoutLock};
-      if (AOTIRCaptureCacheWriteoutQueue.size() == 0) {
-        AOTIRCaptureCacheWriteoutFlusing.store(false);
-        return;
-      }
-    }
-
-    for (;;) {
-      AOTIRCaptureCacheWriteoutLock.lock();
-      std::function<void()> fn = std::move(AOTIRCaptureCacheWriteoutQueue.front());
-      bool MaybeEmpty = false;
-      AOTIRCaptureCacheWriteoutQueue.pop();
-      MaybeEmpty = AOTIRCaptureCacheWriteoutQueue.size() == 0;
-      AOTIRCaptureCacheWriteoutLock.unlock();
-
-      fn();
-      if (MaybeEmpty) {
-        std::shared_lock lk{AOTIRCaptureCacheWriteoutLock};
-        if (AOTIRCaptureCacheWriteoutQueue.size() == 0) {
-          AOTIRCaptureCacheWriteoutFlusing.store(false);
-          return;
-        }
-      }
-    }
-
-    LOGMAN_MSG_A("Must never get here");
-  }
-
-  void Context::AOTIRCaptureCacheWriteoutQueue_Append(const std::function<void()> &fn) {
-    bool Flush = false;
-
-    {
-      std::unique_lock lk{AOTIRCaptureCacheWriteoutLock};
-      AOTIRCaptureCacheWriteoutQueue.push(fn);
-      if (AOTIRCaptureCacheWriteoutQueue.size() > 10000) {
-        Flush = true;
-      }
-    }
-
-    bool test_val = false;
-    if (Flush && AOTIRCaptureCacheWriteoutFlusing.compare_exchange_strong(test_val, true)) {
-      AOTIRCaptureCacheWriteoutQueue_Flush();
-    }
-  }
-
-  Context::Context() {
+  Context::Context()
+  : IRCaptureCache {this} {
 #ifdef BLOCKSTATS
    BlockData = std::make_unique<FEXCore::BlockSamplingData>();
 #endif
-    if (Config.GdbServer) {
-      StartGdbServer();
-    }
-    else {
-      StopGdbServer();
-    }
  }

  Context::~Context() {
@@ -217,10 +166,6 @@ namespace FEXCore::Context {
      }
      Threads.clear();
    }
-
-    for (auto &Mod: AOTIRCache) {
-      FEXCore::Allocator::munmap(Mod.second.mapping, Mod.second.size);
-    }
  }

  static FEXCore::Core::CPUState CreateDefaultCPUState() {
@@ -245,12 +190,44 @@ namespace FEXCore::Context {
  }

  FEXCore::Core::InternalThreadState* Context::InitCore(FEXCore::CodeLoader *Loader) {
+    // Initialize the CPU core signal handlers
+    switch (Config.Core) {
+#ifdef INTERPRETER_ENABLED
+    case FEXCore::Config::CONFIG_INTERPRETER:
+      FEXCore::CPU::InitializeInterpreterSignalHandlers(this);
+      break;
+#endif
+    case FEXCore::Config::CONFIG_IRJIT:
+#if (_M_X86_64 && JIT_X86_64)
+      FEXCore::CPU::InitializeX86JITSignalHandlers(this);
+#elif (_M_ARM_64 && JIT_ARM64)
+      FEXCore::CPU::InitializeArm64JITSignalHandlers(this);
+#else
+      ERROR_AND_DIE_FMT("FEXCore has been compiled without a viable JIT core");
+#endif
+      break;
+    case FEXCore::Config::CONFIG_CUSTOM:
+      // Do nothing
+      break;
+    default:
+      ERROR_AND_DIE_FMT("Unknown core configuration");
+      break;
+    }
+
+    // Initialize GDBServer after the signal handlers are installed
+    // It may install its own handlers that need to be executed AFTER the CPU cores
+    if (Config.GdbServer) {
+      StartGdbServer();
+    }
+    else {
+      StopGdbServer();
+    }
+
    ThunkHandler.reset(FEXCore::ThunkHandler::Create());

    LocalLoader = Loader;
    using namespace FEXCore::Core;

-    FEXCore::CPU::InitializeInterpreterOpHandlers();
    FEXCore::Core::CPUState NewThreadState = CreateDefaultCPUState();
    FEXCore::Core::InternalThreadState *Thread = CreateThread(&NewThreadState, 0);

@@ -323,7 +300,7 @@ namespace FEXCore::Context {
      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Pause);
      if (Thread->RunningEvents.Running.load()) {
        // Only attempt to stop this thread if it is running
-        tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+        FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
      }
    }
  }
@@ -342,7 +319,6 @@ namespace FEXCore::Context {
    std::lock_guard<std::mutex> lk(ThreadCreationMutex);
    for (auto &Thread : Threads) {
      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Return);
-      Thread->RunningEvents.WaitingToStart.store(true);
    }

    for (auto &Thread : Threads) {
@@ -381,13 +357,13 @@ namespace FEXCore::Context {
    this->Config.MaxInstPerBlock = 1;
    Run();
    WaitForThreadsToRun();
-    WaitForIdleWithTimeout();
+    WaitForIdle();
    this->Config.RunningMode = PreviousRunningMode;
    this->Config.MaxInstPerBlock = PreviousMaxIntPerBlock;
  }

  void Context::Stop(bool IgnoreCurrentThread) {
-    pid_t tid = gettid();
+    pid_t tid = FHU::Syscalls::gettid();
    FEXCore::Core::InternalThreadState* CurrentThread{};

    // Tell all the threads that they should stop
@@ -408,6 +384,13 @@ namespace FEXCore::Context {
        if (Thread->RunningEvents.Running.load()) {
          StopThread(Thread);
        }
+
+        // If the thread is waiting to start but immediately killed then there can be a hang
+        // This occurs in the case of gdb attach with immediate kill
+        if (Thread->RunningEvents.WaitingToStart.load()) {
+          Thread->RunningEvents.EarlyExit = true;
+          Thread->StartRunning.NotifyAll();
+        }
      }
    }

@@ -420,20 +403,25 @@ namespace FEXCore::Context {
  void Context::StopThread(FEXCore::Core::InternalThreadState *Thread) {
    if (Thread->RunningEvents.Running.exchange(false)) {
      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Stop);
-      tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
    }
  }

  void Context::SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event) {
    if (Thread->RunningEvents.Running.load()) {
      Thread->SignalReason.store(Event);
-      tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
    }
  }

  FEXCore::Context::ExitReason Context::RunUntilExit() {
-    if(!StartPaused)
-      Run();
+    if(!StartPaused) {
+      // We will only have one thread at this point, but just in case run notify everything
+      std::lock_guard lk(ThreadCreationMutex);
+      for (auto &Thread : Threads) {
+        Thread->StartRunning.NotifyAll();
+      }
+    }

    ExecutionThread(ParentThread);
    while(true) {
@@ -468,7 +456,6 @@ namespace FEXCore::Context {
    };

    LocalLoader->AddIR(IRHandler);
-
  }

  struct ExecutionThreadHandler {
@@ -496,7 +483,7 @@ namespace FEXCore::Context {

  void Context::InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread) {
    // Let's do some initial bookkeeping here
-    Thread->ThreadManager.TID = ::gettid();
+    Thread->ThreadManager.TID = FHU::Syscalls::gettid();
    Thread->ThreadManager.PID = ::getpid();
    SignalDelegation->RegisterTLSState(Thread);
    ThunkHandler->RegisterTLSState(Thread);
@@ -532,9 +519,11 @@ namespace FEXCore::Context {

    // Create CPU backend
    switch (Config.Core) {
+#ifdef INTERPRETER_ENABLED
    case FEXCore::Config::CONFIG_INTERPRETER:
      State->CPUBackend = FEXCore::CPU::CreateInterpreterCore(this, State, CompileThread);
      break;
+#endif
    case FEXCore::Config::CONFIG_IRJIT:
      State->PassManager->InsertRegisterAllocationPass(DoSRA);

@@ -543,14 +532,16 @@ namespace FEXCore::Context {
 #elif (_M_ARM_64 && JIT_ARM64)
      State->CPUBackend = FEXCore::CPU::CreateArm64JITCore(this, State, CompileThread);
 #else
-      ERROR_AND_DIE("FEXCore has been compiled without a viable JIT core");
+      ERROR_AND_DIE_FMT("FEXCore has been compiled without a viable JIT core");
 #endif

      break;
    case FEXCore::Config::CONFIG_CUSTOM:
      State->CPUBackend = CustomCPUFactory(this, State);
      break;
-    default: ERROR_AND_DIE("Unknown core configuration");
+    default:
+      ERROR_AND_DIE_FMT("Unknown core configuration");
+      break;
    }
  }

@@ -583,7 +574,7 @@ namespace FEXCore::Context {
      std::lock_guard<std::mutex> lk(ThreadCreationMutex);

      auto It = std::find(Threads.begin(), Threads.end(), Thread);
-      LOGMAN_THROW_A(It != Threads.end(), "Thread wasn't in Threads");
+      LOGMAN_THROW_A_FMT(It != Threads.end(), "Thread wasn't in Threads");

      Threads.erase(It);
    }
@@ -657,6 +648,58 @@ namespace FEXCore::Context {
    }
  }

+  static void IRDumper(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, IR::RegisterAllocationData* RA) {
+    FILE* f = nullptr;
+    bool CloseAfter = false;
+    const auto DumpIRStr = Thread->CTX->Config.DumpIR();
+
+    if (DumpIRStr =="stderr") {
+      f = stderr;
+    }
+    else if (DumpIRStr =="stdout") {
+      f = stdout;
+    }
+    else {
+      const auto fileName = fmt::format("{}/{:x}{}", DumpIRStr, GuestRIP, RA ? "-post.ir" : "-pre.ir");
+      f = fopen(fileName.c_str(), "w");
+      CloseAfter = true;
+    }
+
+    if (f) {
+      std::stringstream out;
+      auto NewIR = Thread->OpDispatcher->ViewIR();
+      FEXCore::IR::Dump(&out, &NewIR, RA);
+      fmt::print(f,"IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
+
+      if (CloseAfter) {
+        fclose(f);
+      }
+    }
+  };
+
+  static void ValidateIR(FEXCore::Core::InternalThreadState *Thread) {
+    // Convert to text, Parse, Convert to text again and make sure the texts match
+    std::stringstream out;
+    static auto compaction = IR::CreateIRCompaction();
+    compaction->Run(Thread->OpDispatcher.get());
+    auto NewIR = Thread->OpDispatcher->ViewIR();
+    Dump(&out, &NewIR, nullptr);
+    out.seekg(0);
+    auto reparsed = IR::Parse(&out);
+    if (reparsed == nullptr) {
+      LOGMAN_MSG_A_FMT("Failed to parse IR\n");
+    } else {
+      std::stringstream out2;
+      auto NewIR2 = reparsed->ViewIR();
+      Dump(&out2, &NewIR2, nullptr);
+      if (out.str() != out2.str()) {
+        LogMan::Msg::IFmt("one:\n {}", out.str());
+        LogMan::Msg::IFmt("two:\n {}", out2.str());
+        LOGMAN_MSG_A_FMT("Parsed IR doesn't match\n");
+      }
+    }
+  }
+
  Context::GenerateIRResult Context::GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
    uint8_t const *GuestCode{};
    GuestCode = reinterpret_cast<uint8_t const*>(GuestRIP);
@@ -666,9 +709,7 @@ namespace FEXCore::Context {
    uint64_t TotalInstructions {0};
    uint64_t TotalInstructionsLength {0};

-    if (!Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP)) {
-      return {};
-    }
+    Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP);

    auto CodeBlocks = Thread->FrontendDecoder->GetDecodedBlocks();

@@ -681,7 +722,6 @@ namespace FEXCore::Context {
      // Set the block entry point
      Thread->OpDispatcher->SetNewBlockIfChanged(Block.Entry);

-
      uint64_t BlockInstructionsLength {};

      // Reset any block-specific state
@@ -689,11 +729,6 @@ namespace FEXCore::Context {

      uint64_t InstsInBlock = Block.NumInstructions;

-      if (Block.HasInvalidInstruction) {
-        Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize));
-        break;
-      }
-
      for (size_t i = 0; i < InstsInBlock; ++i) {
        FEXCore::X86Tables::X86InstInfo const* TableInfo {nullptr};
        FEXCore::X86Tables::DecodedInst const* DecodedInfo {nullptr};
@@ -723,7 +758,7 @@ namespace FEXCore::Context {
          Thread->OpDispatcher->SetCurrentCodeBlock(NextOpBlock);
        }

-        if (TableInfo->OpcodeDispatcher) {
+        if (TableInfo && TableInfo->OpcodeDispatcher) {
          auto Fn = TableInfo->OpcodeDispatcher;
          Thread->OpDispatcher->HandledLock = false;
          Thread->OpDispatcher->ResetDecodeFailure();
@@ -734,7 +769,7 @@ namespace FEXCore::Context {
          else {
            if (Thread->OpDispatcher->HandledLock != IsLocked) {
              HadDispatchError = true;
-              LogMan::Msg::E("Missing LOCK HANDLER at 0x%lx{'%s'}", Block.Entry + BlockInstructionsLength, TableInfo->Name);
+              LogMan::Msg::EFmt("Missing LOCK HANDLER at 0x{:x}{{'{}'}}", Block.Entry + BlockInstructionsLength, TableInfo->Name ?: "UND");
            }
            BlockInstructionsLength += DecodedInfo->InstSize;
            TotalInstructionsLength += DecodedInfo->InstSize;
@@ -742,8 +777,9 @@ namespace FEXCore::Context {
          }
        }
        else {
-          LogMan::Msg::E("Missing OpDispatcher at 0x%lx{'%s'}", Block.Entry + BlockInstructionsLength, TableInfo->Name);
-          HadDispatchError = true;
+          // Invalid instruction
+          Thread->OpDispatcher->InvalidOp(DecodedInfo);
+          Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize));
        }

        // If we had a dispatch error then leave early
@@ -770,74 +806,32 @@ namespace FEXCore::Context {

    Thread->OpDispatcher->Finalize();

-    auto IRDumper = [Thread, GuestRIP](IR::RegisterAllocationData* RA) {
-      FILE* f = nullptr;
-      bool CloseAfter = false;
-
-      if (Thread->CTX->Config.DumpIR() =="stderr") {
-        f = stderr;
-      }
-      else if (Thread->CTX->Config.DumpIR() =="stdout") {
-        f = stdout;
-      }
-      else {
-        std::stringstream fileName;
-        fileName << Thread->CTX->Config.DumpIR()  << "/" << std::hex << GuestRIP << (RA ? "-post.ir" : "-pre.ir");
-
-        f = fopen(fileName.str().c_str(), "w");
-        CloseAfter = true;
+    // Debug
+    {
+      if (Thread->CTX->Config.DumpIR() != "no") {
+        IRDumper(Thread, GuestRIP, nullptr);
      }

-      if (f) {
-        std::stringstream out;
-        auto NewIR = Thread->OpDispatcher->ViewIR();
-        FEXCore::IR::Dump(&out, &NewIR, RA);
-        fprintf(f,"IR-%s 0x%lx:\n%s\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str().c_str());
-
-        if (CloseAfter) {
-          fclose(f);
-        }
-      }
-    };
-
-    if (Thread->CTX->Config.DumpIR() != "no") {
-      IRDumper(nullptr);
-    }
-
-    if (Thread->CTX->Config.ValidateIRarser) {
-      // Convert to text, Parse, Convert to text again and make sure the texts match
-      std::stringstream out;
-      static auto compaction = IR::CreateIRCompaction();
-      compaction->Run(Thread->OpDispatcher.get());
-      auto NewIR = Thread->OpDispatcher->ViewIR();
-      Dump(&out, &NewIR, nullptr);
-      out.seekg(0);
-      auto reparsed = IR::Parse(&out);
-      if (reparsed == nullptr) {
-        LOGMAN_MSG_A("Failed to parse ir\n");
-      } else {
-        std::stringstream out2;
-        auto NewIR2 = reparsed->ViewIR();
-        Dump(&out2, &NewIR2, nullptr);
-        if (out.str() != out2.str()) {
-          LogMan::Msg::I("one:\n %s", out.str().c_str());
-          LogMan::Msg::I("two:\n %s", out2.str().c_str());
-          LOGMAN_MSG_A("Parsed ir doesn't match\n");
-        }
+      if (Thread->CTX->Config.ValidateIRarser) {
+        ValidateIR(Thread);
      }
    }
+
    // Run the passmanager over the IR from the dispatcher
    Thread->PassManager->Run(Thread->OpDispatcher.get());

-    if (Thread->CTX->Config.DumpIR() != "no") {
-      IRDumper(Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
-    }
+    // Debug
+    {
+      if (Thread->CTX->Config.DumpIR() != "no") {
+        IRDumper(Thread, GuestRIP, Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
+      }

-    if (Thread->OpDispatcher->ShouldDump) {
-      std::stringstream out;
-      auto NewIR = Thread->OpDispatcher->ViewIR();
-      FEXCore::IR::Dump(&out, &NewIR, Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
-      LogMan::Msg::I("IR 0x%lx:\n%s\n@@@@@\n", GuestRIP, out.str().c_str());
+      if (Thread->OpDispatcher->ShouldDump) {
+        std::stringstream out;
+        auto NewIR = Thread->OpDispatcher->ViewIR();
+        FEXCore::IR::Dump(&out, &NewIR, Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
+        LogMan::Msg::IFmt("IR 0x{:x}:\n{}\n@@@@@\n", GuestRIP, out.str());
+      }
    }

    auto RAData = Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->PullAllocationData() : nullptr;
@@ -855,63 +849,6 @@ namespace FEXCore::Context {
    };
  }

-  AOTIRInlineEntry *AOTIRInlineIndex::GetInlineEntry(uint64_t DataOffset) {
-    uintptr_t This = (uintptr_t)this;
-
-    return (AOTIRInlineEntry*)(This + DataBase + DataOffset);
-  }
-
-  AOTIRInlineEntry *AOTIRInlineIndex::Find(uint64_t GuestStart) {
-    ssize_t l = 0;
-    ssize_t r = Count - 1;
-
-    while (l <= r) {
-      size_t m = l + (r - l) / 2;
-
-      if (Entries[m].GuestStart == GuestStart)
-        return GetInlineEntry(Entries[m].DataOffset);
-      else if (Entries[m].GuestStart < GuestStart)
-        l = m + 1;
-      else
-        r = m - 1;
-    }
-
-    return nullptr;
-  }
-
-  IR::RegisterAllocationData *AOTIRInlineEntry::GetRAData() {
-    return (IR::RegisterAllocationData *)InlineData;
-  }
-
-  IR::IRListView *AOTIRInlineEntry::GetIRData() {
-    auto RAData = GetRAData();
-    auto Offset = RAData->Size(RAData->MapCount);
-
-    return (IR::IRListView *)&InlineData[Offset];
-  }
-
-  void AOTIRCaptureCacheEntry::AppendAOTIRCaptureCache(uint64_t GuestRIP, uint64_t Start, uint64_t Length, uint64_t Hash, FEXCore::IR::IRListView *IRList, FEXCore::IR::RegisterAllocationData *RAData) {
-    auto Inserted = Index.emplace(GuestRIP, Stream->tellp());
-
-    if (Inserted.second) {
-      //GuestHash
-      Stream->write((const char*)&Hash, sizeof(Hash));
-
-      //GuestLength
-      Stream->write((const char*)&Length, sizeof(Length));
-
-      // RAData (inline)
-      // In file, IsShared is always set
-      auto Shared = RAData->IsShared;
-      RAData->IsShared = true;
-      Stream->write((const char*)RAData, RAData->Size(RAData->MapCount));
-      RAData->IsShared = Shared;
-
-      // IRData (inline)
-      IRList->Serialize(*Stream);
-    }
-  }
-
  Context::CompileCodeResult Context::CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
    FEXCore::IR::IRListView *IRList {};
    FEXCore::Core::DebugData *DebugData {};
@@ -935,55 +872,17 @@ namespace FEXCore::Context {
      GeneratedIR = false;
    }

+    // AOT IR bookkeeping and cache
    {
-      std::shared_lock lk(AOTIRCacheLock);
-      auto file = AddrToFile.lower_bound(GuestRIP);
-      if (file != AddrToFile.begin()) {
-        --file;
-        if (!file->second.ContainsCode) {
-          file->second.ContainsCode = true;
-          FilesWithCode[file->second.fileid] = file->second.filename;
-        }
-      }
-    }
-
-    if (IRList == nullptr && Config.AOTIRLoad) {
-      std::shared_lock lk(AOTIRCacheLock);
-      auto file = AddrToFile.lower_bound(GuestRIP);
-      if (file != AddrToFile.begin()) {
-        --file;
-        auto Mod = (AOTIRInlineIndex*)file->second.CachedFileEntry;
-
-        if (Mod == nullptr) {
-          file->second.CachedFileEntry = Mod = AOTIRCache[file->second.fileid].Array;
-        }
-
-        if (Mod != nullptr)
-        {
-          auto AOTEntry = Mod->Find(GuestRIP - file->second.Start + file->second.Offset);
-
-          if (AOTEntry) {
-            // verify hash
-            auto MappedStart = GuestRIP;
-            auto hash = XXH3_64bits((void*)MappedStart, AOTEntry->GuestLength);
-            if (hash == AOTEntry->GuestHash) {
-              IRList = AOTEntry->GetIRData();
-              //LogMan::Msg::D("using %s + %lx -> %lx\n", file->second.fileid.c_str(), AOTEntry->first, GuestRIP);
-
-
-              RAData = AOTEntry->GetRAData();;
-              DebugData = new FEXCore::Core::DebugData();
-              StartAddr = MappedStart;
-              Length = AOTEntry->GuestLength;
-
-              GeneratedIR = true;
-            } else {
-              LogMan::Msg::I("AOTIR: hash check failed %lx\n", MappedStart);
-            }
-          } else {
-            //LogMan::Msg::I("AOTIR: Failed to find %lx, %lx, %s\n", GuestRIP, GuestRIP - file->second.Start + file->second.Offset, file->second.fileid.c_str());
-          }
-        }
+      auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(GuestRIP, IRList);
+      if (_GeneratedIR) {
+        // Setup pointers to internal structures
+        IRList = IRCopy;
+        RAData = RACopy;
+        DebugData = DebugDataCopy;
+        StartAddr = _StartAddr;
+        Length = _Length;
+        GeneratedIR = _GeneratedIR;
      }
    }

@@ -998,10 +897,6 @@ namespace FEXCore::Context {
      StartAddr = _StartAddr;
      Length = _Length;

-      // Initialize metadata
-      DebugData->GuestCodeSize = TotalInstructionsLength;
-      DebugData->GuestInstructionCount = TotalInstructions;
-
      // Increment stats
      Thread->Stats.BlocksCompiled.fetch_add(1);

@@ -1024,138 +919,17 @@ namespace FEXCore::Context {
    };
  }

-  static bool readAll(int fd, void *data, size_t size) {
-    int rv = read(fd, data, size);
-
-    if (rv != size)
-      return false;
-    else
-      return true;
-  }
-
-  bool Context::LoadAOTIRCache(int streamfd) {
-    uint64_t tag;
-
-    if (!readAll(streamfd, (char*)&tag, sizeof(tag)) || tag != 0xDEADBEEFC0D30004)
-      return false;
-
-    std::string Module;
-    uint64_t ModSize;
-    uint64_t IndexSize;
-
-    lseek(streamfd, -sizeof(ModSize), SEEK_END);
-
-    if (!readAll(streamfd,  (char*)&ModSize, sizeof(ModSize)))
-      return false;
-
-    Module.resize(ModSize);
-
-    lseek(streamfd, -sizeof(ModSize) - ModSize, SEEK_END);
-
-    if (!readAll(streamfd,  (char*)&Module[0], Module.size()))
-      return false;
-
-    lseek(streamfd, -sizeof(ModSize) - ModSize - sizeof(IndexSize), SEEK_END);
-
-    if (!readAll(streamfd,  (char*)&IndexSize, sizeof(IndexSize)))
-      return false;
-
-    struct stat fileinfo;
-    if (fstat(streamfd, &fileinfo) < 0)
-      return false;
-    size_t Size = (fileinfo.st_size + 4095) & ~4095;
-
-    size_t IndexOffset = fileinfo.st_size - IndexSize -sizeof(ModSize) - ModSize - sizeof(IndexSize);
-
-    void *FilePtr = FEXCore::Allocator::mmap(nullptr, Size, PROT_READ, MAP_SHARED, streamfd, 0);
-
-    if (FilePtr == MAP_FAILED)
-      return false;
-
-    auto Array = (AOTIRInlineIndex *)((char*)FilePtr + IndexOffset);
-
-    AOTIRCache.insert({Module, {Array, FilePtr, Size}});
-
-    LogMan::Msg::D("AOTIR: Module %s has %ld functions", Module.c_str(), Array->Count);
-
-    return true;
-
-  }
-
-  void Context::WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
-    std::shared_lock lk(AOTIRCacheLock);
-    for( const auto &File: FilesWithCode) {
-      Writer(File.first, File.second);
-    }
-  }
-
-  void Context::FinalizeAOTIRCache() {
-    AOTIRCaptureCacheWriteoutQueue_Flush();
-
-    std::unique_lock lk(AOTIRCacheLock);
-
-    for (auto& [String, Entry] : AOTIRCaptureCache) {
-      if (!Entry.Stream) {
-        continue;
-      }
-
-      const auto ModSize = String.size();
-      auto &stream = Entry.Stream;
-
-      // pad to 32 bytes
-      constexpr char Zero = 0;
-      while(stream->tellp() & 31)
-        stream->write(&Zero, 1);
-
-      // AOTIRInlineIndex
-      const auto FnCount = Entry.Index.size();
-      const size_t DataBase = -stream->tellp();
-
-      stream->write((const char*)&FnCount, sizeof(FnCount));
-      stream->write((const char*)&DataBase, sizeof(DataBase));
-
-      for (const auto& [GuestStart, DataOffset] : Entry.Index) {
-        //AOTIRInlineIndexEntry
-
-        // GuestStart
-        stream->write((const char*)&GuestStart, sizeof(GuestStart));
-
-        // DataOffset
-        stream->write((const char*)&DataOffset, sizeof(DataOffset));
-      }
-
-      // End of file header
-      const auto IndexSize = FnCount * sizeof(AOTIRInlineIndexEntry) + sizeof(DataBase) + sizeof(FnCount);
-      stream->write((const char*)&IndexSize, sizeof(IndexSize));
-      stream->write(String.c_str(), ModSize);
-      stream->write((const char*)&ModSize, sizeof(ModSize));
-    }
-  }
-
  void Context::CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
    auto NewBlock = CompileBlock(Frame, GuestRIP);

    if (NewBlock == 0) {
-      LogMan::Msg::E("CompileBlockJit: Failed to compile code %lX - aborting process", GuestRIP);
+      LogMan::Msg::EFmt("CompileBlockJit: Failed to compile code {:X} - aborting process", GuestRIP);
      // Return similar behaviour of SIGILL abort
      Frame->Thread->StatusCode = 128 + SIGILL;
      Stop(false /* Ignore current thread */);
    }
  }

-  Context::AddrToFileMapType::iterator Context::FindAddrForFile(uint64_t Entry, uint64_t Length) {
-    // Thread safety here! We are returning an iterator to the map object
-    // This needs the AOTIRCacheLock locked prior to coming in to the function
-    auto file = AddrToFile.lower_bound(Entry);
-    if (file != AddrToFile.begin()) {
-      --file;
-      if (file->second.Start <= Entry && (file->second.Start + file->second.Len) >= (Entry + Length)) {
-        return file;
-      }
-    }
-    return AddrToFile.end();
-  }
-
  uintptr_t Context::CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
    auto Thread = Frame->Thread;

@@ -1180,7 +954,7 @@ namespace FEXCore::Context {
        Thread->CompileService->Initialize();
      }

-      auto WorkItem = Thread->CompileService->CompileCode(GuestRIP);
+      auto* WorkItem = Thread->CompileService->CompileCode(GuestRIP);
      WorkItem->ServiceWorkDone.Wait();
      // Return here with the data in place
      CodePtr = WorkItem->CodePtr;
@@ -1227,56 +1001,19 @@ namespace FEXCore::Context {
      }
    }

-    // Both generated ir and LibraryJITName need a named region lookup
-    if (GeneratedIR || Config.LibraryJITNaming()) {
-      std::shared_lock lk(AOTIRCacheLock);
-
-      auto file = FindAddrForFile(StartAddr, Length);
-
-      // Only go down this path if we actually found a library region
-      if (file != AddrToFile.end()) {
-        if (DebugData && Config.LibraryJITNaming()) {
-          Symbols.RegisterNamedRegion(CodePtr, DebugData->HostCodeSize, file->second.filename);
-        }
-
-        // Add to AOT cache if aot generation is enabled
-        if (GeneratedIR && RAData &&
-            (Config.AOTIRCapture() || Config.AOTIRGenerate())) {
-          auto hash = XXH3_64bits((void*)StartAddr, Length);
-
-          auto LocalRIP = GuestRIP - file->second.Start + file->second.Offset;
-          auto LocalStartAddr = StartAddr - file->second.Start + file->second.Offset;
-          auto fileid = file->second.fileid;
-          AOTIRCaptureCacheWriteoutQueue_Append([this, LocalRIP, LocalStartAddr, Length, hash, IRList, RAData, fileid]() {
-            auto *AotFile = &AOTIRCaptureCache[fileid];
-
-            if (!AotFile->Stream) {
-              AotFile->Stream = AOTIRWriter(fileid);
-              uint64_t tag = 0xDEADBEEFC0D30004;
-              AotFile->Stream->write((char*)&tag, sizeof(tag));
-            }
-            AotFile->AppendAOTIRCaptureCache(LocalRIP, LocalStartAddr, Length, hash, IRList, RAData);
-          });
-
-          if (Config.AOTIRGenerate()) {
-            // cleanup memory and early exit here -- we're not running the application
-
-            if (DecrementRefCount)
-              --Thread->CompileBlockReentrantRefCount;
-
-            Thread->CPUBackend->ClearCache();
-
-            return (uintptr_t)CodePtr;
-          }
-        }
-      }
-
-      // Insert to caches if we generated IR
-      if (GeneratedIR) {
-        // Add to thread local ir cache
-        Core::LocalIREntry Entry = {StartAddr, Length, decltype(Entry.IR)(IRList), decltype(Entry.RAData)(RAData), decltype(Entry.DebugData)(DebugData)};
-        Thread->LocalIRCache.insert({GuestRIP, std::move(Entry)});
-      }
+    if (IRCaptureCache.PostCompileCode(
+        Thread,
+        CodePtr,
+        GuestRIP,
+        StartAddr,
+        Length,
+        RAData,
+        IRList,
+        DebugData,
+        GeneratedIR,
+        DecrementRefCount)) {
+      // Early exit
+      return (uintptr_t)CodePtr;
    }

    if (DecrementRefCount)
@@ -1304,14 +1041,17 @@ namespace FEXCore::Context {
      Thread->StartRunning.Wait();
    }

-    Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_NONE;
+    if (!Thread->RunningEvents.EarlyExit.load()) {
+      Thread->RunningEvents.WaitingToStart = false;

-    Thread->RunningEvents.Running = true;
+      Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_NONE;

-    Thread->CPUBackend->ExecuteDispatch(Thread->CurrentFrame);
+      Thread->RunningEvents.Running = true;

-    Thread->RunningEvents.WaitingToStart = false;
-    Thread->RunningEvents.Running = false;
+      Thread->CPUBackend->ExecuteDispatch(Thread->CurrentFrame);
+
+      Thread->RunningEvents.Running = false;
+    }

    // If it is the parent thread that died then just leave
    // XXX: This doesn't make sense when the parent thread doesn't outlive its children
@@ -1403,38 +1143,17 @@ namespace FEXCore::Context {
  }

  void Context::AddNamedRegion(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename) {
-    // TODO: Support overlapping maps and region splitting
-    auto base_filename = std::filesystem::path(filename).filename().string();
-
-    if (!base_filename.empty()) {
-      auto filename_hash = XXH3_64bits(filename.c_str(), filename.size());
-
-      auto fileid = base_filename + "-" + std::to_string(filename_hash) + "-";
-
-      // append optimization flags to the fileid
-      fileid += (Config.SMCChecks == FEXCore::Config::CONFIG_SMC_FULL) ? "S" : "s";
-      fileid += Config.TSOEnabled ? "T" : "t";
-      fileid += Config.ABILocalFlags ? "L" : "l";
-      fileid += Config.ABINoPF ? "p" : "P";
-
-      std::unique_lock lk(AOTIRCacheLock);
-
-      AddrToFile.insert({ Base, { Base, Size, Offset, fileid, filename, nullptr, false} });
-
-      if (Config.AOTIRLoad && !AOTIRCache.contains(fileid) && AOTIRLoader) {
-        auto streamfd = AOTIRLoader(fileid);
-        if (streamfd != -1) {
-          LoadAOTIRCache(streamfd);
-          close(streamfd);
-        }
-      }
+    IRCaptureCache.AddNamedRegion(Base, Size, Offset, filename);
+    if (DebugServer) {
+      DebugServer->AlertLibrariesChanged();
    }
  }

  void Context::RemoveNamedRegion(uintptr_t Base, uintptr_t Size) {
-    std::unique_lock lk(AOTIRCacheLock);
-    // TODO: Support partial removing
-    AddrToFile.erase(Base);
+    IRCaptureCache.RemoveNamedRegion(Base, Size);
+    if (DebugServer) {
+      DebugServer->AlertLibrariesChanged();
+    }
  }

  void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
@@ -11,6 +11,8 @@
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXHeaderUtils/Syscalls.h>
+
 #include <array>
 #include <bit>
 #include <cmath>
@@ -25,6 +27,7 @@
 #include "code-buffer-vixl.h"
 #include "platform-vixl.h"

+#include <sys/syscall.h>
 #include <unistd.h>

 namespace FEXCore::CPU {
@@ -36,7 +39,7 @@ static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 #define STATE x28

 Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
-  : Dispatcher(ctx, Thread), Arm64Emitter(MAX_DISPATCHER_CODE_SIZE) {
+  : Dispatcher(ctx, Thread), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE) {
  SRAEnabled = config.StaticRegisterAssignment;
  SetAllowAssembler(true);

@@ -50,10 +53,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
  //    Ptr();
  // }

-  uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
-  Literal l_VirtualMemory {VirtualMemorySize};
  Literal l_PagePtr {Thread->LookupCache->GetPagePointer()};
-  Literal l_L1Ptr {Thread->LookupCache->GetL1Pointer()};
  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
  Literal l_CompileBlock {GetCompileBlockPtr()};
@@ -96,7 +96,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
  auto RipReg = x2;

  // L1 Cache
-  ldr(x0, &l_L1Ptr);
+  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.L1Pointer)));

  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
  add(x0, x0, Operand(x3, Shift::LSL, 4));
@@ -118,11 +118,12 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
  ldr(x0, &l_PagePtr);

  // Mask the address by the virtual address size so we can check for aliases
+  uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
  if (std::popcount(VirtualMemorySize) == 1) {
-    and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
+    and_(x3, RipReg, VirtualMemorySize - 1);
  }
  else {
-    ldr(x3, &l_VirtualMemory);
+    LoadConstant(x3, VirtualMemorySize);
    and_(x3, RipReg, x3);
  }

@@ -156,7 +157,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
    // If we've made it here then we have a real compiled block
    {
      // update L1 cache
-      ldr(x0, &l_L1Ptr);
+      ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.L1Pointer)));

      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
      add(x0, x0, Operand(x1, Shift::LSL, 4));
@@ -205,11 +206,31 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
    ret();
  }

+  constexpr bool SignalSafeCompile = true;
  {
    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
    if (SRAEnabled)
      SpillStaticRegs();

+    if (SignalSafeCompile) {
+      // When compiling code, mask all signals to reduce the chance of reentrant allocations
+      // Args:
+      // X0: SETMASK
+      // X1: Pointer to mask value (uint64_t)
+      // X2: Pointer to old mask value (uint64_t)
+      // X3: Size of mask, sizeof(uint64_t)
+      // X8: Syscall
+
+      LoadConstant(x0, ~0ULL);
+      stp(x0, x0, MemOperand(sp, -16, PreIndex));
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      add(x2, sp, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+    }
+
    ldr(x0, &l_ExitFunctionLinkThis);
    mov(x1, STATE);
    mov(x2, lr);
@@ -217,6 +238,24 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
    ldr(x3, &l_ExitFunctionLink);
    blr(x3);

+    if (SignalSafeCompile) {
+      // Now restore the signal mask
+      // Living in the same location
+
+      mov(x4, x0);
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      LoadConstant(x2, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Bring stack back
+      add(sp, sp, 16);
+
+      mov(x0, x4);
+    }
+
    if (SRAEnabled)
      FillStaticRegs();
    br(x0);
@@ -226,16 +265,53 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
  {
    bind(&NoBlock);

+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    if (SignalSafeCompile) {
+      // When compiling code, mask all signals to reduce the chance of reentrant allocations
+      // Args:
+      // X0: SETMASK
+      // X1: Pointer to mask value (uint64_t)
+      // X2: Pointer to old mask value (uint64_t)
+      // X3: Size of mask, sizeof(uint64_t)
+      // X8: Syscall
+
+      LoadConstant(x0, ~0ULL);
+      stp(x0, x2, MemOperand(sp, -16, PreIndex));
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      add(x2, sp, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Reload x2 to bring back RIP
+      ldr(x2, MemOperand(sp, 8, Offset));
+    }
+
    ldr(x0, &l_CTX);
    mov(x1, STATE);
    ldr(x3, &l_CompileBlock);

-    if (SRAEnabled)
-      SpillStaticRegs();
-
    // X2 contains our guest RIP
    blr(x3); // { CTX, Frame, RIP}

+
+    if (SignalSafeCompile) {
+      // Now restore the signal mask
+      // Living in the same location
+      LoadConstant(x0, SIG_SETMASK);
+      add(x1, sp, 0);
+      LoadConstant(x2, 0);
+      LoadConstant(x3, 8);
+      LoadConstant(x8, SYS_rt_sigprocmask);
+      svc(0);
+
+      // Bring stack back
+      add(sp, sp, 16);
+    }
+
    if (SRAEnabled)
      FillStaticRegs();

@@ -250,6 +326,42 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
    hlt(0);
  }

+  {
+    // Guest SIGILL handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    UnimplementedInstructionAddress = GetCursorAddress<uint64_t>();
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    hlt(0);
+  }
+
+  {
+    // Guest Overflow handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    OverflowExceptionInstructionAddress = GetCursorAddress<uint64_t>();
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    LoadConstant(x0, reinterpret_cast<uint64_t>(&SynchronousFaultData));
+    LoadConstant(w1, 1);
+    strb(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, FaultToTopAndGeneratedException)));
+    LoadConstant(w1, X86State::X86_TRAPNO_OF);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, TrapNo)));
+    LoadConstant(w1, 0x80);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, si_code)));
+    LoadConstant(x1, 0);
+    str(w1, MemOperand(x0, offsetof(Dispatcher::SynchronousFaultDataStruct, err_code)));
+
+    // hlt/udf = SIGILL
+    // brk = SIGTRAP
+    // ??? = SIGSEGV
+    // Force a SIGSEGV by loading zero
+    ldr(x1, MemOperand(x1));
+  }
+
  {
    ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
    if (SRAEnabled)
@@ -324,9 +436,89 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
    b(&LoopTop);
  }

-  place(&l_VirtualMemory);
+  // Long division helpers
+  uint64_t LUDIVHandler{};
+  uint64_t LDIVHandler{};
+  uint64_t LUREMHandler{};
+  uint64_t LREMHandler{};
+
+  {
+    LUDIVHandler = GetCursorAddress<uint64_t>();
+
+    PushDynamicRegsAndLR();
+
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIV)));
+
+    SpillStaticRegs();
+    blr(x3);
+    FillStaticRegs();
+
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    PopDynamicRegsAndLR();
+
+    // Go back to our code block
+    ret();
+  }
+
+  {
+    LDIVHandler = GetCursorAddress<uint64_t>();
+
+    PushDynamicRegsAndLR();
+
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIV)));
+
+    SpillStaticRegs();
+    blr(x3);
+    FillStaticRegs();
+
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    PopDynamicRegsAndLR();
+
+    // Go back to our code block
+    ret();
+  }
+
+  {
+    LUREMHandler = GetCursorAddress<uint64_t>();
+
+    PushDynamicRegsAndLR();
+
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUREM)));
+
+    SpillStaticRegs();
+    blr(x3);
+    FillStaticRegs();
+
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    PopDynamicRegsAndLR();
+
+    // Go back to our code block
+    ret();
+  }
+
+  {
+    LREMHandler = GetCursorAddress<uint64_t>();
+
+    PushDynamicRegsAndLR();
+
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LREM)));
+
+    SpillStaticRegs();
+    blr(x3);
+    FillStaticRegs();
+
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    PopDynamicRegsAndLR();
+
+    // Go back to our code block
+    ret();
+  }
+
  place(&l_PagePtr);
-  place(&l_L1Ptr);
  place(&l_CTX);
  place(&l_Sleep);
  place(&l_CompileBlock);
@@ -341,16 +533,38 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
  GetBuffer()->SetExecutable();

  if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(::gettid());
+    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
    CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
  }
  if (CTX->Config.GlobalJITNaming()) {
    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
  }
+
+  // Setup dispatcher specific pointers that need to be accessed from JIT code
+  {
+    auto &Pointers = ThreadState->CurrentFrame->Pointers.AArch64;
+
+    Pointers.DispatcherLoopTop = AbsoluteLoopTopAddress;
+    Pointers.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
+    Pointers.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
+    Pointers.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
+    Pointers.UnimplementedInstructionHandler = UnimplementedInstructionAddress;
+    Pointers.OverflowExceptionHandler = OverflowExceptionInstructionAddress;
+    Pointers.SignalReturnHandler = SignalHandlerReturnAddress;
+    Pointers.L1Pointer = Thread->LookupCache->GetL1Pointer();
+    Pointers.LUDIVHandler = LUDIVHandler;
+    Pointers.LDIVHandler = LDIVHandler;
+    Pointers.LUREMHandler = LUREMHandler;
+    Pointers.LREMHandler = LREMHandler;
+  }
 }

-void Arm64Dispatcher::SpillSRA(void *ucontext) {
+void Arm64Dispatcher::SpillSRA(void *ucontext, uint32_t IgnoreMask) {
  for(int i = 0; i < SRA64.size(); i++) {
+    if (IgnoreMask & (1U << SRA64[i].GetCode())) {
+      // Skip this one, it's already spilled
+      continue;
+    }
    ThreadState->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
  }

@@ -18,7 +18,7 @@ class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
    Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);

  protected:
-    void SpillSRA(void *ucontext) override;
+    void SpillSRA(void *ucontext, uint32_t IgnoreMask) override;
 };

 }
@@ -1,8 +1,8 @@

-#include "Common/MathUtils.h"
 #include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/X86HelperGen.h"
+#include "Interface/Core/CompileService.h"

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
@@ -12,12 +12,13 @@
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>

 #include <atomic>
 #include <condition_variable>
-#include <bits/types/siginfo_t.h>
+#include <csignal>
+#include <cstring>
 #include <signal.h>
-#include <string.h>

 namespace FEXCore::CPU {

@@ -27,15 +28,19 @@ void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuS
  --ctx->IdleWaitRefCount;
  ctx->IdleWaitCV.notify_all();

+  Thread->RunningEvents.ThreadSleeping = true;
+
  // Go to sleep
  Thread->StartRunning.Wait();

  Thread->RunningEvents.Running = true;
  ++ctx->IdleWaitRefCount;
+  Thread->RunningEvents.ThreadSleeping = false;
+
  ctx->IdleWaitCV.notify_all();
 }

-void Dispatcher::StoreThreadState(int Signal, void *ucontext) {
+ArchHelpers::Context::ContextBackup* Dispatcher::StoreThreadState(int Signal, void *ucontext) {
  // We can end up getting a signal at any point in our host state
  // Jump to a handler that saves all state so we can safely return
  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
@@ -65,13 +70,35 @@ void Dispatcher::StoreThreadState(int Signal, void *ucontext) {
  // Set the new SP
  ArchHelpers::Context::SetSp(ucontext, NewSP);

-  SignalFrames.push(NewSP);
+  // Signal frames are only used on the interpreter
+  // The JITS require the stack to be setup correctly on rt_sigreturn
+  if (CTX->Config.Core() == FEXCore::Config::CONFIG_INTERPRETER) {
+    SignalFrames.push(NewSP);
+  }
+
+  Context->Flags = 0;
+  Context->FPStateLocation = 0;
+  Context->UContextLocation = 0;
+  Context->SigInfoLocation = 0;
+
+  // Store fault to top status and then reset it
+  Context->FaultToTopAndGeneratedException = SynchronousFaultData.FaultToTopAndGeneratedException;
+  SynchronousFaultData.FaultToTopAndGeneratedException = false;
+
+  return Context;
 }

 void Dispatcher::RestoreThreadState(void *ucontext) {
-  LOGMAN_THROW_A(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
-  uint64_t OldSP = SignalFrames.top();
-  SignalFrames.pop();
+  uint64_t OldSP{};
+  if (CTX->Config.Core() == FEXCore::Config::CONFIG_IRJIT) {
+    OldSP = ArchHelpers::Context::GetSp(ucontext);
+  }
+  else {
+    LOGMAN_THROW_A_FMT(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
+    OldSP = SignalFrames.top();
+    SignalFrames.pop();
+  }
+
  uintptr_t NewSP = OldSP;
  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);

@@ -80,6 +107,139 @@ void Dispatcher::RestoreThreadState(void *ucontext) {

  // Now restore host state
  ArchHelpers::Context::RestoreContext(ucontext, Context);
+
+  if (Context->UContextLocation) {
+    auto Frame = ThreadState->CurrentFrame;
+
+    if (Context->Flags &ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT) {
+      // XXX: Unsupported since it needs state reconstruction
+      // If we are in the JIT then SRA might need to be restored to values from the context
+      // We can't currently support this since it might result in tearing without real state reconstruction
+    }
+
+    if (!(Context->Flags & ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT)) {
+      auto *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(Context->UContextLocation);
+      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<siginfo_t*>(Context->SigInfoLocation);
+
+      // If the guest modified the RIP then we need to take special precautions here
+      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] ||
+          Context->FaultToTopAndGeneratedException) {
+        // Hack! Go back to the top of the dispatcher top
+        // This is only safe inside the JIT rather than anything outside of it
+        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+        // Set our state register to point to our guest thread data
+        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP];
+        // XXX: Full context setting
+        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL];
+        for (size_t i = 0; i < 32; ++i) {
+          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
+        }
+
+        Frame->State.flags[1] = 1;
+        Frame->State.flags[9] = 1;
+
+#define COPY_REG(x) \
+            Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x];
+            COPY_REG(R8);
+            COPY_REG(R9);
+            COPY_REG(R10);
+            COPY_REG(R11);
+            COPY_REG(R12);
+            COPY_REG(R13);
+            COPY_REG(R14);
+            COPY_REG(R15);
+            COPY_REG(RDI);
+            COPY_REG(RSI);
+            COPY_REG(RBP);
+            COPY_REG(RBX);
+            COPY_REG(RDX);
+            COPY_REG(RAX);
+            COPY_REG(RCX);
+            COPY_REG(RSP);
+#undef COPY_REG
+        FEXCore::x86_64::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+        // Copy float registers
+        memcpy(Frame->State.mm, fpstate->_st, sizeof(Frame->State.mm));
+        memcpy(Frame->State.xmm, fpstate->_xmm, sizeof(Frame->State.xmm));
+
+        // FCW store default
+        Frame->State.FCW = fpstate->fcw;
+        Frame->State.FTW = fpstate->ftw;
+
+        // Deconstruct FSW
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
+      }
+    }
+    else {
+      auto *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(Context->UContextLocation);
+      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(Context->SigInfoLocation);
+      // If the guest modified the RIP then we need to take special precautions here
+      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] ||
+          Context->FaultToTopAndGeneratedException) {
+        // Hack! Go back to the top of the dispatcher top
+        // This is only safe inside the JIT rather than anything outside of it
+        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+        // Set our state register to point to our guest thread data
+        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+        // XXX: Full context setting
+        // First 32-bytes of flags is EFLAGS broken out
+        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL];
+        for (size_t i = 0; i < 32; ++i) {
+          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
+        }
+
+        Frame->State.flags[1] = 1;
+        Frame->State.flags[9] = 1;
+
+        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP];
+        Frame->State.cs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS];
+        Frame->State.ds = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS];
+        Frame->State.es = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES];
+        Frame->State.fs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS];
+        Frame->State.gs = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS];
+        Frame->State.ss = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS];
+#define COPY_REG(x) \
+      Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x];
+        COPY_REG(RDI);
+        COPY_REG(RSI);
+        COPY_REG(RBP);
+        COPY_REG(RBX);
+        COPY_REG(RDX);
+        COPY_REG(RAX);
+        COPY_REG(RCX);
+        COPY_REG(RSP);
+#undef COPY_REG
+        FEXCore::x86::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+
+        // Copy float registers
+        for (size_t i = 0; i < 8; ++i) {
+          // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
+          memcpy(&Frame->State.mm[i], &fpstate->_st[i], 10);
+        }
+
+        // Extended XMM state
+        memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+        // FCW store default
+        Frame->State.FCW = fpstate->fcw;
+        Frame->State.FTW = fpstate->ftw;
+
+        // Deconstruct FSW
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
+        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
+      }
+    }
+  }
 }

 static uint32_t ConvertSignalToTrapNo(int Signal, siginfo_t *HostSigInfo) {
@@ -115,7 +275,8 @@ static uint32_t ConvertSignalToError(int Signal, siginfo_t *HostSigInfo) {
 }

 bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  StoreThreadState(Signal, ucontext);
+  auto ContextBackup = StoreThreadState(Signal, ucontext);
+
  auto Frame = ThreadState->CurrentFrame;

  // Ref count our faults
@@ -140,15 +301,42 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
  // Otherwise we might load garbage
  if (SRAEnabled) {
    if (IsAddressInJITCode(OldPC, false)) {
+      uint32_t IgnoreMask{};
+#ifdef _M_ARM_64
+      if (Frame->InSyscallInfo != 0) {
+        // We are in a syscall, this means we are in a weird register state
+        // We need to spill SRA but only some of it, since some values have already been spilled
+        // Lower 16 bits tells us which registers are already spilled to the context
+        // So we ignore spilling those ones
+        uint16_t NumRegisters = std::popcount(Frame->InSyscallInfo & 0xFFFF);
+        if (NumRegisters >= 4) {
+          // Unhandled case
+          IgnoreMask = 0;
+        }
+        else {
+          IgnoreMask = Frame->InSyscallInfo & 0xFFFF;
+        }
+      }
+      else {
+        // We must spill everything
+        IgnoreMask = 0;
+      }
+#endif
+
      // We are in jit, SRA must be spilled
-      SpillSRA(ucontext);
+      SpillSRA(ucontext, IgnoreMask);
+
+      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT;
    } else {
      if (!IsAddressInJITCode(OldPC, true)) {
        // This is likely to cause issues but in some cases it isn't fatal
        // This can also happen if we have put a signal on hold, then we just reenabled the signal
        // So we are in the syscall handler
        // Only throw a log message in this case
-        LogMan::Msg::E("Signals in dispatcher have unsynchronized context");
+        if constexpr (false) {
+          // XXX: Messages in the signal handler can cause us to crash
+          LogMan::Msg::EFmt("Signals in dispatcher have unsynchronized context");
+        }
      }
    }
  }
@@ -180,8 +368,10 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
  // siginfo_t
  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);

-  if (GuestAction->sa_flags & SA_SIGINFO) {
+  // Backup where we think the RIP currently is
+  ContextBackup->OriginalRIP = Frame->State.rip;

+  if (GuestAction->sa_flags & SA_SIGINFO) {
    // Setup ucontext a bit
    if (Is64BitMode) {
      NewGuestSP -= sizeof(FEXCore::x86_64::_libc_fpstate);
@@ -196,6 +386,10 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      NewGuestSP = AlignDown(NewGuestSP, alignof(siginfo_t));
      uint64_t SigInfoLocation = NewGuestSP;

+      ContextBackup->FPStateLocation = FPStateLocation;
+      ContextBackup->UContextLocation = UContextLocation;
+      ContextBackup->SigInfoLocation = SigInfoLocation;
+
      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);

@@ -209,8 +403,23 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+
+      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
+      // SI_USER could also potentially have random data in it, needs to be bit perfect
+      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
+      *guest_siginfo = *HostSigInfo;
+
+      if (ContextBackup->FaultToTopAndGeneratedException) {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = SynchronousFaultData.TrapNo;
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = SynchronousFaultData.err_code;
+
+        // Overwrite si_code
+        guest_siginfo->si_code = SynchronousFaultData.si_code;
+      }
+      else {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
+      }
      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;

@@ -255,15 +464,12 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;

-      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
-      // SI_USER could also potentially have random data in it, needs to be bit perfect
-      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
-      *guest_siginfo = *HostSigInfo;
-
      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
    }
    else {
+      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT;
+
      NewGuestSP -= sizeof(FEXCore::x86::_libc_fpstate);
      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::_libc_fpstate));
      uint64_t FPStateLocation = NewGuestSP;
@@ -276,6 +482,10 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::siginfo_t));
      uint64_t SigInfoLocation = NewGuestSP;

+      ContextBackup->FPStateLocation = FPStateLocation;
+      ContextBackup->UContextLocation = UContextLocation;
+      ContextBackup->SigInfoLocation = SigInfoLocation;
+
      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
      FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);

@@ -290,8 +500,16 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+      if (ContextBackup->FaultToTopAndGeneratedException) {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = SynchronousFaultData.TrapNo;
+        guest_siginfo->si_code = SynchronousFaultData.si_code;
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = SynchronousFaultData.err_code;
+      }
+      else {
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
+        guest_siginfo->si_code = HostSigInfo->si_code;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
+      }
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs;
      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
@@ -339,7 +557,6 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
      // These three elements are in every siginfo
      guest_siginfo->si_signo = HostSigInfo->si_signo;
      guest_siginfo->si_errno = HostSigInfo->si_errno;
-      guest_siginfo->si_code = HostSigInfo->si_code;

      switch (Signal) {
        case SIGSEGV:
@@ -368,7 +585,7 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
          guest_siginfo->_sifields._timer.sigval.sival_int = HostSigInfo->si_int;
          break;
        default:
-          LogMan::Msg::E("Unhandled siginfo_t for signal: %d\n", Signal);
+          LogMan::Msg::EFmt("Unhandled siginfo_t for signal: {}\n", Signal);
          break;
      }

@@ -402,7 +619,7 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
  else {
    NewGuestSP -= 4;
    *(uint32_t*)NewGuestSP = SignalReturn;
-    LOGMAN_THROW_A(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
+    LOGMAN_THROW_A_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
  }

@@ -454,7 +671,8 @@ bool Dispatcher::HandleSignalPause(int Signal, void *info, void *ucontext) {
    } else {
      if (SRAEnabled) {
        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+        LOGMAN_THROW_A_FMT(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true),
+                           "Signals in dispatcher have unsynchronized context");
      }
      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
    }
@@ -486,11 +704,21 @@ bool Dispatcher::HandleSignalPause(int Signal, void *info, void *ucontext) {
    } else {
      if (SRAEnabled) {
        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+        LOGMAN_THROW_A_FMT(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true),
+                           "Signals in dispatcher have unsynchronized context");
      }
      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
    }

+    // We need to be a little bit careful here
+    // If we were already paused (due to GDB) and we are immediately stopping (due to gdb kill)
+    // Then we need to ensure we don't double decrement our idle thread counter
+    if (ThreadState->RunningEvents.ThreadSleeping) {
+      // If the thread was sleeping then its idle counter was decremented
+      // Reincrement it here to not break logic
+      ++ThreadState->CTX->IdleWaitRefCount;
+    }
+
    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
    return true;
  }
@@ -531,15 +759,19 @@ void Dispatcher::RemoveCodeBuffer(uint8_t* start_to_remove) {
  }
 }

-bool Dispatcher::IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher) const {
+bool Dispatcher::IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher, bool IncludeCompileService) const {
  for (auto [start, end] : CodeBuffers) {
    if (Address >= start && Address < end) {
      return true;
    }
  }

-  if (IncludeDispatcher) {
-    return IsAddressInDispatcher(Address);
+  if (IncludeDispatcher && IsAddressInDispatcher(Address)) {
+    return true;
+  }
+
+  if (IncludeCompileService &&  ThreadState->CompileService && ThreadState->CompileService->IsAddressInJITCode(Address)) {
+    return true;
  }
  return false;
 }
@@ -3,9 +3,10 @@
 #include <FEXCore/Core/CPUBackend.h>

 #include "Interface/Context/Context.h"
+#include "Interface/Core/ArchHelpers/MContext.h"

-#include <bits/types/stack_t.h>
 #include <cstdint>
+#include <signal.h>
 #include <stddef.h>
 #include <stack>
 #include <tuple>
@@ -47,11 +48,20 @@ public:
  uint64_t ThreadPauseHandlerAddressSpillSRA{};
  uint64_t ExitFunctionLinkerAddress{};
  uint64_t SignalHandlerReturnAddress{};
+  uint64_t UnimplementedInstructionAddress{};
+  uint64_t OverflowExceptionInstructionAddress{};
+
  uint64_t PauseReturnInstruction{};

  /**  @} */

  uint32_t SignalHandlerRefCounter{};
+  struct SynchronousFaultDataStruct {
+    bool FaultToTopAndGeneratedException{};
+    uint32_t TrapNo;
+    uint32_t err_code;
+    uint32_t si_code;
+  } SynchronousFaultData;

  uint64_t Start{};
  uint64_t End{};
@@ -67,7 +77,7 @@ public:

  void RemoveCodeBuffer(uint8_t* start);

-  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true) const;
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true, bool IncludeCompileService = true) const;
  bool IsAddressInDispatcher(uint64_t Address) const {
    return Address >= Start && Address < End;
  }
@@ -77,12 +87,12 @@ protected:
    : CTX {ctx}
    , ThreadState {Thread} {}

-  void StoreThreadState(int Signal, void *ucontext);
+  ArchHelpers::Context::ContextBackup* StoreThreadState(int Signal, void *ucontext);
  void RestoreThreadState(void *ucontext);
-  std::stack<uint64_t> SignalFrames;
+  std::stack<uint64_t, std::vector<uint64_t>> SignalFrames;

  bool SRAEnabled = false;
-  virtual void SpillSRA(void *ucontext) {}
+  virtual void SpillSRA(void *ucontext, uint32_t IgnoreMask) {}

  FEXCore::Context::Context *CTX;
  FEXCore::Core::InternalThreadState *ThreadState;
@@ -11,6 +11,7 @@
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Allocator.h>
+#include <FEXHeaderUtils/Syscalls.h>

 #include <cmath>
 #include <memory>
@@ -94,7 +95,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);

    // L1 Cache
-    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(r13, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.L1Pointer)]);
    mov(rax, rdx);

    and_(rax, LookupCache::L1_ENTRIES_MASK);
@@ -113,8 +114,9 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
    mov(r13, Thread->LookupCache->GetPagePointer());

    // Full lookup
+    uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
    mov(rax, rdx);
-    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
+    mov(rbx, VirtualMemorySize - 1);
    and_(rax, rbx);
    shr(rax, 12);

@@ -141,8 +143,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
    je(NoBlock);

    // Update L1
-    
-    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(r13, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.L1Pointer)]);
    mov(rcx, rdx);
    and_(rcx, LookupCache::L1_ENTRIES_MASK);
    shl(rcx, 1);
@@ -251,8 +252,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
    // XXX: XMM?

    // Make sure to adjust the refcounter so we don't clear the cache now
-    mov(rax, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
-    add(dword [rax], 1);
+    add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.SignalHandlerRefCountPointer)], 1);

    // Now push the callback return trampoline to the guest stack
    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
@@ -274,10 +274,33 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
  {
    // Signal return handler
    SignalHandlerReturnAddress = getCurr<uint64_t>();
-
    ud2();
  }

+  {
+    // Guest SIGILL handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    UnimplementedInstructionAddress = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    // Guest Overflow handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    OverflowExceptionInstructionAddress = getCurr<uint64_t>();
+
+    // ud2 = SIGILL
+    // int3 = SIGTRAP
+    // hlt = SIGSEGV
+
+    mov(rax, reinterpret_cast<uint64_t>(&SynchronousFaultData));
+    add(byte [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, FaultToTopAndGeneratedException)], 1);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, TrapNo)], X86State::X86_TRAPNO_OF);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, err_code)], 0);
+    mov(dword [rax + offsetof(Dispatcher::SynchronousFaultDataStruct, si_code)], 0x80);
+
+    hlt();
+  }

  {
    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
@@ -307,12 +330,26 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
  End = Start + getSize();

  if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(::gettid());
+    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
    CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
  }
  if (CTX->Config.GlobalJITNaming()) {
    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(Start), End-Start);
  }
+
+  // Setup dispatcher specific pointers that need to be accessed from JIT code
+  {
+    auto &Pointers = ThreadState->CurrentFrame->Pointers.X86;
+
+    Pointers.DispatcherLoopTop = AbsoluteLoopTopAddress;
+    Pointers.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
+    Pointers.ThreadStopHandler = ThreadStopHandlerAddress;
+    Pointers.ThreadPauseHandler = ThreadPauseHandlerAddress;
+    Pointers.UnimplementedInstructionHandler = UnimplementedInstructionAddress;
+    Pointers.OverflowExceptionHandler = OverflowExceptionInstructionAddress;
+    Pointers.SignalReturnHandler = SignalHandlerReturnAddress;
+    Pointers.L1Pointer = Thread->LookupCache->GetL1Pointer();
+  }
 }

 X86Dispatcher::~X86Dispatcher() {
@@ -192,7 +192,7 @@ Decoder::~Decoder() {

 uint8_t Decoder::ReadByte() {
  uint8_t Byte = InstStream[InstructionSize];
-  LOGMAN_THROW_A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
+  LOGMAN_THROW_A_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
  Instruction[InstructionSize] = Byte;
  InstructionSize++;
  return Byte;
@@ -209,7 +209,7 @@ uint64_t Decoder::ReadData(uint8_t Size) {
  }

  if (Size > sizeof(uint64_t)) {
-    LOGMAN_MSG_A("Unknown data size to read");
+    LOGMAN_MSG_A_FMT("Unknown data size to read");
    return 0;
  }

@@ -351,10 +351,9 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
    Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
    Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);

-    uint64_t Literal {0};
-    LOGMAN_THROW_A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
+    LOGMAN_THROW_A_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");

-    Literal = ReadData(Displacement);
+    uint64_t Literal = ReadData(Displacement);
    if (Displacement == 1) {
      Literal = static_cast<int8_t>(Literal);
    }
@@ -364,8 +363,7 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
    // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
    if (ModRM.rm == 0b101) {
      // 32bit Displacement
-      uint32_t Literal;
-      Literal = ReadData(4);
+      const uint32_t Literal = ReadData(4);

      Operand->Type = DecodedOperand::OpType::RIPRelative;
      Operand->Data.RIPLiteral.Value.u = Literal;
@@ -378,8 +376,7 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
  }
  else {
    uint8_t DisplacementSize = ModRM.mod == 1 ? 1 : 4;
-    uint32_t Literal{};
-    Literal = ReadData(DisplacementSize);
+    uint32_t Literal = ReadData(DisplacementSize);
    if (DisplacementSize == 1) {
      Literal = static_cast<int8_t>(Literal);
    }
@@ -397,26 +394,26 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,

  // XXX: Once we support 32bit x86 then this will be necessary to support
  if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::D("Legacy Prefix");
+    LogMan::Msg::DFmt("Legacy Prefix");
    return false;
  }

  if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
-    LogMan::Msg::D("Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
    return false;
  }

  if (Info->Type == FEXCore::X86Tables::TYPE_INVALID) {
-    LogMan::Msg::D("Invalid or Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Invalid or Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
    return false;
  }

-  LOGMAN_THROW_A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
-    "Group Ops should have been decoded before this!");
+  LOGMAN_THROW_A_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
+                     "Group Ops should have been decoded before this!");

  uint8_t DestSize{};
  const bool HasWideningDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST) != 0 ||
-                                       Options.w;
+                                       (Options.w && CTX->Config.Is64BitMode);
  const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;

  bool HasXMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
@@ -535,7 +532,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
  }

  if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
-    LOGMAN_THROW_A(!HasMODRM, "This instruction shouldn't have ModRM!");
+    LOGMAN_THROW_A_FMT(!HasMODRM, "This instruction shouldn't have ModRM!");

    // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
    // This also means that the destination is always a GPR on these ones
@@ -586,8 +583,11 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
        return false;
    }
    else {
-      auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
-      (this->*Disp)(&NonGPR, ModRM);
+      // Only decode if we haven't pre-decoded
+      if (NonGPR.IsNone()) {
+        auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
+        (this->*Disp)(&NonGPR, ModRM);
+      }
    }

    return true;
@@ -641,7 +641,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
  }

  if (Bytes != 0) {
-    LOGMAN_THROW_A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
+    LOGMAN_THROW_A_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src");

    DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;

@@ -666,7 +666,8 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
  }

-  LOGMAN_THROW_A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
+  LOGMAN_THROW_A_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining",
+                     DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name ?: "UND", InstructionSize, Bytes);
  DecodeInst->InstSize = InstructionSize;
  return true;
 }
@@ -677,21 +678,22 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16

  // XXX: Once we support 32bit x86 then this will be necessary to support
  if (Info->Type == FEXCore::X86Tables::TYPE_LEGACY_PREFIX) {
-    LogMan::Msg::D("Legacy Prefix");
+    LogMan::Msg::DFmt("Legacy Prefix");
    return false;
  }

  if (Info->Type == FEXCore::X86Tables::TYPE_UNKNOWN) {
-    LogMan::Msg::D("Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
    return false;
  }

  if (Info->Type == FEXCore::X86Tables::TYPE_INVALID) {
-    LogMan::Msg::D("Invalid or Unknown instruction: %s 0x%04x 0x%lx", Info->Name, Op, DecodeInst->PC);
+    LogMan::Msg::DFmt("Invalid or Unknown instruction: {} 0x{:04x} 0x{:x}", Info->Name ?: "UND", Op, DecodeInst->PC);
    return false;
  }

-  LOGMAN_THROW_A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
+  LOGMAN_THROW_A_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX,
+                     "REX PREFIX should have been decoded before this!");

  if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
      Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
@@ -747,7 +749,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
        3,
      };
      uint8_t Field = RegToField[ModRM.reg];
-      LOGMAN_THROW_A(Field != 255, "Invalid field selected!");
+      LOGMAN_THROW_A_FMT(Field != 255, "Invalid field selected!");

      LocalOp = (Field << 3) | ModRM.rm;
      return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp);
@@ -775,6 +777,11 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
    const uint8_t Byte1 = ReadByte();
    DecodedHeader options{};

+    if ((Byte1 & 0b10000000) == 0) {
+      LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.R shouldn't be 0 in 32-bit mode!");
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_R;
+    }
+
    if (Op == 0xC5) { // Two byte VEX
      pp = Byte1 & 0b11;
      options.vvvv = 15 - ((Byte1 & 0b01111000) >> 3);
@@ -785,8 +792,15 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
      map_select = Byte1 & 0b11111;
      options.vvvv = 15 - ((Byte2 & 0b01111000) >> 3);
      options.w = (Byte2 & 0b10000000) != 0;
+      if ((Byte1 & 0b01000000) == 0) {
+        LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "VEX.X shouldn't be 0 in 32-bit mode!");
+        DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
+      }
+      if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) {
+        DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
+      }
      if (!(map_select >= 1 && map_select <= 3)) {
-        LogMan::Msg::E("We don't understand a map_select of: %d", map_select);
+        LogMan::Msg::EFmt("We don't understand a map_select of: {}", map_select);
        return false;
      }
    }
@@ -846,7 +860,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
    case 0x0F: {// Escape Op
      uint8_t EscapeOp = ReadByte();
      switch (EscapeOp) {
-      case 0x0F: { // 3DNow!
+      case 0x0F: [[unlikely]] { // 3DNow!
        // 3DNow! Instruction Encoding: 0F 0F [ModRM] [SIB] [Displacement] [Opcode]
        // Decode ModRM
        uint8_t ModRMByte = ReadByte();
@@ -859,8 +873,12 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
        const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
          DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;

-        auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
-        (this->*Disp)(&DecodeInst->Src[0], ModRM);
+        // All 3DNow! instructions have the second argument as the rm handler
+        // We need to decode it upfront to get the displacement out of the way
+        if (ModRM.mod != 0b11) {
+          auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
+          (this->*Disp)(&DecodeInst->Src[0], ModRM);
+        }

        // Take a peek at the op just past the displacement
        uint8_t LocalOp = ReadByte();
@@ -869,14 +887,20 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
      }
      case 0x38: { // F38 Table!
        constexpr uint16_t PF_38_NONE = 0;
-        constexpr uint16_t PF_38_66 = 1;
-        constexpr uint16_t PF_38_F2 = 2;
+        constexpr uint16_t PF_38_66   = (1U << 0);
+        constexpr uint16_t PF_38_F2   = (1U << 1);
+        constexpr uint16_t PF_38_F3   = (1U << 2);

        uint16_t Prefix = PF_38_NONE;
-        if (DecodeInst->LastEscapePrefix == 0xF2) // REPNE
-          Prefix = PF_38_F2;
-        else if (DecodeInst->LastEscapePrefix == 0x66) // Operand Size
-          Prefix = PF_38_66;
+        if (DecodeInst->Flags & DecodeFlags::FLAG_OPERAND_SIZE) {
+          Prefix |= PF_38_66;
+        }
+        if (DecodeInst->Flags & DecodeFlags::FLAG_REPNE_PREFIX) {
+          Prefix |= PF_38_F2;
+        }
+        if (DecodeInst->Flags & DecodeFlags::FLAG_REP_PREFIX) {
+          Prefix |= PF_38_F3;
+        }

        uint16_t LocalOp = (Prefix << 8) | ReadByte();
        return NormalOpHeader(&FEXCore::X86Tables::H0F38TableOps[LocalOp], LocalOp);
@@ -991,7 +1015,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
      auto Info = &FEXCore::X86Tables::BaseOps[Op];

      if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-        LOGMAN_THROW_A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
+        LOGMAN_THROW_A_FMT(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
        DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;

        // Widening displacement
@@ -1044,13 +1068,13 @@ void Decoder::BranchTargetInMultiblockRange() {
      // auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
      // auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
      // Target offset is PC + InstSize + Literal
-      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
    break;
    }
    case 0xE9:
    case 0xEB: // Both are unconditional JMP instructions
-      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
      Conditional = false;
    break;
@@ -1116,7 +1140,7 @@ const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, u
  return _InstStream - EntryPoint + RIP;
 }

-bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
+void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
  Blocks.clear();
  BlocksToDecode.clear();
  HasBlocks.clear();
@@ -1130,7 +1154,6 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
  EntryPoint = PC;
  InstStream = _InstStream;

-  bool ErrorDuringDecoding = false;
  uint64_t TotalInstructions{};

  // If we don't have symbols available then we become a bit optimistic about multiblock ranges
@@ -1162,20 +1185,15 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
    InstStream = AdjustAddrForSpecialRegion(_InstStream, EntryPoint, RIPToDecode);

    while (1) {
-      ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
+      bool ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);

      if (ErrorDuringDecoding) {
-        LogMan::Msg::D("Couldn't Decode something at 0x%lx, Started at 0x%lx", PC + PCOffset, PC);
-        if (Blocks.size() == 1) {
-          return false;
-        }
-        LOGMAN_THROW_A(Blocks.size() != 1, "Decode Error in entry block");
-
+        LogMan::Msg::DFmt("Couldn't Decode something at 0x{:x}, Started at 0x{:x}", PC + PCOffset, PC);
+        // Put an invalid instruction in the stream so the core can raise SIGILL if hit
        CurrentBlockDecoding.HasInvalidInstruction = true;
-        if (ErrorDuringDecoding && Blocks.size() != 1) {
-          ErrorDuringDecoding = false;
-        }
-        break;
+        // Error while decoding instruction. We don't know the table or instruction size
+        DecodeInst->TableInfo = nullptr;
+        DecodeInst->InstSize = 0;
      }

      DecodedMinAddress = std::min(DecodedMinAddress, RIPToDecode + PCOffset);
@@ -1184,6 +1202,11 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
      ++BlockNumberOfInstructions;
      ++DecodedSize;

+      // Can not continue this block at all on invalid instruction
+      if (CurrentBlockDecoding.HasInvalidInstruction) {
+        break;
+      }
+
      bool CanContinue = false;
      if (!(DecodeInst->TableInfo->Flags &
          (FEXCore::X86Tables::InstFlags::FLAGS_BLOCK_END | FEXCore::X86Tables::InstFlags::FLAGS_SETS_RIP))) {
@@ -1228,7 +1251,6 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
  std::sort(Blocks.begin(), Blocks.end(), [](const FEXCore::Frontend::Decoder::DecodedBlocks& a, const FEXCore::Frontend::Decoder::DecodedBlocks& b) {
    return a.Entry < b.Entry;
  });
-  return !ErrorDuringDecoding;
 }

 }
@@ -27,7 +27,7 @@ public:

  Decoder(FEXCore::Context::Context *ctx);
  ~Decoder();
-  bool DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
+  void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);

  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
    return &Blocks;
@@ -35,7 +35,7 @@ public:

  uint64_t DecodedMinAddress {};
  uint64_t DecodedMaxAddress {~0ULL};
-  
+
  void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
 private:
@@ -91,7 +91,7 @@ private:
  void DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
  void DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);

-  const std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp {
+  static constexpr std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp{
    &FEXCore::Frontend::Decoder::DecodeModRM_64,
    &FEXCore::Frontend::Decoder::DecodeModRM_16,
  };
@@ -6,8 +6,10 @@ $end_info$
 #pragma once

 #include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/Threads.h>

+#include <atomic>
 #include <istream>
 #include <memory>
 #include <mutex>
@@ -27,9 +29,14 @@ public:
    // Public for threading
    void GdbServerLoop();

+    void AlertLibrariesChanged() {
+      LibraryMapChanged = true;
+    }
+
 private:
    void Break(int signal);

+    void OpenListenSocket();
    std::unique_ptr<std::iostream> OpenSocket();
    void StartThread();
    std::string ReadPacket(std::iostream &stream);
@@ -37,6 +44,9 @@ private:

    void SendACK(std::ostream &stream, bool NACK);

+    Event ThreadBreakEvent{};
+    void WaitForThreadWakeup();
+
    struct HandledPacketType {
      std::string Response{};
      enum ResponseType {
@@ -60,6 +70,8 @@ private:
    HandledPacketType handleBreakpoint(const std::string &packet);
    HandledPacketType handleProgramOffsets();

+    HandledPacketType ThreadAction(char action, uint32_t tid);
+
    std::string readRegs();
    HandledPacketType readReg(const std::string& packet);

@@ -69,8 +81,17 @@ private:
    std::mutex sendMutex;
    bool SettingNoAckMode{false};
    bool NoAckMode{false};
+    bool NonStopMode{false};
    std::string ThreadString{};
+    std::string OSDataString{};
+    void buildLibraryMap();
+    std::atomic<bool> LibraryMapChanged = true;
+    std::string LibraryMapString{};
+
+    // Used to keep track of which signals to pass to the guest
+    std::array<bool, SignalDelegator::MAX_SIGNALS + 1> PassSignals{};
    uint32_t CurrentDebuggingThread{};
+    int ListenSocket{};
    FEX_CONFIG_OPT(Filename, APP_FILENAME);
 };

@@ -1,3 +1,4 @@
+#include "Interface/Core/CPUID.h"
 #include "Interface/Core/HostFeatures.h"

 #ifdef _M_ARM_64
@@ -13,14 +14,117 @@

 namespace FEXCore {

+// Data Zero Prohibited flag
+// 0b0 = ZVA/GVA/GZVA permitted
+// 0b1 = ZVA/GVA/GZVA prohibited
+constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
+// Log2 of the blocksize in 32-bit words
+constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
+
+#ifdef _M_ARM_64
+static uint32_t GetDCZID() {
+  uint64_t Result{};
+  __asm("mrs %[Res], DCZID_EL0"
+      : [Res] "=r" (Result));
+  return Result;
+}
+
+static uint32_t GetFPCR() {
+  uint64_t Result{};
+  __asm ("mrs %[Res], FPCR"
+    : [Res] "=r" (Result));
+  return Result;
+}
+
+static void SetFPCR(uint64_t Value) {
+  __asm ("msr FPCR, %[Value]"
+    :: [Value] "r" (Value));
+}
+
+#else
+static uint32_t GetDCZID() {
+  // Return unsupported
+  return DCZID_DZP_MASK;
+}
+#endif
+
+
 HostFeatures::HostFeatures() {
 #ifdef _M_ARM_64
  auto Features = vixl::CPUFeatures::InferFromOS();
  SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
+  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
+  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
+  SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
+
+  // Only supported when FEAT_AFP is supported
+  SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
+
+  // RCPC is bugged on Snapdragon 865
+  // Causes glibc cond16 test to immediately throw assert
+  // __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
+  SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
+
+  // We need to get the CPU's cache line size
+  // We expect sane targets that have correct cacheline sizes across clusters
+  uint64_t CTR;
+  __asm volatile ("mrs %[ctr], ctr_el0"
+    : [ctr] "=r"(CTR));
+
+  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
+  ICacheLineSize = 4 << (CTR & 0xF);
+
+  if (!SupportsAtomics) {
+    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
+  }
 #endif
 #ifdef _M_X86_64
  Xbyak::util::Cpu Features{};
  SupportsAES = Features.has(Xbyak::util::Cpu::tAESNI);
+  SupportsCRC = Features.has(Xbyak::util::Cpu::tSSE42);
+  SupportsRAND = Features.has(Xbyak::util::Cpu::tRDRAND) && Features.has(Xbyak::util::Cpu::tRDSEED);
+
+  // xbyak doesn't know how to check for CLZero
+  uint32_t eax, ebx, ecx, edx;
+  // First ensure we support a new enough extended CPUID function range
+  __cpuid(0x8000'0000, eax, ebx, ecx, edx);
+  if (eax >= 0x8000'0008U) {
+    // CLZero defined in 8000_00008_EBX[bit 0]
+    __cpuid(0x8000'0008, eax, ebx, ecx, edx);
+    SupportsCLZERO = ebx & 1;
+  }
+
+  SupportsFlushInputsToZero = true;
+  SupportsFloatExceptions = true;
+#else
+  // Test if this CPU supports float exception trapping by attempting to enable
+  // On unsupported these bits are architecturally defined as RAZ/WI
+  constexpr uint32_t ExceptionEnableTraps =
+    (1U << 8) |  // Invalid Operation float exception trap enable
+    (1U << 9) |  // Divide by zero float exception trap enable
+    (1U << 10) | // Overflow float exception trap enable
+    (1U << 11) | // Underflow float exception trap enable
+    (1U << 12) | // Inexact float exception trap enable
+    (1U << 15);  // Input Denormal float exception trap enable
+
+  uint32_t OriginalFPCR = GetFPCR();
+  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
+  SetFPCR(FPCR);
+  FPCR = GetFPCR();
+  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
+
+  // Set FPCR back to original just in case anything changed
+  SetFPCR(OriginalFPCR);
 #endif
+
+  // Check if we can support cacheline clears
+  uint32_t DCZID = GetDCZID();
+  if ((DCZID & DCZID_DZP_MASK) == 0) {
+    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
+    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
+    // If the DC ZVA size matches the emulated cache line size
+    // This means we can use the instruction
+    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
+  }
 }
 }
@@ -1,9 +1,28 @@
 #pragma once
+#include <cstdint>

 namespace FEXCore {
 class HostFeatures final {
  public:
    HostFeatures();
+
+    /**
+     * @brief Backend features that change how codegen is generated from IR
+     *
+     * Specifically things that affect the IR->Codegen process
+     * Not the x86->IR process
+     */
+    uint32_t DCacheLineSize{};
+    uint32_t ICacheLineSize{};
    bool SupportsAES{};
+    bool SupportsCRC{};
+    bool SupportsCLZERO{};
+    bool SupportsAtomics{};
+    bool SupportsRCPC{};
+    bool SupportsRAND{};
+
+    // Float exception behaviour
+    bool SupportsFlushInputsToZero{};
+    bool SupportsFloatExceptions{};
 };
 }
@@ -13,12 +13,12 @@ $end_info$
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)

 DEF_OP(TruncElementPair) {
  auto Op = IROp->C<IR::IROp_TruncElementPair>();

-  switch (Op->Size) {
+  switch (IROp->Size) {
    case 4: {
      uint64_t *Src = GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
      uint64_t Result{};
@@ -27,7 +27,7 @@ DEF_OP(TruncElementPair) {
      GD = Result;
      break;
    }
-    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", IROp->Size); break;
  }
 }

@@ -38,7 +38,13 @@ DEF_OP(Constant) {

 DEF_OP(EntrypointOffset) {
  auto Op = IROp->C<IR::IROp_EntrypointOffset>();
-  GD = Data->CurrentEntry + Op->Offset;
+  uint64_t Mask = ~0ULL;
+  uint8_t OpSize = IROp->Size;
+  if (OpSize == 4) {
+    Mask = 0xFFFF'FFFFULL;
+  }
+
+  GD = (Data->CurrentEntry + Op->Offset) & Mask;
 }

 DEF_OP(InlineConstant) {
@@ -493,6 +499,54 @@ DEF_OP(Extr) {
  }
 }

+DEF_OP(PDep) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  if (OpSize != 4 && OpSize != 8) {
+    LOGMAN_MSG_A_FMT("Unknown PDep Size: {}\n", OpSize);
+    return;
+  }
+
+  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(0))
+                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(0));
+  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(1))
+                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(1));
+
+  uint64_t Result = 0;
+  for (uint64_t Index = 0; Mask > 0; Index++) {
+    const uint64_t Offset = std::countr_zero(Mask);
+    Mask &= Mask - 1;
+    Result |= ((Input >> Index) & 1) << Offset;
+  }
+
+  GD = Result;
+}
+
+DEF_OP(PExt) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  if (OpSize != 4 && OpSize != 8) {
+    LOGMAN_MSG_A_FMT("Unknown PExt Size: {}\n", OpSize);
+    return;
+  }
+
+  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(0))
+                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(0));
+  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(1))
+                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(1));
+
+  uint64_t Result = 0;
+  for (uint64_t Offset = 0; Mask > 0; Offset++) {
+    const uint64_t Index = std::countr_zero(Mask);
+    Mask &= Mask - 1;
+    Result |= ((Input >> Index) & 1) << Offset;
+  }
+
+  GD = Result;
+}
+
 DEF_OP(LDiv) {
  auto Op = IROp->C<IR::IROp_LDiv>();
  uint8_t OpSize = IROp->Size;
@@ -787,9 +841,8 @@ DEF_OP(Bfi) {

 DEF_OP(Bfe) {
  auto Op = IROp->C<IR::IROp_Bfe>();
-  uint8_t OpSize = IROp->Size;

-  LOGMAN_THROW_A_FMT(OpSize <= 8, "OpSize is too large for BFE: {}", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
  uint64_t SourceMask = (1ULL << Op->Width) - 1;
  if (Op->Width == 64)
    SourceMask = ~0ULL;
@@ -800,9 +853,8 @@ DEF_OP(Bfe) {

 DEF_OP(Sbfe) {
  auto Op = IROp->C<IR::IROp_Sbfe>();
-  uint8_t OpSize = IROp->Size;

-  LOGMAN_THROW_A_FMT(OpSize <= 8, "OpSize is too large for SBFE: {}", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for SBFE: {}", IROp->Size);
  int64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
  uint64_t ShiftLeftAmount = (64 - (Op->Width + Op->lsb));
  uint64_t ShiftRightAmount = ShiftLeftAmount + Op->lsb;
@@ -841,15 +893,14 @@ DEF_OP(Select) {

 DEF_OP(VExtractToGPR) {
  auto Op = IROp->C<IR::IROp_VExtractToGPR>();
-  uint8_t OpSize = IROp->Size;

  uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Header.Args[0]);

-  LOGMAN_THROW_A_FMT(OpSize <= 16, "OpSize is too large for VExtractToGPR: {}", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 16, "OpSize is too large for VExtractToGPR: {}", IROp->Size);

  if (SourceSize == 16) {
    __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
-    uint64_t Shift = Op->Header.ElementSize * Op->Idx * 8;
+    uint64_t Shift = Op->Header.ElementSize * Op->Index * 8;
    if (Op->Header.ElementSize == 8)
      SourceMask = ~0ULL;

@@ -860,7 +911,7 @@ DEF_OP(VExtractToGPR) {
  }
  else {
    uint64_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
-    uint64_t Shift = Op->Header.ElementSize * Op->Idx * 8;
+    uint64_t Shift = Op->Header.ElementSize * Op->Index * 8;
    if (Op->Header.ElementSize == 8)
      SourceMask = ~0ULL;

@@ -974,55 +1025,4 @@ DEF_OP(FCmp) {

 #undef DEF_OP

-void InterpreterOps::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) FEXCore::CPU::InterpreterOps::OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
-  REGISTER_OP(CONSTANT,          Constant);
-  REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
-  REGISTER_OP(INLINECONSTANT,    InlineConstant);
-  REGISTER_OP(INLINEENTRYPOINTOFFSET,  InlineEntrypointOffset);
-  REGISTER_OP(CYCLECOUNTER,      CycleCounter);
-  REGISTER_OP(ADD,               Add);
-  REGISTER_OP(SUB,               Sub);
-  REGISTER_OP(NEG,               Neg);
-  REGISTER_OP(MUL,               Mul);
-  REGISTER_OP(UMUL,              UMul);
-  REGISTER_OP(DIV,               Div);
-  REGISTER_OP(UDIV,              UDiv);
-  REGISTER_OP(REM,               Rem);
-  REGISTER_OP(UREM,              URem);
-  REGISTER_OP(MULH,              MulH);
-  REGISTER_OP(UMULH,             UMulH);
-  REGISTER_OP(OR,                Or);
-  REGISTER_OP(AND,               And);
-  REGISTER_OP(ANDN,              Andn);
-  REGISTER_OP(XOR,               Xor);
-  REGISTER_OP(LSHL,              Lshl);
-  REGISTER_OP(LSHR,              Lshr);
-  REGISTER_OP(ASHR,              Ashr);
-  REGISTER_OP(ROR,               Ror);
-  REGISTER_OP(EXTR,              Extr);
-  REGISTER_OP(LDIV,              LDiv);
-  REGISTER_OP(LUDIV,             LUDiv);
-  REGISTER_OP(LREM,              LRem);
-  REGISTER_OP(LUREM,             LURem);
-  REGISTER_OP(NOT,               Not);
-  REGISTER_OP(POPCOUNT,          Popcount);
-  REGISTER_OP(FINDLSB,           FindLSB);
-  REGISTER_OP(FINDMSB,           FindMSB);
-  REGISTER_OP(FINDTRAILINGZEROS, FindTrailingZeros);
-  REGISTER_OP(COUNTLEADINGZEROES, CountLeadingZeroes);
-  REGISTER_OP(REV,               Rev);
-  REGISTER_OP(BFI,               Bfi);
-  REGISTER_OP(BFE,               Bfe);
-  REGISTER_OP(SBFE,              Sbfe);
-  REGISTER_OP(SELECT,            Select);
-  REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
-  REGISTER_OP(FCMP,              FCmp);
-#undef REGISTER_OP
-}
-
-
-}
+} // namespace FEXCore::CPU
@@ -310,33 +310,32 @@ uint64_t AtomicCompareAndSwap(uint64_t expected, uint64_t desired, uint64_t *add

 #endif

-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(CASPair) {
  auto Op = IROp->C<IR::IROp_CASPair>();
-  uint8_t OpSize = IROp->Size;

  // Size is the size of each pair element
-  switch (OpSize) {
+  switch (IROp->ElementSize) {
    case 4: {
      GD = AtomicCompareAndSwap(
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]),
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]),
-        *GetSrc<uint64_t**>(Data->SSAData, Op->Header.Args[2])
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Expected),
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Desired),
+        *GetSrc<uint64_t**>(Data->SSAData, Op->Addr)
      );
      break;
    }
    case 8: {
-      std::atomic<__uint128_t> *MemData = *GetSrc<std::atomic<__uint128_t> **>(Data->SSAData, Op->Header.Args[2]);
+      std::atomic<__uint128_t> *MemData = *GetSrc<std::atomic<__uint128_t> **>(Data->SSAData, Op->Addr);

-      __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-      __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+      __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Expected);
+      __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Desired);

      __uint128_t Expected = Src1;
      bool Result = MemData->compare_exchange_strong(Expected, Src2);
      memcpy(GDP, Result ? &Src1 : &Expected, 16);
      break;
    }
-    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", IROp->ElementSize); break;
  }
 }

@@ -347,33 +346,33 @@ DEF_OP(CAS) {
  switch (OpSize) {
    case 1: {
      GD = AtomicCompareAndSwap(
-        *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]),
-        *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]),
-        *GetSrc<uint8_t**>(Data->SSAData, Op->Header.Args[2])
+        *GetSrc<uint8_t*>(Data->SSAData, Op->Expected),
+        *GetSrc<uint8_t*>(Data->SSAData, Op->Desired),
+        *GetSrc<uint8_t**>(Data->SSAData, Op->Addr)
      );
      break;
    }
    case 2: {
      GD = AtomicCompareAndSwap(
-        *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]),
-        *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]),
-        *GetSrc<uint16_t**>(Data->SSAData, Op->Header.Args[2])
+        *GetSrc<uint16_t*>(Data->SSAData, Op->Expected),
+        *GetSrc<uint16_t*>(Data->SSAData, Op->Desired),
+        *GetSrc<uint16_t**>(Data->SSAData, Op->Addr)
      );
      break;
    }
    case 4: {
      GD = AtomicCompareAndSwap(
-        *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]),
-        *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]),
-        *GetSrc<uint32_t**>(Data->SSAData, Op->Header.Args[2])
+        *GetSrc<uint32_t*>(Data->SSAData, Op->Expected),
+        *GetSrc<uint32_t*>(Data->SSAData, Op->Desired),
+        *GetSrc<uint32_t**>(Data->SSAData, Op->Addr)
      );
      break;
    }
    case 8: {
      GD = AtomicCompareAndSwap(
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]),
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]),
-        *GetSrc<uint64_t**>(Data->SSAData, Op->Header.Args[2])
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Expected),
+        *GetSrc<uint64_t*>(Data->SSAData, Op->Desired),
+        *GetSrc<uint64_t**>(Data->SSAData, Op->Addr)
      );
      break;
    }
@@ -385,26 +384,26 @@ DEF_OP(AtomicAdd) {
  auto Op = IROp->C<IR::IROp_AtomicAdd>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      *MemData += Src;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      *MemData += Src;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      *MemData += Src;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      *MemData += Src;
      break;
    }
@@ -416,26 +415,26 @@ DEF_OP(AtomicSub) {
  auto Op = IROp->C<IR::IROp_AtomicSub>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      *MemData -= Src;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      *MemData -= Src;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      *MemData -= Src;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      *MemData -= Src;
      break;
    }
@@ -447,26 +446,26 @@ DEF_OP(AtomicAnd) {
  auto Op = IROp->C<IR::IROp_AtomicAnd>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      *MemData &= Src;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      *MemData &= Src;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      *MemData &= Src;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      *MemData &= Src;
      break;
    }
@@ -478,26 +477,26 @@ DEF_OP(AtomicOr) {
  auto Op = IROp->C<IR::IROp_AtomicOr>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      *MemData |= Src;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      *MemData |= Src;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      *MemData |= Src;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      *MemData |= Src;
      break;
    }
@@ -509,26 +508,26 @@ DEF_OP(AtomicXor) {
  auto Op = IROp->C<IR::IROp_AtomicXor>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      *MemData ^= Src;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      *MemData ^= Src;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      *MemData ^= Src;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      *MemData ^= Src;
      break;
    }
@@ -540,29 +539,29 @@ DEF_OP(AtomicSwap) {
  auto Op = IROp->C<IR::IROp_AtomicSwap>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->exchange(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->exchange(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->exchange(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->exchange(Src);
      GD = Previous;
      break;
@@ -575,29 +574,29 @@ DEF_OP(AtomicFetchAdd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->fetch_add(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->fetch_add(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->fetch_add(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->fetch_add(Src);
      GD = Previous;
      break;
@@ -610,29 +609,29 @@ DEF_OP(AtomicFetchSub) {
  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->fetch_sub(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->fetch_sub(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->fetch_sub(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->fetch_sub(Src);
      GD = Previous;
      break;
@@ -645,29 +644,29 @@ DEF_OP(AtomicFetchAnd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->fetch_and(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->fetch_and(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->fetch_and(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->fetch_and(Src);
      GD = Previous;
      break;
@@ -680,29 +679,29 @@ DEF_OP(AtomicFetchOr) {
  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->fetch_or(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->fetch_or(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->fetch_or(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->fetch_or(Src);
      GD = Previous;
      break;
@@ -715,29 +714,29 @@ DEF_OP(AtomicFetchXor) {
  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
  switch (IROp->Size) {
    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
+      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
      uint8_t Previous = MemData->fetch_xor(Src);
      GD = Previous;
      break;
    }
    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
+      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
      uint16_t Previous = MemData->fetch_xor(Src);
      GD = Previous;
      break;
    }
    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
+      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
      uint32_t Previous = MemData->fetch_xor(Src);
      GD = Previous;
      break;
    }
    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
+      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
      uint64_t Previous = MemData->fetch_xor(Src);
      GD = Previous;
      break;
@@ -751,22 +750,22 @@ DEF_OP(AtomicFetchNeg) {
  switch (IROp->Size) {
    case 1: {
      using Type = uint8_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
      break;
    }
    case 2: {
      using Type = uint16_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
      break;
    }
    case 4: {
      using Type = uint32_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
      break;
    }
    case 8: {
      using Type = uint64_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Header.Args[0]));
+      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
      break;
    }
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
@@ -774,23 +773,5 @@ DEF_OP(AtomicFetchNeg) {
 }

 #undef DEF_OP
-void InterpreterOps::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(CASPAIR,        CASPair);
-  REGISTER_OP(CAS,            CAS);
-  REGISTER_OP(ATOMICADD,      AtomicAdd);
-  REGISTER_OP(ATOMICSUB,      AtomicSub);
-  REGISTER_OP(ATOMICAND,      AtomicAnd);
-  REGISTER_OP(ATOMICOR,       AtomicOr);
-  REGISTER_OP(ATOMICXOR,      AtomicXor);
-  REGISTER_OP(ATOMICSWAP,     AtomicSwap);
-  REGISTER_OP(ATOMICFETCHADD, AtomicFetchAdd);
-  REGISTER_OP(ATOMICFETCHSUB, AtomicFetchSub);
-  REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
-  REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
-  REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
-  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
-#undef REGISTER_OP
-}
-}

+} // namespace FEXCore::CPU
@@ -13,6 +13,7 @@ $end_info$
 #include <FEXCore/HLE/SyscallHandler.h>

 #include <cstdint>
+#include <unistd.h>

 namespace FEXCore::CPU {
 [[noreturn]]
@@ -23,7 +24,7 @@ static void SignalReturn(FEXCore::Core::InternalThreadState *Thread) {
  FEX_UNREACHABLE;
 }

-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(GuestCallDirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }
@@ -32,10 +33,6 @@ DEF_OP(GuestCallIndirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }

-DEF_OP(GuestReturn) {
-  LogMan::Msg::DFmt("Unimplemented");
-}
-
 DEF_OP(SignalReturn) {
  SignalReturn(Data->State);
 }
@@ -104,6 +101,34 @@ DEF_OP(Syscall) {
  GD = Res;
 }

+DEF_OP(InlineSyscall) {
+  auto Op = IROp->C<IR::IROp_InlineSyscall>();
+
+  FEXCore::HLE::SyscallArguments Args;
+  for (size_t j = 0; j < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++j) {
+    if (Op->Header.Args[j].IsInvalid()) break;
+    Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
+  }
+
+  // We don't want the errno handling but I also don't want to write inline ASM atm
+  uint64_t Res = syscall(
+    Op->HostSyscallNumber,
+    Args.Argument[0],
+    Args.Argument[1],
+    Args.Argument[2],
+    Args.Argument[3],
+    Args.Argument[4],
+    Args.Argument[5],
+    Args.Argument[6]
+  );
+
+  if (Res == -1) {
+    Res = -errno;
+  }
+
+  GD = Res;
+}
+
 DEF_OP(Thunk) {
  auto Op = IROp->C<IR::IROp_Thunk>();

@@ -137,21 +162,5 @@ DEF_OP(CPUID) {
 }

 #undef DEF_OP
-void InterpreterOps::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
-  REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
-  REGISTER_OP(GUESTRETURN,       GuestReturn);
-  REGISTER_OP(SIGNALRETURN,      SignalReturn);
-  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
-  REGISTER_OP(EXITFUNCTION,      ExitFunction);
-  REGISTER_OP(JUMP,              Jump);
-  REGISTER_OP(CONDJUMP,          CondJump);
-  REGISTER_OP(SYSCALL,           Syscall);
-  REGISTER_OP(THUNK,             Thunk);
-  REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(REMOVECODEENTRY,   RemoveCodeEntry);
-  REGISTER_OP(CPUID,             CPUID);
-#undef REGISTER_OP
-}
-}
+
+} // namespace FEXCore::CPU
@@ -11,7 +11,7 @@ $end_info$
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(VInsGPR) {
  auto Op = IROp->C<IR::IROp_VInsGPR>();
  uint8_t OpSize = IROp->Size;
@@ -19,7 +19,7 @@ DEF_OP(VInsGPR) {
  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);

-  uint64_t Offset = Op->Index * Op->Header.ElementSize * 8;
+  uint64_t Offset = Op->DestIdx * Op->Header.ElementSize * 8;
  __uint128_t Mask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
  if (Op->Header.ElementSize == 8) {
    Mask = ~0ULL;
@@ -220,18 +220,5 @@ DEF_OP(Vector_FToI) {
 }

 #undef DEF_OP
-void InterpreterOps::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(VINSGPR,         VInsGPR);
-  REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
-  REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
-  REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
-  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
-#undef REGISTER_OP
-}

-}
+} // namespace FEXCore::CPU
@@ -298,8 +298,65 @@ namespace AES {
  }
 }

+namespace CRC32 {
+  // CRC32 per byte lookup table.
+  constexpr std::array<uint32_t, 256> CRC32CTable = []() consteval {
+    std::array<uint32_t, 256> Table{};
+
+    // Clang 11.x doesn't support bitreverse as a consteval
+    // constexpr uint32_t Polynomial = 0x1EDC6F41;
+    constexpr uint32_t PolynomialRev = 0x82F63B78; //__builtin_bitreverse32(Polynomial);
+
+    for (size_t Char = 0; Char < std::size(Table); ++Char) {
+      uint32_t CurrentChar = Char;
+      for (size_t i = 0; i < 8; ++i) {
+        if (CurrentChar & 1) {
+          CurrentChar = (CurrentChar >> 1) ^ PolynomialRev;
+        }
+        else {
+          CurrentChar >>= 1;
+        }
+      }
+      Table[Char] = CurrentChar;
+    }
+
+    return Table;
+  }();
+
+  uint32_t crc32cb(uint32_t Accumulator, uint8_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ data] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32ch(uint32_t Accumulator, uint16_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 8) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32cw(uint32_t Accumulator, uint32_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+
+  uint32_t crc32cx(uint32_t Accumulator, uint64_t data) {
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 32) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 40) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 48) & 0xFF)] ^ Accumulator >> 8;
+    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 56) & 0xFF)] ^ Accumulator >> 8;
+    return Accumulator;
+  }
+}
+
 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)

 DEF_OP(AESImc) {
  auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -429,15 +486,33 @@ DEF_OP(AESKeyGenAssist) {
  memcpy(GDP, &Tmp, sizeof(Tmp));
 }

+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  uint32_t Src1 = *GetSrc<uint32_t*>(Data->SSAData, Op->Src1);
+  uint8_t *Src2 = GetSrc<uint8_t*>(Data->SSAData, Op->Src2);
+  uint32_t Tmp{};
+
+  switch (Op->SrcSize) {
+    case 1:
+      Tmp = CRC32::crc32cb(Src1, *(uint8_t*)Src2);
+      break;
+    case 2:
+      Tmp = CRC32::crc32ch(Src1, *(uint16_t*)Src2);
+      break;
+    case 4:
+      Tmp = CRC32::crc32cw(Src1, *(uint32_t*)Src2);
+      break;
+    case 8:
+      Tmp = CRC32::crc32cx(Src1, *(uint64_t*)Src2);
+      break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown CRC32C size: {}", Op->SrcSize);
+      break;
+
+  }
+  memcpy(GDP, &Tmp, sizeof(Tmp));
+}
+
 #undef DEF_OP
-void InterpreterOps::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(VAESIMC,     AESImc);
-  REGISTER_OP(VAESENC,     AESEnc);
-  REGISTER_OP(VAESENCLAST, AESEncLast);
-  REGISTER_OP(VAESDEC,     AESDec);
-  REGISTER_OP(VAESDECLAST, AESDecLast);
-  REGISTER_OP(VAESKEYGENASSIST, AESKeyGenAssist);
-#undef REGISTER_OP
-}
-}
+
+} // namespace FEXCore::CPU
@@ -13,7 +13,7 @@ $end_info$
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(F80LOADFCW) {
  FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle(*GetSrc<uint16_t*>(Data->SSAData, IROp->Args[0]));
 }
@@ -158,7 +158,7 @@ DEF_OP(F80CVTINT) {
 DEF_OP(F80CVTTO) {
  auto Op = IROp->C<IR::IROp_F80CVTTo>();

-  switch (Op->Size) {
+  switch (Op->SrcSize) {
    case 4: {
      float Src = *GetSrc<float *>(Data->SSAData, Op->Header.Args[0]);
      X80SoftFloat Tmp = Src;
@@ -171,14 +171,14 @@ DEF_OP(F80CVTTO) {
      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
      break;
    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->Size);
+    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->SrcSize);
  }
 }

 DEF_OP(F80CVTTOINT) {
  auto Op = IROp->C<IR::IROp_F80CVTToInt>();

-  switch (Op->Size) {
+  switch (Op->SrcSize) {
    case 2: {
      int16_t Src = *GetSrc<int16_t*>(Data->SSAData, Op->Header.Args[0]);
      X80SoftFloat Tmp = Src;
@@ -191,7 +191,7 @@ DEF_OP(F80CVTTOINT) {
      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
      break;
    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->Size);
+    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->SrcSize);
  }
 }

@@ -323,7 +323,7 @@ DEF_OP(F80BCDLOAD) {

 DEF_OP(F80BCDSTORE) {
  auto Op = IROp->C<IR::IROp_F80BCDStore>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]));
  bool Negative = Src1.Sign;

  // Clear the Sign bit
@@ -357,33 +357,5 @@ DEF_OP(F80BCDSTORE) {
 }

 #undef DEF_OP
-void InterpreterOps::RegisterF80Handlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(F80LOADFCW, F80LOADFCW);
-  REGISTER_OP(F80ADD, F80ADD);
-  REGISTER_OP(F80SUB, F80SUB);
-  REGISTER_OP(F80MUL, F80MUL);
-  REGISTER_OP(F80DIV, F80DIV);
-  REGISTER_OP(F80FYL2X, F80FYL2X);
-  REGISTER_OP(F80ATAN, F80ATAN);
-  REGISTER_OP(F80FPREM1, F80FPREM1);
-  REGISTER_OP(F80FPREM, F80FPREM);
-  REGISTER_OP(F80SCALE, F80SCALE);
-  REGISTER_OP(F80CVT, F80CVT);
-  REGISTER_OP(F80CVTINT, F80CVTINT);
-  REGISTER_OP(F80CVTTO, F80CVTTO);
-  REGISTER_OP(F80CVTTOINT, F80CVTTOINT);
-  REGISTER_OP(F80ROUND, F80ROUND);
-  REGISTER_OP(F80F2XM1, F80F2XM1);
-  REGISTER_OP(F80TAN, F80TAN);
-  REGISTER_OP(F80SQRT, F80SQRT);
-  REGISTER_OP(F80SIN, F80SIN);
-  REGISTER_OP(F80COS, F80COS);
-  REGISTER_OP(F80XTRACT_EXP, F80XTRACT_EXP);
-  REGISTER_OP(F80XTRACT_SIG, F80XTRACT_SIG);
-  REGISTER_OP(F80CMP, F80CMP);
-  REGISTER_OP(F80BCDLOAD, F80BCDLOAD);
-  REGISTER_OP(F80BCDSTORE, F80BCDSTORE);
-#undef REGISTER_OP
-}
-}
+
+} // namespace FEXCore::CPU
@@ -227,6 +227,8 @@ struct OpHandlers<IR::OP_F80BCDSTORE> {
  static X80SoftFloat handle(X80SoftFloat Src1) {
    bool Negative = Src1.Sign;

+    Src1 = X80SoftFloat::FRNDINT(Src1);
+
    // Clear the Sign bit
    Src1.Sign = 0;

@@ -11,17 +11,11 @@ $end_info$
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
  auto Op = IROp->C<IR::IROp_GetHostFlag>();
  GD = (*GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]) >> Op->Flag) & 1;
 }
-
 #undef DEF_OP
-void InterpreterOps::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(GETHOSTFLAG, GetHostFlag);
-#undef REGISTER_OP
-}
-}

+} // namespace FEXCore::CPU
@@ -37,7 +37,9 @@ public:

  void CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);

-  static void InitializeInterpreterOpHandlers();
+  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);
+
+  bool NeedsRetainedIRCopy() const override { return true; }

 private:
  FEXCore::Context::Context *CTX;
@@ -11,7 +11,6 @@
 #include <FEXCore/Utils/LogManager.h>

 #include <memory>
-#include <bits/types/stack_t.h>
 #include <signal.h>
 #include <stdint.h>
 #include <unordered_map>
@@ -35,24 +34,6 @@ static void InterpreterExecution(FEXCore::Core::CpuStateFrame *Frame) {
  InterpreterOps::InterpretIR(Thread, Thread->CurrentFrame->State.rip, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
 }

-void InitializeInterpreterOpHandlers() {
-  for (uint32_t i = 0; i <= FEXCore::IR::IROps::OP_LAST; ++i) {
-    InterpreterOps::OpHandlers[i] = &InterpreterOps::Op_Unhandled;
-  }
-
-  InterpreterOps::RegisterALUHandlers();
-  InterpreterOps::RegisterAtomicHandlers();
-  InterpreterOps::RegisterBranchHandlers();
-  InterpreterOps::RegisterConversionHandlers();
-  InterpreterOps::RegisterFlagHandlers();
-  InterpreterOps::RegisterMemoryHandlers();
-  InterpreterOps::RegisterMiscHandlers();
-  InterpreterOps::RegisterMoveHandlers();
-  InterpreterOps::RegisterVectorHandlers();
-  InterpreterOps::RegisterEncryptionHandlers();
-  InterpreterOps::RegisterF80Handlers();
-}
-
 InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread)
  : CTX {ctx}
  , State {Thread} {
@@ -60,26 +41,28 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
  if (!CompileThread &&
      CTX->Config.Core == FEXCore::Config::CONFIG_INTERPRETER) {
    CreateAsmDispatch(ctx, Thread);
-    CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
-    }, true);
+  }
+}
+
+void InterpreterCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
+  CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
+  }, true);

 #ifdef _M_ARM_64
-    CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(true, Signal, info, ucontext);
-    }, true);
+  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(true, Signal, info, ucontext);
+  }, true);
 #endif

-    auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
-      InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-    };
+  auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
+    InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+  };

-    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
-      CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
-    }
+  for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
+    CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
  }
 }

@@ -91,4 +74,8 @@ std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx
  return std::make_unique<InterpreterCore>(ctx, Thread, CompileThread);
 }

+void InitializeInterpreterSignalHandlers(FEXCore::Context::Context *CTX) {
+  InterpreterCore::InitializeSignalHandlers(CTX);
+}
+
 }
@@ -13,10 +13,10 @@ namespace FEXCore::Core {
 namespace FEXCore::CPU {
 class CPUBackend;

-void InitializeInterpreterOpHandlers();
-
 [[nodiscard]] std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx,
                                                                FEXCore::Core::InternalThreadState *Thread,
                                                                bool CompileThread);

+void InitializeInterpreterSignalHandlers(FEXCore::Context::Context *CTX);
+
 } // namespace FEXCore::CPU
@@ -161,19 +161,19 @@

 template<typename Res>
 Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.ID()];
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.ID().Value];
  return reinterpret_cast<Res>(DstPtr);
 }

 template<typename Res>
-Res GetDest(void* SSAData, uint32_t Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op];
+Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.Value];
  return reinterpret_cast<Res>(DstPtr);
 }


 template<typename Res>
 Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Src.ID()];
+  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Src.ID().Value];
  return reinterpret_cast<Res>(DstPtr);
 }
@@ -0,0 +1,272 @@
+#include "FEXCore/Core/CoreState.h"
+#include "Interface/Core/Interpreter/InterpreterOps.h"
+#include "Interface/Core/Interpreter/F80Ops.h"
+
+#include <cstddef>
+#include <cstdint>
+
+namespace FEXCore::CPU {
+
+template<typename R, typename... Args>
+static FallbackInfo GetFallbackInfo(R(*fn)(Args...), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_UNKNOWN, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_F32, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_F64, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_I16, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(void(*fn)(uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_VOID_U16, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_I32, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(float(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F32_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(double(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F64_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int16_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I16_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int32_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I32_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(int64_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I64_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(uint64_t(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I64_F80_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_F80, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_F80_F80_F80, (void*)fn, HandlerIndex};
+}
+
+void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
+  Info[Core::OPINDEX_F80LOADFCW] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW).fn);
+  Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4).fn);
+  Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8).fn);
+  Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4).fn);
+  Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8).fn);
+  Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2).fn);
+  Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4).fn);
+  Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8).fn);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2).fn);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4).fn);
+  Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8).fn);
+  Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>, Core::OPINDEX_F80CMP_0).fn);
+  Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>, Core::OPINDEX_F80CMP_1).fn);
+  Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>, Core::OPINDEX_F80CMP_2).fn);
+  Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>, Core::OPINDEX_F80CMP_3).fn);
+  Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>, Core::OPINDEX_F80CMP_4).fn);
+  Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>, Core::OPINDEX_F80CMP_5).fn);
+  Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>, Core::OPINDEX_F80CMP_6).fn);
+  Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>, Core::OPINDEX_F80CMP_7).fn);
+  Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2).fn);
+  Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4).fn);
+
+  // Unary
+  Info[Core::OPINDEX_F80ROUND] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle, Core::OPINDEX_F80ROUND).fn);
+  Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle, Core::OPINDEX_F80F2XM1).fn);
+  Info[Core::OPINDEX_F80TAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle, Core::OPINDEX_F80TAN).fn);
+  Info[Core::OPINDEX_F80SQRT] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle, Core::OPINDEX_F80SQRT).fn);
+  Info[Core::OPINDEX_F80SIN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle, Core::OPINDEX_F80SIN).fn);
+  Info[Core::OPINDEX_F80COS] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle, Core::OPINDEX_F80COS).fn);
+  Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle, Core::OPINDEX_F80XTRACT_EXP).fn);
+  Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle, Core::OPINDEX_F80XTRACT_SIG).fn);
+  Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle, Core::OPINDEX_F80BCDSTORE).fn);
+  Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle, Core::OPINDEX_F80BCDLOAD).fn);
+
+  // Binary
+  Info[Core::OPINDEX_F80ADD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle, Core::OPINDEX_F80ADD).fn);
+  Info[Core::OPINDEX_F80SUB] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle, Core::OPINDEX_F80SUB).fn);
+  Info[Core::OPINDEX_F80MUL] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle, Core::OPINDEX_F80MUL).fn);
+  Info[Core::OPINDEX_F80DIV] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle, Core::OPINDEX_F80DIV).fn);
+  Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle, Core::OPINDEX_F80FYL2X).fn);
+  Info[Core::OPINDEX_F80ATAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle, Core::OPINDEX_F80ATAN).fn);
+  Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle, Core::OPINDEX_F80FPREM1).fn);
+  Info[Core::OPINDEX_F80FPREM] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle, Core::OPINDEX_F80FPREM).fn);
+  Info[Core::OPINDEX_F80SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle, Core::OPINDEX_F80SCALE).fn);
+}
+
+bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info) {
+  uint8_t OpSize = IROp->Size;
+  switch(IROp->Op) {
+    case IR::OP_F80LOADFCW: {
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW);
+      return true;
+    }
+
+    case IR::OP_F80CVTTO: {
+      auto Op = IROp->C<IR::IROp_F80CVTTo>();
+
+      switch (Op->SrcSize) {
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4);
+          return true;
+        }
+        case 8: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8);
+          return true;
+        }
+      default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CVT: {
+      switch (OpSize) {
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4);
+          return true;
+        }
+        case 8: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8);
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CVTINT: {
+      auto Op = IROp->C<IR::IROp_F80CVTInt>();
+
+      switch (OpSize) {
+        case 2: {
+          if (Op->Truncate) {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2);
+          }
+          else {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2);
+          }
+          return true;
+        }
+        case 4: {
+          if (Op->Truncate) {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4);
+          }
+          else {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4);
+          }
+          return true;
+        }
+        case 8: {
+          if (Op->Truncate) {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8);
+          }
+          else {
+            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8);
+          }
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+    case IR::OP_F80CMP: {
+      auto Op = IROp->C<IR::IROp_F80Cmp>();
+
+      static constexpr std::array handlers{
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>,
+        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
+      };
+
+      *Info = GetFallbackInfo(handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags));
+      return true;
+    }
+
+    case IR::OP_F80CVTTOINT: {
+      auto Op = IROp->C<IR::IROp_F80CVTToInt>();
+
+      switch (Op->SrcSize) {
+        case 2: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2);
+          return true;
+        }
+        case 4: {
+          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4);
+          return true;
+        }
+        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
+      }
+      break;
+    }
+
+#define COMMON_X87_OP(OP) \
+    case IR::OP_F80##OP: { \
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP); \
+      return true; \
+    }
+
+    // Unary
+    COMMON_X87_OP(ROUND)
+    COMMON_X87_OP(F2XM1)
+    COMMON_X87_OP(TAN)
+    COMMON_X87_OP(SQRT)
+    COMMON_X87_OP(SIN)
+    COMMON_X87_OP(COS)
+    COMMON_X87_OP(XTRACT_EXP)
+    COMMON_X87_OP(XTRACT_SIG)
+    COMMON_X87_OP(BCDSTORE)
+    COMMON_X87_OP(BCDLOAD)
+
+    // Binary
+    COMMON_X87_OP(ADD)
+    COMMON_X87_OP(SUB)
+    COMMON_X87_OP(MUL)
+    COMMON_X87_OP(DIV)
+    COMMON_X87_OP(FYL2X)
+    COMMON_X87_OP(ATAN)
+    COMMON_X87_OP(FPREM1)
+    COMMON_X87_OP(FPREM)
+    COMMON_X87_OP(SCALE)
+
+    default:
+      break;
+  }
+
+  return false;
+}
+
+
+}
@@ -21,234 +21,309 @@

 #include <alloca.h>
 #include <algorithm>
+#include <array>
 #include <atomic>
 #include <bit>
 #include <cmath>
+#include <cstddef>
 #include <cstdint>
+#include <cstdlib>
+#include <cstring>
+#include <ctime>
 #include <limits>
 #include <memory>
-#include <stddef.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>

 namespace FEXCore::CPU {
-std::array<InterpreterOps::OpHandler, FEXCore::IR::IROps::OP_LAST + 1> InterpreterOps::OpHandlers;

-void InterpreterOps::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node) {
+using OpHandler = void (*)(IR::IROp_Header *IROp, InterpreterOps::IROpData *Data, IR::NodeID Node);
+using OpHandlerArray = std::array<OpHandler, IR::IROps::OP_LAST + 1>;
+
+constexpr OpHandlerArray InterpreterOpHandlers = [] {
+  OpHandlerArray Handlers{};
+  for (auto& Entry : Handlers) {
+    Entry = &InterpreterOps::Op_Unhandled;
+  }
+
+  #define REGISTER_OP(op, x) Handlers[IR::IROps::OP_##op] = &InterpreterOps::Op_##x
+
+  // ALU ops
+  REGISTER_OP(TRUNCELEMENTPAIR,       TruncElementPair);
+  REGISTER_OP(CONSTANT,               Constant);
+  REGISTER_OP(ENTRYPOINTOFFSET,       EntrypointOffset);
+  REGISTER_OP(INLINECONSTANT,         InlineConstant);
+  REGISTER_OP(INLINEENTRYPOINTOFFSET, InlineEntrypointOffset);
+  REGISTER_OP(CYCLECOUNTER,           CycleCounter);
+  REGISTER_OP(ADD,                    Add);
+  REGISTER_OP(SUB,                    Sub);
+  REGISTER_OP(NEG,                    Neg);
+  REGISTER_OP(MUL,                    Mul);
+  REGISTER_OP(UMUL,                   UMul);
+  REGISTER_OP(DIV,                    Div);
+  REGISTER_OP(UDIV,                   UDiv);
+  REGISTER_OP(REM,                    Rem);
+  REGISTER_OP(UREM,                   URem);
+  REGISTER_OP(MULH,                   MulH);
+  REGISTER_OP(UMULH,                  UMulH);
+  REGISTER_OP(OR,                     Or);
+  REGISTER_OP(AND,                    And);
+  REGISTER_OP(ANDN,                   Andn);
+  REGISTER_OP(XOR,                    Xor);
+  REGISTER_OP(LSHL,                   Lshl);
+  REGISTER_OP(LSHR,                   Lshr);
+  REGISTER_OP(ASHR,                   Ashr);
+  REGISTER_OP(ROR,                    Ror);
+  REGISTER_OP(EXTR,                   Extr);
+  REGISTER_OP(PDEP,                   PDep);
+  REGISTER_OP(PEXT,                   PExt);
+  REGISTER_OP(LDIV,                   LDiv);
+  REGISTER_OP(LUDIV,                  LUDiv);
+  REGISTER_OP(LREM,                   LRem);
+  REGISTER_OP(LUREM,                  LURem);
+  REGISTER_OP(NOT,                    Not);
+  REGISTER_OP(POPCOUNT,               Popcount);
+  REGISTER_OP(FINDLSB,                FindLSB);
+  REGISTER_OP(FINDMSB,                FindMSB);
+  REGISTER_OP(FINDTRAILINGZEROS,      FindTrailingZeros);
+  REGISTER_OP(COUNTLEADINGZEROES,     CountLeadingZeroes);
+  REGISTER_OP(REV,                    Rev);
+  REGISTER_OP(BFI,                    Bfi);
+  REGISTER_OP(BFE,                    Bfe);
+  REGISTER_OP(SBFE,                   Sbfe);
+  REGISTER_OP(SELECT,                 Select);
+  REGISTER_OP(VEXTRACTTOGPR,          VExtractToGPR);
+  REGISTER_OP(FLOAT_TOGPR_ZS,         Float_ToGPR_ZS);
+  REGISTER_OP(FLOAT_TOGPR_S,          Float_ToGPR_S);
+  REGISTER_OP(FCMP,                   FCmp);
+
+  // Atomic ops
+  REGISTER_OP(CASPAIR,                CASPair);
+  REGISTER_OP(CAS,                    CAS);
+  REGISTER_OP(ATOMICADD,              AtomicAdd);
+  REGISTER_OP(ATOMICSUB,              AtomicSub);
+  REGISTER_OP(ATOMICAND,              AtomicAnd);
+  REGISTER_OP(ATOMICOR,               AtomicOr);
+  REGISTER_OP(ATOMICXOR,              AtomicXor);
+  REGISTER_OP(ATOMICSWAP,             AtomicSwap);
+  REGISTER_OP(ATOMICFETCHADD,         AtomicFetchAdd);
+  REGISTER_OP(ATOMICFETCHSUB,         AtomicFetchSub);
+  REGISTER_OP(ATOMICFETCHAND,         AtomicFetchAnd);
+  REGISTER_OP(ATOMICFETCHOR,          AtomicFetchOr);
+  REGISTER_OP(ATOMICFETCHXOR,         AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG,         AtomicFetchNeg);
+
+  // Branch ops
+  REGISTER_OP(GUESTCALLDIRECT,        GuestCallDirect);
+  REGISTER_OP(GUESTCALLINDIRECT,      GuestCallIndirect);
+  REGISTER_OP(SIGNALRETURN,           SignalReturn);
+  REGISTER_OP(CALLBACKRETURN,         CallbackReturn);
+  REGISTER_OP(EXITFUNCTION,           ExitFunction);
+  REGISTER_OP(JUMP,                   Jump);
+  REGISTER_OP(CONDJUMP,               CondJump);
+  REGISTER_OP(SYSCALL,                Syscall);
+  REGISTER_OP(INLINESYSCALL,          InlineSyscall);
+  REGISTER_OP(THUNK,                  Thunk);
+  REGISTER_OP(VALIDATECODE,           ValidateCode);
+  REGISTER_OP(REMOVECODEENTRY,        RemoveCodeEntry);
+  REGISTER_OP(CPUID,                  CPUID);
+
+  // Conversion ops
+  REGISTER_OP(VINSGPR,                VInsGPR);
+  REGISTER_OP(VCASTFROMGPR,           VCastFromGPR);
+  REGISTER_OP(FLOAT_FROMGPR_S,        Float_FromGPR_S);
+  REGISTER_OP(FLOAT_FTOF,             Float_FToF);
+  REGISTER_OP(VECTOR_STOF,            Vector_SToF);
+  REGISTER_OP(VECTOR_FTOZS,           Vector_FToZS);
+  REGISTER_OP(VECTOR_FTOS,            Vector_FToS);
+  REGISTER_OP(VECTOR_FTOF,            Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,            Vector_FToI);
+
+  // Flag ops
+  REGISTER_OP(GETHOSTFLAG,            GetHostFlag);
+
+  // Memory ops
+  REGISTER_OP(LOADCONTEXT,            LoadContext);
+  REGISTER_OP(STORECONTEXT,           StoreContext);
+  REGISTER_OP(LOADREGISTER,           LoadRegister);
+  REGISTER_OP(STOREREGISTER,          StoreRegister);
+  REGISTER_OP(LOADCONTEXTINDEXED,     LoadContextIndexed);
+  REGISTER_OP(STORECONTEXTINDEXED,    StoreContextIndexed);
+  REGISTER_OP(SPILLREGISTER,          SpillRegister);
+  REGISTER_OP(FILLREGISTER,           FillRegister);
+  REGISTER_OP(LOADFLAG,               LoadFlag);
+  REGISTER_OP(STOREFLAG,              StoreFlag);
+  REGISTER_OP(LOADMEM,                LoadMem);
+  REGISTER_OP(STOREMEM,               StoreMem);
+  REGISTER_OP(LOADMEMTSO,             LoadMem);
+  REGISTER_OP(STOREMEMTSO,            StoreMem);
+  REGISTER_OP(VLOADMEMELEMENT,        VLoadMemElement);
+  REGISTER_OP(VSTOREMEMELEMENT,       VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,         CacheLineClear);
+  REGISTER_OP(CACHELINEZERO,          CacheLineZero);
+
+  // Misc ops
+  REGISTER_OP(DUMMY,                  NoOp);
+  REGISTER_OP(IRHEADER,               NoOp);
+  REGISTER_OP(CODEBLOCK,              NoOp);
+  REGISTER_OP(BEGINBLOCK,             NoOp);
+  REGISTER_OP(ENDBLOCK,               NoOp);
+  REGISTER_OP(FENCE,                  Fence);
+  REGISTER_OP(BREAK,                  Break);
+  REGISTER_OP(PHI,                    NoOp);
+  REGISTER_OP(PHIVALUE,               NoOp);
+  REGISTER_OP(PRINT,                  Print);
+  REGISTER_OP(GETROUNDINGMODE,        GetRoundingMode);
+  REGISTER_OP(SETROUNDINGMODE,        SetRoundingMode);
+  REGISTER_OP(INVALIDATEFLAGS,        NoOp);
+  REGISTER_OP(PROCESSORID,            ProcessorID);
+  REGISTER_OP(RDRAND,                 RDRAND);
+
+  // Move ops
+  REGISTER_OP(EXTRACTELEMENTPAIR,     ExtractElementPair);
+  REGISTER_OP(CREATEELEMENTPAIR,      CreateElementPair);
+  REGISTER_OP(MOV,                    Mov);
+
+  // Vector ops
+  REGISTER_OP(VECTORZERO,             VectorZero);
+  REGISTER_OP(VECTORIMM,              VectorImm);
+  REGISTER_OP(SPLATVECTOR2,           SplatVector);
+  REGISTER_OP(SPLATVECTOR4,           SplatVector);
+  REGISTER_OP(VMOV,                   VMov);
+  REGISTER_OP(VAND,                   VAnd);
+  REGISTER_OP(VBIC,                   VBic);
+  REGISTER_OP(VOR,                    VOr);
+  REGISTER_OP(VXOR,                   VXor);
+  REGISTER_OP(VADD,                   VAdd);
+  REGISTER_OP(VSUB,                   VSub);
+  REGISTER_OP(VUQADD,                 VUQAdd);
+  REGISTER_OP(VUQSUB,                 VUQSub);
+  REGISTER_OP(VSQADD,                 VSQAdd);
+  REGISTER_OP(VSQSUB,                 VSQSub);
+  REGISTER_OP(VADDP,                  VAddP);
+  REGISTER_OP(VADDV,                  VAddV);
+  REGISTER_OP(VUMINV,                 VUMinV);
+  REGISTER_OP(VURAVG,                 VURAvg);
+  REGISTER_OP(VABS,                   VAbs);
+  REGISTER_OP(VPOPCOUNT,              VPopcount);
+  REGISTER_OP(VFADD,                  VFAdd);
+  REGISTER_OP(VFADDP,                 VFAddP);
+  REGISTER_OP(VFSUB,                  VFSub);
+  REGISTER_OP(VFMUL,                  VFMul);
+  REGISTER_OP(VFDIV,                  VFDiv);
+  REGISTER_OP(VFMIN,                  VFMin);
+  REGISTER_OP(VFMAX,                  VFMax);
+  REGISTER_OP(VFRECP,                 VFRecp);
+  REGISTER_OP(VFSQRT,                 VFSqrt);
+  REGISTER_OP(VFRSQRT,                VFRSqrt);
+  REGISTER_OP(VNEG,                   VNeg);
+  REGISTER_OP(VFNEG,                  VFNeg);
+  REGISTER_OP(VNOT,                   VNot);
+  REGISTER_OP(VUMIN,                  VUMin);
+  REGISTER_OP(VSMIN,                  VSMin);
+  REGISTER_OP(VUMAX,                  VUMax);
+  REGISTER_OP(VSMAX,                  VSMax);
+  REGISTER_OP(VZIP,                   VZip);
+  REGISTER_OP(VZIP2,                  VZip);
+  REGISTER_OP(VUNZIP,                 VUnZip);
+  REGISTER_OP(VUNZIP2,                VUnZip);
+  REGISTER_OP(VBSL,                   VBSL);
+  REGISTER_OP(VCMPEQ,                 VCMPEQ);
+  REGISTER_OP(VCMPEQZ,                VCMPEQZ);
+  REGISTER_OP(VCMPGT,                 VCMPGT);
+  REGISTER_OP(VCMPGTZ,                VCMPGTZ);
+  REGISTER_OP(VCMPLTZ,                VCMPLTZ);
+  REGISTER_OP(VFCMPEQ,                VFCMPEQ);
+  REGISTER_OP(VFCMPNEQ,               VFCMPNEQ);
+  REGISTER_OP(VFCMPLT,                VFCMPLT);
+  REGISTER_OP(VFCMPGT,                VFCMPGT);
+  REGISTER_OP(VFCMPLE,                VFCMPLE);
+  REGISTER_OP(VFCMPORD,               VFCMPORD);
+  REGISTER_OP(VFCMPUNO,               VFCMPUNO);
+  REGISTER_OP(VUSHL,                  VUShl);
+  REGISTER_OP(VUSHR,                  VUShr);
+  REGISTER_OP(VSSHR,                  VSShr);
+  REGISTER_OP(VUSHLS,                 VUShlS);
+  REGISTER_OP(VUSHRS,                 VUShrS);
+  REGISTER_OP(VSSHRS,                 VSShrS);
+  REGISTER_OP(VINSELEMENT,            VInsElement);
+  REGISTER_OP(VINSSCALARELEMENT,      VInsScalarElement);
+  REGISTER_OP(VEXTRACTELEMENT,        VExtractElement);
+  REGISTER_OP(VDUPELEMENT,            VDupElement);
+  REGISTER_OP(VEXTR,                  VExtr);
+  REGISTER_OP(VSLI,                   VSLI);
+  REGISTER_OP(VSRI,                   VSRI);
+  REGISTER_OP(VUSHRI,                 VUShrI);
+  REGISTER_OP(VSSHRI,                 VSShrI);
+  REGISTER_OP(VSHLI,                  VShlI);
+  REGISTER_OP(VUSHRNI,                VUShrNI);
+  REGISTER_OP(VUSHRNI2,               VUShrNI2);
+  REGISTER_OP(VBITCAST,               VBitcast);
+  REGISTER_OP(VSXTL,                  VSXTL);
+  REGISTER_OP(VSXTL2,                 VSXTL2);
+  REGISTER_OP(VUXTL,                  VUXTL);
+  REGISTER_OP(VUXTL2,                 VUXTL2);
+  REGISTER_OP(VSQXTN,                 VSQXTN);
+  REGISTER_OP(VSQXTN2,                VSQXTN2);
+  REGISTER_OP(VSQXTUN,                VSQXTUN);
+  REGISTER_OP(VSQXTUN2,               VSQXTUN2);
+  REGISTER_OP(VUMUL,                  VUMul);
+  REGISTER_OP(VSMUL,                  VSMul);
+  REGISTER_OP(VUMULL,                 VUMull);
+  REGISTER_OP(VSMULL,                 VSMull);
+  REGISTER_OP(VUMULL2,                VUMull2);
+  REGISTER_OP(VSMULL2,                VSMull2);
+  REGISTER_OP(VUABDL,                 VUABDL);
+  REGISTER_OP(VTBL1,                  VTBL1);
+  REGISTER_OP(VREV64,                 VRev64);
+
+  // Encryption ops
+  REGISTER_OP(VAESIMC,                AESImc);
+  REGISTER_OP(VAESENC,                AESEnc);
+  REGISTER_OP(VAESENCLAST,            AESEncLast);
+  REGISTER_OP(VAESDEC,                AESDec);
+  REGISTER_OP(VAESDECLAST,            AESDecLast);
+  REGISTER_OP(VAESKEYGENASSIST,       AESKeyGenAssist);
+  REGISTER_OP(CRC32,                  CRC32);
+
+  // F80 ops
+  REGISTER_OP(F80LOADFCW,             F80LOADFCW);
+  REGISTER_OP(F80ADD,                 F80ADD);
+  REGISTER_OP(F80SUB,                 F80SUB);
+  REGISTER_OP(F80MUL,                 F80MUL);
+  REGISTER_OP(F80DIV,                 F80DIV);
+  REGISTER_OP(F80FYL2X,               F80FYL2X);
+  REGISTER_OP(F80ATAN,                F80ATAN);
+  REGISTER_OP(F80FPREM1,              F80FPREM1);
+  REGISTER_OP(F80FPREM,               F80FPREM);
+  REGISTER_OP(F80SCALE,               F80SCALE);
+  REGISTER_OP(F80CVT,                 F80CVT);
+  REGISTER_OP(F80CVTINT,              F80CVTINT);
+  REGISTER_OP(F80CVTTO,               F80CVTTO);
+  REGISTER_OP(F80CVTTOINT,            F80CVTTOINT);
+  REGISTER_OP(F80ROUND,               F80ROUND);
+  REGISTER_OP(F80F2XM1,               F80F2XM1);
+  REGISTER_OP(F80TAN,                 F80TAN);
+  REGISTER_OP(F80SQRT,                F80SQRT);
+  REGISTER_OP(F80SIN,                 F80SIN);
+  REGISTER_OP(F80COS,                 F80COS);
+  REGISTER_OP(F80XTRACT_EXP,          F80XTRACT_EXP);
+  REGISTER_OP(F80XTRACT_SIG,          F80XTRACT_SIG);
+  REGISTER_OP(F80CMP,                 F80CMP);
+  REGISTER_OP(F80BCDLOAD,             F80BCDLOAD);
+  REGISTER_OP(F80BCDSTORE,            F80BCDSTORE);
+
+  return Handlers;
+}();
+
+void InterpreterOps::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node) {
  LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
 }

-void InterpreterOps::Op_NoOp(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node) {
-}
-
-template<typename R, typename... Args>
-FallbackInfo GetFallbackInfo(R(*fn)(Args...)) {
-  return {FABI_UNKNOWN, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(float)) {
-  return {FABI_F80_F32, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double)) {
-  return {FABI_F80_F64, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int16_t)) {
-  return {FABI_F80_I16, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(void(*fn)(uint16_t)) {
-  return {FABI_VOID_U16, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int32_t)) {
-  return {FABI_F80_I32, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(float(*fn)(X80SoftFloat)) {
-  return {FABI_F32_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(double(*fn)(X80SoftFloat)) {
-  return {FABI_F64_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int16_t(*fn)(X80SoftFloat)) {
-  return {FABI_I16_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int32_t(*fn)(X80SoftFloat)) {
-  return {FABI_I32_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int64_t(*fn)(X80SoftFloat)) {
-  return {FABI_I64_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint64_t(*fn)(X80SoftFloat, X80SoftFloat)) {
-  return {FABI_I64_F80_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat)) {
-  return {FABI_F80_F80, (void*)fn};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat)) {
-  return {FABI_F80_F80_F80, (void*)fn};
-}
-
-bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info) {
-  uint8_t OpSize = IROp->Size;
-  switch(IROp->Op) {
-    case IR::OP_F80LOADFCW: {
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle);
-      return true;
-    }
-
-    case IR::OP_F80CVTTO: {
-      auto Op = IROp->C<IR::IROp_F80CVTTo>();
-
-      switch (Op->Size) {
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4);
-          return true;
-        }
-        case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8);
-          return true;
-        }
-      default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CVT: {
-      switch (OpSize) {
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4);
-          return true;
-        }
-        case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8);
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CVTINT: {
-      auto Op = IROp->C<IR::IROp_F80CVTInt>();
-
-      switch (OpSize) {
-        case 2: {
-          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2);
-          return true;
-        }
-        case 4: {
-          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4);
-          return true;
-        }
-        case 8: {
-          *Info = GetFallbackInfo(Op->Truncate ? &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t : &FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8);
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CMP: {
-      auto Op = IROp->C<IR::IROp_F80Cmp>();
-
-      decltype(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>) handlers[] = {
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7> };
-
-      *Info = GetFallbackInfo(handlers[Op->Flags]);
-      return true;
-    }
-
-    case IR::OP_F80CVTTOINT: {
-      auto Op = IROp->C<IR::IROp_F80CVTToInt>();
-
-      switch (Op->Size) {
-        case 2: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2);
-          return true;
-        }
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4);
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-
-#define COMMON_X87_OP(OP) \
-    case IR::OP_F80##OP: { \
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle); \
-      return true; \
-    }
-
-    // Unary
-    COMMON_X87_OP(ROUND)
-    COMMON_X87_OP(F2XM1)
-    COMMON_X87_OP(TAN)
-    COMMON_X87_OP(SQRT)
-    COMMON_X87_OP(SIN)
-    COMMON_X87_OP(COS)
-    COMMON_X87_OP(XTRACT_EXP)
-    COMMON_X87_OP(XTRACT_SIG)
-    COMMON_X87_OP(BCDSTORE)
-    COMMON_X87_OP(BCDLOAD)
-
-    // Binary
-    COMMON_X87_OP(ADD)
-    COMMON_X87_OP(SUB)
-    COMMON_X87_OP(MUL)
-    COMMON_X87_OP(DIV)
-    COMMON_X87_OP(FYL2X)
-    COMMON_X87_OP(ATAN)
-    COMMON_X87_OP(FPREM1)
-    COMMON_X87_OP(FPREM)
-    COMMON_X87_OP(SCALE)
-
-    default:
-      break;
-  }
-
-  return false;
+void InterpreterOps::Op_NoOp(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node) {
 }

 void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData) {
  volatile void *StackEntry = alloca(0);

-  // Debug data is only passed in debug builds
-  #ifndef NDEBUG
-  // TODO: should be moved to an IR Op
-  Thread->Stats.InstructionsExecuted.fetch_add(DebugData->GuestInstructionCount);
-  #endif
-
  uintptr_t ListSize = CurrentIR->GetSSACount();

  static_assert(sizeof(FEXCore::IR::IROp_Header) == 4);
@@ -280,11 +355,11 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uin
    auto CodeLast = CurrentIR->at(BlockIROp->Last);

    for (auto [CodeNode, IROp] : CurrentIR->GetCode(BlockNode)) {
-      uint32_t ID = CurrentIR->GetID(CodeNode);
-      uint32_t Op = IROp->Op;
+      const auto ID = CurrentIR->GetID(CodeNode);
+      const uint32_t Op = IROp->Op;

      // Execute handler
-      OpHandler Handler = InterpreterOps::OpHandlers[Op];
+      OpHandler Handler = InterpreterOpHandlers[Op];

      Handler(IROp, &OpData, ID);

@@ -1,6 +1,7 @@
 #pragma once
 #include <stdint.h>

+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>

@@ -38,26 +39,16 @@ namespace FEXCore::CPU {
  struct FallbackInfo {
    FallbackABI ABI;
    void *fn;
+    FEXCore::Core::FallbackHandlerIndex HandlerIndex;
  };

  class InterpreterOps {

    public:
      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
+      static void FillFallbackIndexPointers(uint64_t *Info);
      static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);

-      static void RegisterALUHandlers();
-      static void RegisterAtomicHandlers();
-      static void RegisterBranchHandlers();
-      static void RegisterConversionHandlers();
-      static void RegisterFlagHandlers();
-      static void RegisterMemoryHandlers();
-      static void RegisterMiscHandlers();
-      static void RegisterMoveHandlers();
-      static void RegisterVectorHandlers();
-      static void RegisterEncryptionHandlers();
-      static void RegisterF80Handlers();
-
      struct IROpData {
        FEXCore::Core::InternalThreadState *State{};
        uint64_t CurrentEntry{};
@@ -72,10 +63,7 @@ namespace FEXCore::CPU {
        IR::NodeIterator BlockIterator{0, 0};
      };

-      using OpHandler = std::function<void(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)>;
-      static std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers;
-
-#define DEF_OP(x) static void Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) static void Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)

  ///< Unhandled handler
  DEF_OP(Unhandled);
@@ -111,6 +99,8 @@ namespace FEXCore::CPU {
  DEF_OP(Rol);
  DEF_OP(Ror);
  DEF_OP(Extr);
+  DEF_OP(PDep);
+  DEF_OP(PExt);
  DEF_OP(LDiv);
  DEF_OP(LUDiv);
  DEF_OP(LRem);
@@ -152,13 +142,13 @@ namespace FEXCore::CPU {
  ///< Branch ops
  DEF_OP(GuestCallDirect);
  DEF_OP(GuestCallIndirect);
-  DEF_OP(GuestReturn);
  DEF_OP(SignalReturn);
  DEF_OP(CallbackReturn);
  DEF_OP(ExitFunction);
  DEF_OP(Jump);
  DEF_OP(CondJump);
  DEF_OP(Syscall);
+  DEF_OP(InlineSyscall);
  DEF_OP(Thunk);
  DEF_OP(ValidateCode);
  DEF_OP(RemoveCodeEntry);
@@ -194,6 +184,7 @@ namespace FEXCore::CPU {
  DEF_OP(VLoadMemElement);
  DEF_OP(VStoreMemElement);
  DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineZero);

  ///< Misc ops
  DEF_OP(EndBlock);
@@ -204,6 +195,8 @@ namespace FEXCore::CPU {
  DEF_OP(Print);
  DEF_OP(GetRoundingMode);
  DEF_OP(SetRoundingMode);
+  DEF_OP(ProcessorID);
+  DEF_OP(RDRAND);

  ///< Move ops
  DEF_OP(ExtractElementPair);
@@ -213,8 +206,6 @@ namespace FEXCore::CPU {
  ///< Vector ops
  DEF_OP(VectorZero);
  DEF_OP(VectorImm);
-  DEF_OP(CreateVector2);
-  DEF_OP(CreateVector4);
  DEF_OP(SplatVector);
  DEF_OP(VMov);
  DEF_OP(VAnd);
@@ -300,6 +291,7 @@ namespace FEXCore::CPU {
  DEF_OP(VSMull2);
  DEF_OP(VUABDL);
  DEF_OP(VTBL1);
+  DEF_OP(VRev64);

  ///< Encryption ops
  DEF_OP(AESImc);
@@ -308,6 +300,7 @@ namespace FEXCore::CPU {
  DEF_OP(AESDec);
  DEF_OP(AESDecLast);
  DEF_OP(AESKeyGenAssist);
+  DEF_OP(CRC32);

  ///< F80 ops
  DEF_OP(F80LOADFCW);
@@ -407,4 +400,4 @@ namespace FEXCore::CPU {
  }

  };
-};
+} // namespace FEXCore::CPU
@@ -22,7 +22,7 @@ static inline void CacheLineFlush(char *Addr) {
 #endif
 }

-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(LoadContext) {
  auto Op = IROp->C<IR::IROp_LoadContext>();
  uint8_t OpSize = IROp->Size;
@@ -264,26 +264,22 @@ DEF_OP(CacheLineClear) {
  CacheLineFlush(MemData);
 }

+DEF_OP(CacheLineZero) {
+  auto Op = IROp->C<IR::IROp_CacheLineZero>();
+
+  uintptr_t MemData = *GetSrc<uintptr_t*>(Data->SSAData, Op->Addr);
+
+  // Force cacheline alignment
+  MemData = MemData & ~(CPUIDEmu::CACHELINE_SIZE - 1);
+
+  using DataType = uint64_t;
+  DataType *MemData64 = reinterpret_cast<DataType*>(MemData);
+
+  // 64-byte cache line zero
+  for (size_t i = 0; i < (CPUIDEmu::CACHELINE_SIZE / sizeof(DataType)); ++i) {
+    MemData64[i] = 0;
+  }
+}
+
 #undef DEF_OP
-void InterpreterOps::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(LOADCONTEXT,         LoadContext);
-  REGISTER_OP(STORECONTEXT,        StoreContext);
-  REGISTER_OP(LOADREGISTER,        LoadRegister);
-  REGISTER_OP(STOREREGISTER,       StoreRegister);
-  REGISTER_OP(LOADCONTEXTINDEXED,  LoadContextIndexed);
-  REGISTER_OP(STORECONTEXTINDEXED, StoreContextIndexed);
-  REGISTER_OP(SPILLREGISTER,       SpillRegister);
-  REGISTER_OP(FILLREGISTER,        FillRegister);
-  REGISTER_OP(LOADFLAG,            LoadFlag);
-  REGISTER_OP(STOREFLAG,           StoreFlag);
-  REGISTER_OP(LOADMEM,             LoadMem);
-  REGISTER_OP(STOREMEM,            StoreMem);
-  REGISTER_OP(LOADMEMTSO,          LoadMem);
-  REGISTER_OP(STOREMEMTSO,         StoreMem);
-  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
-  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
-#undef REGISTER_OP
-}
-}
+} // namespace FEXCore::CPU
@@ -8,10 +8,13 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"

+#include <FEXHeaderUtils/Syscalls.h>
+
 #include <cstdint>
 #ifdef _M_X86_64
 #include <xmmintrin.h>
 #endif
+#include <sys/random.h>

 namespace FEXCore::CPU {
 [[noreturn]]
@@ -22,7 +25,7 @@ static void StopThread(FEXCore::Core::InternalThreadState *Thread) {
  FEX_UNREACHABLE;
 }

-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(Fence) {
  auto Op = IROp->C<IR::IROp_Fence>();
  switch (Op->Fence) {
@@ -42,9 +45,12 @@ DEF_OP(Fence) {
 DEF_OP(Break) {
  auto Op = IROp->C<IR::IROp_Break>();
  switch (Op->Reason) {
-    case 4: // HLT
+    case FEXCore::IR::Break_Halt: // HLT
      StopThread(Data->State);
    break;
+    case FEXCore::IR::Break_InvalidInstruction:
+      FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGILL);
+    break;
  default: LOGMAN_MSG_A_FMT("Unknown Break Reason: {}", Op->Reason); break;
  }
 }
@@ -137,22 +143,20 @@ DEF_OP(Print) {
    LOGMAN_MSG_A_FMT("Unknown value size: {}", OpSize);
 }

+DEF_OP(ProcessorID) {
+  uint32_t CPU, CPUNode;
+  FHU::Syscalls::getcpu(&CPU, &CPUNode);
+  GD = (CPUNode << 12) | CPU;
+}
+
+DEF_OP(RDRAND) {
+  // We are ignoring Op->GetReseeded in the interpreter
+  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
+  ssize_t Result = ::getrandom(&DstPtr[0], 8, 0);
+
+  // Second result is if we managed to read a valid random number or not
+  DstPtr[1] = Result == 8 ? 1 : 0;
+}
 #undef DEF_OP
-void InterpreterOps::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(DUMMY,      NoOp);
-  REGISTER_OP(IRHEADER,   NoOp);
-  REGISTER_OP(CODEBLOCK,  NoOp);
-  REGISTER_OP(BEGINBLOCK, NoOp);
-  REGISTER_OP(ENDBLOCK,   NoOp);
-  REGISTER_OP(FENCE,      Fence);
-  REGISTER_OP(BREAK,      Break);
-  REGISTER_OP(PHI,        NoOp);
-  REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Print);
-  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
-  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
-  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
-#undef REGISTER_OP
-}
-}
+
+} // namespace FEXCore::CPU
@@ -11,7 +11,7 @@ $end_info$
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
  uintptr_t Src = GetSrc<uintptr_t>(Data->SSAData, Op->Header.Args[0]);
@@ -26,8 +26,8 @@ DEF_OP(CreateElementPair) {

  uint8_t *Dst = GetDest<uint8_t*>(Data->SSAData, Node);

-  memcpy(Dst, Src_Lower, Op->Header.Size);
-  memcpy(Dst + Op->Header.Size, Src_Upper, Op->Header.Size);
+  memcpy(Dst, Src_Lower, IROp->ElementSize);
+  memcpy(Dst + IROp->ElementSize, Src_Upper, IROp->ElementSize);
 }

 DEF_OP(Mov) {
@@ -38,13 +38,5 @@ DEF_OP(Mov) {
 }

 #undef DEF_OP
-void InterpreterOps::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
-  REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
-  REGISTER_OP(MOV,                Mov);
-#undef REGISTER_OP
-}
-}
-

+} // namespace FEXCore::CPU
@@ -7,11 +7,13 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterClass.h"
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"
+#include <FEXCore/Utils/BitUtils.h>

+#include <bit>
 #include <cstdint>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(FEXCore::IR::IROp_Header *IROp, IROpData *Data, uint32_t Node)
+#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(VectorZero) {
  uint8_t OpSize = IROp->Size;
  memset(GDP, 0, OpSize);
@@ -37,39 +39,6 @@ DEF_OP(VectorImm) {
  memcpy(GDP, Tmp, OpSize);
 }

-DEF_OP(CreateVector2) {
-  auto Op = IROp->C<IR::IROp_CreateVector2>();
-  uint8_t OpSize = IROp->Size;
-
-  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  uint8_t Tmp[16];
-  uint8_t ElementSize = OpSize / 2;
-  #define CREATE_VECTOR(elementsize, type) \
-    case elementsize: { \
-      auto *Dst_d = reinterpret_cast<type*>(Tmp); \
-      auto *Src1_d = reinterpret_cast<type*>(Src1); \
-      auto *Src2_d = reinterpret_cast<type*>(Src2); \
-      Dst_d[0] = *Src1_d; \
-      Dst_d[1] = *Src2_d; \
-      break; \
-    }
-  switch (ElementSize) {
-    CREATE_VECTOR(1, uint8_t)
-    CREATE_VECTOR(2, uint16_t)
-    CREATE_VECTOR(4, uint32_t)
-    CREATE_VECTOR(8, uint64_t)
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize); break;
-  }
-  #undef CREATE_VECTOR
-  memcpy(GDP, Tmp, OpSize);
-}
-
-DEF_OP(CreateVector4) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
 DEF_OP(SplatVector) {
  auto Op = IROp->C<IR::IROp_SplatVector2>();
  uint8_t OpSize = IROp->Size;
@@ -1401,10 +1370,9 @@ DEF_OP(VInsScalarElement) {

 DEF_OP(VExtractElement) {
  auto Op = IROp->C<IR::IROp_VExtractElement>();
-  uint8_t OpSize = IROp->Size;

  uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Header.Args[0]);
-  LOGMAN_THROW_A_FMT(OpSize <= 16, "OpSize is too large for VExtractElement: {}", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 16, "OpSize is too large for VExtractElement: {}", IROp->Size);
  if (SourceSize == 16) {
    __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
    uint64_t Shift = Op->Header.ElementSize * Op->Index * 8;
@@ -1930,102 +1898,39 @@ DEF_OP(VTBL1) {
  memcpy(GDP, Tmp, OpSize);
 }

-#undef DEF_OP
-void InterpreterOps::RegisterVectorHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-  REGISTER_OP(VECTORZERO,        VectorZero);
-  REGISTER_OP(VECTORIMM,         VectorImm);
-  REGISTER_OP(CREATEVECTOR2,     CreateVector2);
-  REGISTER_OP(CREATEVECTOR4,     CreateVector4);
-  REGISTER_OP(SPLATVECTOR2,      SplatVector);
-  REGISTER_OP(SPLATVECTOR4,      SplatVector);
-  REGISTER_OP(VMOV,              VMov);
-  REGISTER_OP(VAND,              VAnd);
-  REGISTER_OP(VBIC,              VBic);
-  REGISTER_OP(VOR,               VOr);
-  REGISTER_OP(VXOR,              VXor);
-  REGISTER_OP(VADD,              VAdd);
-  REGISTER_OP(VSUB,              VSub);
-  REGISTER_OP(VUQADD,            VUQAdd);
-  REGISTER_OP(VUQSUB,            VUQSub);
-  REGISTER_OP(VSQADD,            VSQAdd);
-  REGISTER_OP(VSQSUB,            VSQSub);
-  REGISTER_OP(VADDP,             VAddP);
-  REGISTER_OP(VADDV,             VAddV);
-  REGISTER_OP(VUMINV,            VUMinV);
-  REGISTER_OP(VURAVG,            VURAvg);
-  REGISTER_OP(VABS,              VAbs);
-  REGISTER_OP(VPOPCOUNT,         VPopcount);
-  REGISTER_OP(VFADD,             VFAdd);
-  REGISTER_OP(VFADDP,            VFAddP);
-  REGISTER_OP(VFSUB,             VFSub);
-  REGISTER_OP(VFMUL,             VFMul);
-  REGISTER_OP(VFDIV,             VFDiv);
-  REGISTER_OP(VFMIN,             VFMin);
-  REGISTER_OP(VFMAX,             VFMax);
-  REGISTER_OP(VFRECP,            VFRecp);
-  REGISTER_OP(VFSQRT,            VFSqrt);
-  REGISTER_OP(VFRSQRT,           VFRSqrt);
-  REGISTER_OP(VNEG,              VNeg);
-  REGISTER_OP(VFNEG,             VFNeg);
-  REGISTER_OP(VNOT,              VNot);
-  REGISTER_OP(VUMIN,             VUMin);
-  REGISTER_OP(VSMIN,             VSMin);
-  REGISTER_OP(VUMAX,             VUMax);
-  REGISTER_OP(VSMAX,             VSMax);
-  REGISTER_OP(VZIP,              VZip);
-  REGISTER_OP(VZIP2,             VZip);
-  REGISTER_OP(VUNZIP,            VUnZip);
-  REGISTER_OP(VUNZIP2,           VUnZip);
-  REGISTER_OP(VBSL,              VBSL);
-  REGISTER_OP(VCMPEQ,            VCMPEQ);
-  REGISTER_OP(VCMPEQZ,           VCMPEQZ);
-  REGISTER_OP(VCMPGT,            VCMPGT);
-  REGISTER_OP(VCMPGTZ,           VCMPGTZ);
-  REGISTER_OP(VCMPLTZ,           VCMPLTZ);
-  REGISTER_OP(VFCMPEQ,           VFCMPEQ);
-  REGISTER_OP(VFCMPNEQ,          VFCMPNEQ);
-  REGISTER_OP(VFCMPLT,           VFCMPLT);
-  REGISTER_OP(VFCMPGT,           VFCMPGT);
-  REGISTER_OP(VFCMPLE,           VFCMPLE);
-  REGISTER_OP(VFCMPORD,          VFCMPORD);
-  REGISTER_OP(VFCMPUNO,          VFCMPUNO);
-  REGISTER_OP(VUSHL,             VUShl);
-  REGISTER_OP(VUSHR,             VUShr);
-  REGISTER_OP(VSSHR,             VSShr);
-  REGISTER_OP(VUSHLS,            VUShlS);
-  REGISTER_OP(VUSHRS,            VUShrS);
-  REGISTER_OP(VSSHRS,            VSShrS);
-  REGISTER_OP(VINSELEMENT,       VInsElement);
-  REGISTER_OP(VINSSCALARELEMENT, VInsScalarElement);
-  REGISTER_OP(VEXTRACTELEMENT,   VExtractElement);
-  REGISTER_OP(VDUPELEMENT,       VDupElement);
-  REGISTER_OP(VEXTR,             VExtr);
-  REGISTER_OP(VSLI,              VSLI);
-  REGISTER_OP(VSRI,              VSRI);
-  REGISTER_OP(VUSHRI,            VUShrI);
-  REGISTER_OP(VSSHRI,            VSShrI);
-  REGISTER_OP(VSHLI,             VShlI);
-  REGISTER_OP(VUSHRNI,           VUShrNI);
-  REGISTER_OP(VUSHRNI2,          VUShrNI2);
-  REGISTER_OP(VBITCAST,          VBitcast);
-  REGISTER_OP(VSXTL,             VSXTL);
-  REGISTER_OP(VSXTL2,            VSXTL2);
-  REGISTER_OP(VUXTL,             VUXTL);
-  REGISTER_OP(VUXTL2,            VUXTL2);
-  REGISTER_OP(VSQXTN,            VSQXTN);
-  REGISTER_OP(VSQXTN2,           VSQXTN2);
-  REGISTER_OP(VSQXTUN,           VSQXTUN);
-  REGISTER_OP(VSQXTUN2,          VSQXTUN2);
-  REGISTER_OP(VUMUL,             VUMul);
-  REGISTER_OP(VSMUL,             VSMul);
-  REGISTER_OP(VUMULL,            VUMull);
-  REGISTER_OP(VSMULL,            VSMull);
-  REGISTER_OP(VUMULL2,           VUMull2);
-  REGISTER_OP(VSMULL2,           VSMull2);
-  REGISTER_OP(VUABDL,            VUABDL);
-  REGISTER_OP(VTBL1,             VTBL1);
-#undef REGISTER_OP
-}
+DEF_OP(VRev64) {
+  auto Op = IROp->C<IR::IROp_VRev64>();
+  uint8_t OpSize = IROp->Size;
+
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+
+  uint8_t Tmp[16];
+
+  uint8_t Elements = OpSize / 8;
+
+  // The element working size is always 64-bit
+  // The defined element size in the op is the operating size of the element swapping
+  auto Func8 = [](auto a) { return BSwap64(a); };
+  auto Func16 = [](auto a) {
+    return (a >> 48) |                    // Element[3] -> Element[0]
+      ((a >> 16) & 0xFFFF'0000U) |        // Element[2] -> Element[1]
+      ((a << 16) & 0xFFFF'0000'0000ULL) | // Element[1] -> Element[2]
+      (a << 48);                          // Element[0] -> Element[3]
+  };
+  auto Func32 = [](auto a) {
+    return (a >> 32) | (a << 32);
+  };
+
+  switch (Op->Header.ElementSize) {
+    DO_VECTOR_1SRC_OP(1, uint64_t, Func8)
+    DO_VECTOR_1SRC_OP(2, uint64_t, Func16)
+    DO_VECTOR_1SRC_OP(4, uint64_t, Func32)
+
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+  }
+  memcpy(GDP, Tmp, Op->Header.Size);
 }

+#undef DEF_OP
+
+} // namespace FEXCore::CPU
@@ -8,37 +8,17 @@ $end_info$
 #include "Interface/IR/Passes/RegisterAllocationPass.h"

 namespace FEXCore::CPU {
-static uint64_t LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
-  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-  __uint128_t Res = Source / Divisor;
-  return Res;
-}

-static int64_t LDIV(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-  __int128_t Res = Source / Divisor;
-  return Res;
-}
-
-static uint64_t LUREM(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
-  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-  __uint128_t Res = Source % Divisor;
-  return Res;
-}
-
-static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-  __int128_t Res = Source % Divisor;
-  return Res;
-}
+#define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
+#define GRS(Node) (IROp->Size <= 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(TruncElementPair) {
  auto Op = IROp->C<IR::IROp_TruncElementPair>();

-  switch (Op->Size) {
+  switch (IROp->Size) {
    case 4: {
      auto Dst = GetSrcPair<RA_32>(Node);
      auto Src = GetSrcPair<RA_32>(Op->Header.Args[0].ID());
@@ -46,7 +26,7 @@ DEF_OP(TruncElementPair) {
      mov(Dst.second, Src.second);
      break;
    }
-    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", IROp->Size); break;
  }
 }

@@ -61,7 +41,13 @@ DEF_OP(EntrypointOffset) {

  auto Constant = Entry + Op->Offset;
  auto Dst = GetReg<RA_64>(Node);
-  LoadConstant(Dst, Constant);
+  uint64_t Mask = ~0ULL;
+  uint8_t OpSize = IROp->Size;
+  if (OpSize == 4) {
+    Mask = 0xFFFF'FFFFULL;
+  }
+
+  LoadConstant(Dst, Constant & Mask);
 }

 DEF_OP(InlineConstant) {
@@ -80,8 +66,6 @@ DEF_OP(CycleCounter) {
 #endif
 }

-#define GRS(Node) (IROp->Size <= 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
-
 DEF_OP(Add) {
  auto Op = IROp->C<IR::IROp_Add>();
  uint8_t OpSize = IROp->Size;
@@ -511,6 +495,125 @@ DEF_OP(Extr) {
  }
 }

+DEF_OP(PDep) {
+  auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const Register Input = GRS(Op->Args(0).ID());
+  const Register Mask = GRS(Op->Args(1).ID());
+  const Register Dest = GRS(Node);
+
+  const Register ShiftedBitReg = OpSize <= 4 ? TMP1.W() : TMP1;
+  const Register BitReg        = OpSize <= 4 ? TMP2.W() : TMP2;
+  const Register SubMaskReg    = OpSize <= 4 ? TMP3.W() : TMP3;
+  const Register IndexReg      = OpSize <= 4 ? TMP4.W() : TMP4;
+  const Register SizedZero     = OpSize <= 4 ? Register{wzr} : Register{xzr};
+
+  const Register InputReg = OpSize <= 4 ? SRA64[0].W() : SRA64[0];
+  const Register MaskReg  = OpSize <= 4 ? SRA64[1].W() : SRA64[1];
+  const Register DestReg  = OpSize <= 4 ? SRA64[2].W() : SRA64[2];
+  const auto SpillCode    = 1U << InputReg.GetCode() |
+                            1U << MaskReg.GetCode() |
+                            1U << DestReg.GetCode();
+
+  aarch64::Label EarlyExit;
+  aarch64::Label NextBit;
+  aarch64::Label Done;
+
+  cbz(Mask, &EarlyExit);
+  mov(IndexReg, SizedZero);
+
+  // We sadly need to spill regs for this for the time being
+  // TODO: Remove when scratch registers can be allocated
+  //       explicitly.
+  SpillStaticRegs(false, SpillCode);
+  mov(InputReg, Input);
+  mov(MaskReg, Mask);
+  mov(DestReg, SizedZero);
+
+  // Main loop
+  bind(&NextBit);
+  rbit(ShiftedBitReg, MaskReg);
+  clz(ShiftedBitReg, ShiftedBitReg);
+  lsrv(BitReg, InputReg, IndexReg);
+  and_(BitReg, BitReg, 1);
+  sub(SubMaskReg, MaskReg, 1);
+  add(IndexReg, IndexReg, 1);
+  ands(MaskReg, MaskReg, SubMaskReg);
+  lslv(ShiftedBitReg, BitReg, ShiftedBitReg);
+  orr(DestReg, DestReg, ShiftedBitReg);
+  b(&NextBit, Condition::ne);
+  // Store result in a temp so it doesn't get clobbered.
+  // and restore it after the re-fill below.
+  mov(IndexReg, DestReg);
+  // Restore our registers before leaving
+  // TODO: Also remove along with above TODO.
+  FillStaticRegs(false, SpillCode);
+  mov(Dest, IndexReg);
+  b(&Done);
+
+  // Early exit
+  bind(&EarlyExit);
+  mov(Dest, SizedZero);
+
+  // All done with nothing to do.
+  bind(&Done);
+}
+
+DEF_OP(PExt) {
+  auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const Register Input = GRS(Op->Args(0).ID());
+  const Register Mask = GRS(Op->Args(1).ID());
+  const Register Dest = GRS(Node);
+
+  const Register MaskReg    = OpSize <= 4 ? TMP1.W() : TMP1;
+  const Register BitReg     = OpSize <= 4 ? TMP2.W() : TMP2;
+  const Register SubMaskReg = OpSize <= 4 ? TMP3.W() : TMP3;
+  const Register Offset     = OpSize <= 4 ? TMP4.W() : TMP4;
+  const Register SizedZero  = OpSize <= 4 ? Register{wzr} : Register{xzr};
+
+  aarch64::Label EarlyExit;
+  aarch64::Label NextBit;
+  aarch64::Label Done;
+
+  cbz(Mask, &EarlyExit);
+  mov(MaskReg, Mask);
+  mov(Offset, SizedZero);
+
+  // We sadly need to spill a reg for this for the time being
+  // TODO: Remove when scratch registers can be allocated
+  //       explicitly.
+  SpillStaticRegs(false, 1U << Mask.GetCode());
+  mov(Mask, SizedZero);
+
+  // Main loop
+  bind(&NextBit);
+  rbit(BitReg, MaskReg);
+  clz(BitReg, BitReg);
+  sub(SubMaskReg, MaskReg, 1);
+  ands(MaskReg, SubMaskReg, MaskReg);
+  lsrv(BitReg, Input, BitReg);
+  and_(BitReg, BitReg, 1);
+  lslv(BitReg, BitReg, Offset);
+  add(Offset, Offset, 1);
+  orr(Mask, BitReg, Mask);
+  b(&NextBit, Condition::ne);
+  mov(Dest, Mask);
+  // Restore our mask register before leaving
+  // TODO: Also remove along with above TODO.
+  FillStaticRegs(false, 1U << Mask.GetCode());
+  b(&Done);
+
+  // Early exit
+  bind(&EarlyExit);
+  mov(Dest, SizedZero);
+
+  // All done with nothing to do.
+  bind(&Done);
+}
+
 DEF_OP(LDiv) {
  auto Op = IROp->C<IR::IROp_LDiv>();
  uint8_t OpSize = IROp->Size;
@@ -533,23 +636,42 @@ DEF_OP(LDiv) {
    break;
    }
    case 8: {
-      PushDynamicRegsAndLR();
+      auto Upper64Bit = GetReg<RA_64>(Op->Header.Args[1].ID());
+      auto Lower64Bit = GetReg<RA_64>(Op->Header.Args[0].ID());
+      auto Divisor = GetReg<RA_64>(Op->Header.Args[2].ID());
+      Label Only64Bit{};
+      Label LongDIVRet{};

-      mov(x0, GetReg<RA_64>(Op->Header.Args[1].ID()));
-      mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
-      mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
+      // Check if the upper bits match the top bit of the lower 64-bits
+      // Sign extend the top bit of lower bits
+      sbfx(TMP1, Lower64Bit, 63, 1);
+      eor(TMP1, TMP1, Upper64Bit);

-      LoadConstant(x3, reinterpret_cast<uint64_t>(LDIV));
-      SpillStaticRegs();
-      blr(x3);
-      FillStaticRegs();
+      // If the sign bit matches then the result is zero
+      cbz(TMP1, &Only64Bit);

-      // Result is now in x0
-      // Fix the stack and any values that were stepped on
-      PopDynamicRegsAndLR();
+      // Long divide
+      {
+        mov(x0, Upper64Bit);
+        mov(x1, Lower64Bit);
+        mov(x2, Divisor);

-      // Move result to its destination register
-      mov(GetReg<RA_64>(Node), x0);
+        ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler)));
+        blr(x3);
+        // Move result to its destination register
+        mov(GetReg<RA_64>(Node), x0);
+
+        // Skip 64-bit path
+        b(&LongDIVRet);
+      }
+
+      bind(&Only64Bit);
+      // 64-Bit only
+      {
+        sdiv(GetReg<RA_64>(Node), Lower64Bit, Divisor);
+      }
+
+      bind(&LongDIVRet);
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown LDIV Size: {}", Size); break;
@@ -576,23 +698,38 @@ DEF_OP(LUDiv) {
    break;
    }
    case 8: {
-      PushDynamicRegsAndLR();
+      auto Upper64Bit = GetReg<RA_64>(Op->Header.Args[1].ID());
+      auto Lower64Bit = GetReg<RA_64>(Op->Header.Args[0].ID());
+      auto Divisor = GetReg<RA_64>(Op->Header.Args[2].ID());
+      Label Only64Bit{};
+      Label LongDIVRet{};

-      mov(x0, GetReg<RA_64>(Op->Header.Args[1].ID()));
-      mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
-      mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
+      // Check the upper bits for zero
+      // If the upper bits are zero then we can do a 64-bit divide
+      cbz(Upper64Bit, &Only64Bit);

-      LoadConstant(x3, reinterpret_cast<uint64_t>(LUDIV));
-      SpillStaticRegs();
-      blr(x3);
-      FillStaticRegs();
+      // Long divide
+      {
+        mov(x0, Upper64Bit);
+        mov(x1, Lower64Bit);
+        mov(x2, Divisor);

-      // Result is now in x0
-      // Fix the stack and any values that were stepped on
-      PopDynamicRegsAndLR();
+        ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler)));
+        blr(x3);
+        // Move result to its destination register
+        mov(GetReg<RA_64>(Node), x0);

-      // Move result to its destination register
-      mov(GetReg<RA_64>(Node), x0);
+        // Skip 64-bit path
+        b(&LongDIVRet);
+      }
+
+      bind(&Only64Bit);
+      // 64-Bit only
+      {
+        udiv(GetReg<RA_64>(Node), Lower64Bit, Divisor);
+      }
+
+      bind(&LongDIVRet);
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", Size); break;
@@ -629,23 +766,42 @@ DEF_OP(LRem) {
    break;
    }
    case 8: {
-      PushDynamicRegsAndLR();
+      auto Upper64Bit = GetReg<RA_64>(Op->Header.Args[1].ID());
+      auto Lower64Bit = GetReg<RA_64>(Op->Header.Args[0].ID());
+      auto Divisor = GetReg<RA_64>(Op->Header.Args[2].ID());
+      Label Only64Bit{};
+      Label LongDIVRet{};

-      mov(x0, GetReg<RA_64>(Op->Header.Args[1].ID()));
-      mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
-      mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
+      // Check if the upper bits match the top bit of the lower 64-bits
+      // Sign extend the top bit of lower bits
+      sbfx(TMP1, Lower64Bit, 63, 1);
+      eor(TMP1, TMP1, Upper64Bit);

-      LoadConstant(x3, reinterpret_cast<uint64_t>(LREM));
-      SpillStaticRegs();
-      blr(x3);
-      FillStaticRegs();
+      // If the sign bit matches then the result is zero
+      cbz(TMP1, &Only64Bit);

-      // Result is now in x0
-      // Fix the stack and any values that were stepped on
-      PopDynamicRegsAndLR();
+      // Long divide
+      {
+        mov(x0, Upper64Bit);
+        mov(x1, Lower64Bit);
+        mov(x2, Divisor);

-      // Move result to its destination register
-      mov(GetReg<RA_64>(Node), x0);
+        ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LREMHandler)));
+        blr(x3);
+        // Move result to its destination register
+        mov(GetReg<RA_64>(Node), x0);
+
+        // Skip 64-bit path
+        b(&LongDIVRet);
+      }
+
+      bind(&Only64Bit);
+      // 64-Bit only
+      {
+        sdiv(TMP1, Lower64Bit, Divisor);
+        msub(GetReg<RA_64>(Node), TMP1, Divisor, Lower64Bit);
+      }
+      bind(&LongDIVRet);
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown LREM Size: {}", Size); break;
@@ -678,24 +834,39 @@ DEF_OP(LURem) {
    break;
    }
    case 8: {
+      auto Upper64Bit = GetReg<RA_64>(Op->Header.Args[1].ID());
+      auto Lower64Bit = GetReg<RA_64>(Op->Header.Args[0].ID());
+      auto Divisor = GetReg<RA_64>(Op->Header.Args[2].ID());
+      Label Only64Bit{};
+      Label LongDIVRet{};

-      PushDynamicRegsAndLR();
+      // Check the upper bits for zero
+      // If the upper bits are zero then we can do a 64-bit divide
+      cbz(Upper64Bit, &Only64Bit);

-      mov(x0, GetReg<RA_64>(Op->Header.Args[1].ID()));
-      mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
-      mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
+      // Long divide
+      {
+        mov(x0, Upper64Bit);
+        mov(x1, Lower64Bit);
+        mov(x2, Divisor);

-      LoadConstant(x3, reinterpret_cast<uint64_t>(LUREM));
-      SpillStaticRegs();
-      blr(x3);
-      FillStaticRegs();
+        ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUREMHandler)));
+        blr(x3);
+        // Move result to its destination register
+        mov(GetReg<RA_64>(Node), x0);

-      // Fix the stack and any values that were stepped on
-      PopDynamicRegsAndLR();
+        // Skip 64-bit path
+        b(&LongDIVRet);
+      }

-      // Result is now in x0
-      // Move result to its destination register
-      mov(GetReg<RA_64>(Node), x0);
+      bind(&Only64Bit);
+      // 64-Bit only
+      {
+        udiv(TMP1, Lower64Bit, Divisor);
+        msub(GetReg<RA_64>(Node), TMP1, Divisor, Lower64Bit);
+      }
+
+      bind(&LongDIVRet);
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown LUREM Size: {}", OpSize); break;
@@ -916,7 +1087,7 @@ Condition MapSelectCC(IR::CondClassType Cond) {
  case FEXCore::IR::COND_FLU: return Condition::lt;
  case FEXCore::IR::COND_FGE: return Condition::ge;
  case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::hi;
+  case FEXCore::IR::COND_FGT: return Condition::gt;
  case FEXCore::IR::COND_FU:  return Condition::vs;
  case FEXCore::IR::COND_FNU: return Condition::vc;
  case FEXCore::IR::COND_VS:
@@ -966,16 +1137,16 @@ DEF_OP(VExtractToGPR) {
  uint8_t OpSize = IROp->Size;
  switch (OpSize) {
    case 1:
-      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V16B(), Op->Idx);
+      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V16B(), Op->Index);
    break;
    case 2:
-      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V8H(), Op->Idx);
+      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V8H(), Op->Index);
    break;
    case 4:
-      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V4S(), Op->Idx);
+      umov(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).V4S(), Op->Index);
    break;
    case 8:
-      umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Idx);
+      umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Index);
    break;
    default:  LOGMAN_MSG_A_FMT("Unhandled ExtractElementSize: {}", OpSize);
  }
@@ -1099,6 +1270,8 @@ void Arm64JITCore::RegisterALUHandlers() {
  REGISTER_OP(ASHR,              Ashr);
  REGISTER_OP(ROR,               Ror);
  REGISTER_OP(EXTR,              Extr);
+  REGISTER_OP(PDEP,              PDep);
+  REGISTER_OP(PEXT,              PExt);
  REGISTER_OP(LDIV,              LDiv);
  REGISTER_OP(LUDIV,             LUDiv);
  REGISTER_OP(LREM,              LRem);
@@ -9,21 +9,20 @@ $end_info$
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(CASPair) {
  auto Op = IROp->C<IR::IROp_CASPair>();
-  uint8_t OpSize = IROp->Size;
  // Size is the size of each pair element
  auto Dst = GetSrcPair<RA_64>(Node);
-  auto Expected = GetSrcPair<RA_64>(Op->Header.Args[0].ID());
-  auto Desired = GetSrcPair<RA_64>(Op->Header.Args[1].ID());
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[2].ID());
+  auto Expected = GetSrcPair<RA_64>(Op->Expected.ID());
+  auto Desired = GetSrcPair<RA_64>(Op->Desired.ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    mov(TMP3, Expected.first);
    mov(TMP4, Expected.second);

-    switch (OpSize) {
+    switch (IROp->ElementSize) {
    case 4:
      caspal(TMP3.W(), TMP4.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc));
      mov(Dst.first.W(), TMP3.W());
@@ -34,11 +33,11 @@ DEF_OP(CASPair) {
      mov(Dst.first, TMP3);
      mov(Dst.second, TMP4);
      break;
-    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
    }
  }
  else {
-    switch (OpSize) {
+    switch (IROp->ElementSize) {
      case 4: {
        aarch64::Label LoopTop;
        aarch64::Label LoopNotExpected;
@@ -91,7 +90,7 @@ DEF_OP(CASPair) {
        bind(&LoopExpected);
        break;
      }
-      default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
    }
  }
 }
@@ -99,18 +98,15 @@ DEF_OP(CASPair) {
 DEF_OP(CAS) {
  auto Op = IROp->C<IR::IROp_CAS>();
  uint8_t OpSize = IROp->Size;
-  // Args[0]: Expected
-  // Args[1]: Desired
-  // Args[2]: Pointer
  // DataSrc = *Src1
  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
  // This will write to memory! Careful!

-  auto Expected = GetReg<RA_64>(Op->Header.Args[0].ID());
-  auto Desired = GetReg<RA_64>(Op->Header.Args[1].ID());
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[2].ID());
+  auto Expected = GetReg<RA_64>(Op->Expected.ID());
+  auto Desired = GetReg<RA_64>(Op->Desired.ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    mov(TMP2, Expected);
    switch (OpSize) {
    case 1: casalb(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
@@ -216,14 +212,14 @@ DEF_OP(CAS) {
 DEF_OP(AtomicAdd) {
  auto Op = IROp->C<IR::IROp_AtomicAdd>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: staddlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 2: staddlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 4: staddl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 8: staddl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
+    case 1: staddlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 2: staddlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 4: staddl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 8: staddl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -234,7 +230,7 @@ DEF_OP(AtomicAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -243,7 +239,7 @@ DEF_OP(AtomicAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -252,7 +248,7 @@ DEF_OP(AtomicAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -261,7 +257,7 @@ DEF_OP(AtomicAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        add(TMP2, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        add(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP2, TMP2, MemOperand(MemSrc));
        cbnz(TMP2, &LoopTop);
        break;
@@ -274,10 +270,10 @@ DEF_OP(AtomicAdd) {
 DEF_OP(AtomicSub) {
  auto Op = IROp->C<IR::IROp_AtomicSub>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
-    neg(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+  if (CTX->HostFeatures.SupportsAtomics) {
+    neg(TMP2, GetReg<RA_64>(Op->Value.ID()));
    switch (IROp->Size) {
    case 1: staddlb(TMP2.W(), MemOperand(MemSrc)); break;
    case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
@@ -293,7 +289,7 @@ DEF_OP(AtomicSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -302,7 +298,7 @@ DEF_OP(AtomicSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -311,7 +307,7 @@ DEF_OP(AtomicSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -320,7 +316,7 @@ DEF_OP(AtomicSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        sub(TMP2, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        sub(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP2, TMP2, MemOperand(MemSrc));
        cbnz(TMP2, &LoopTop);
        break;
@@ -333,10 +329,10 @@ DEF_OP(AtomicSub) {
 DEF_OP(AtomicAnd) {
  auto Op = IROp->C<IR::IROp_AtomicAnd>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
-    mvn(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+  if (CTX->HostFeatures.SupportsAtomics) {
+    mvn(TMP2, GetReg<RA_64>(Op->Value.ID()));
    switch (IROp->Size) {
    case 1: stclrlb(TMP2.W(), MemOperand(MemSrc)); break;
    case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
@@ -352,7 +348,7 @@ DEF_OP(AtomicAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -361,7 +357,7 @@ DEF_OP(AtomicAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -370,7 +366,7 @@ DEF_OP(AtomicAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -379,7 +375,7 @@ DEF_OP(AtomicAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        and_(TMP2, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        and_(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP2, TMP2, MemOperand(MemSrc));
        cbnz(TMP2, &LoopTop);
        break;
@@ -392,14 +388,14 @@ DEF_OP(AtomicAnd) {
 DEF_OP(AtomicOr) {
  auto Op = IROp->C<IR::IROp_AtomicOr>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: stsetlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 2: stsetlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 4: stsetl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 8: stsetl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
+    case 1: stsetlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 2: stsetlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 4: stsetl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 8: stsetl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -410,7 +406,7 @@ DEF_OP(AtomicOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -419,7 +415,7 @@ DEF_OP(AtomicOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -428,7 +424,7 @@ DEF_OP(AtomicOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -437,7 +433,7 @@ DEF_OP(AtomicOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        orr(TMP2, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        orr(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP2, TMP2, MemOperand(MemSrc));
        cbnz(TMP2, &LoopTop);
        break;
@@ -450,14 +446,14 @@ DEF_OP(AtomicOr) {
 DEF_OP(AtomicXor) {
  auto Op = IROp->C<IR::IROp_AtomicXor>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: steorlb(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 2: steorlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 4: steorl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    case 8: steorl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
+    case 1: steorlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 2: steorlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 4: steorl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
+    case 8: steorl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -468,7 +464,7 @@ DEF_OP(AtomicXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -477,7 +473,7 @@ DEF_OP(AtomicXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -486,7 +482,7 @@ DEF_OP(AtomicXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
        cbnz(TMP2.W(), &LoopTop);
        break;
@@ -495,7 +491,7 @@ DEF_OP(AtomicXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        eor(TMP2, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        eor(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP2, TMP2, MemOperand(MemSrc));
        cbnz(TMP2, &LoopTop);
        break;
@@ -508,10 +504,10 @@ DEF_OP(AtomicXor) {
 DEF_OP(AtomicSwap) {
  auto Op = IROp->C<IR::IROp_AtomicSwap>();

-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
-    mov(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+  if (CTX->HostFeatures.SupportsAtomics) {
+    mov(TMP2, GetReg<RA_64>(Op->Value.ID()));
    switch (IROp->Size) {
    case 1: swplb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
    case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
@@ -527,7 +523,7 @@ DEF_OP(AtomicSwap) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
+        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        uxtb(GetReg<RA_32>(Node), TMP2.W());
        break;
@@ -536,7 +532,7 @@ DEF_OP(AtomicSwap) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
+        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        uxtw(GetReg<RA_32>(Node), TMP2.W());
        break;
@@ -545,7 +541,7 @@ DEF_OP(AtomicSwap) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        stlxr(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
+        stlxr(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
        break;
@@ -554,7 +550,7 @@ DEF_OP(AtomicSwap) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        stlxr(TMP4, GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
+        stlxr(TMP4, GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2.X());
        break;
@@ -566,14 +562,14 @@ DEF_OP(AtomicSwap) {

 DEF_OP(AtomicFetchAdd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: ldaddalb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldaddalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldaddal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldaddal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
+    case 1: ldaddalb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 2: ldaddalh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 4: ldaddal(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 8: ldaddal(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -584,7 +580,7 @@ DEF_OP(AtomicFetchAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -594,7 +590,7 @@ DEF_OP(AtomicFetchAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -604,7 +600,7 @@ DEF_OP(AtomicFetchAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -614,7 +610,7 @@ DEF_OP(AtomicFetchAdd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        add(TMP3, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        add(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP4, TMP3, MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2);
@@ -627,10 +623,10 @@ DEF_OP(AtomicFetchAdd) {

 DEF_OP(AtomicFetchSub) {
  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
-    neg(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+  if (CTX->HostFeatures.SupportsAtomics) {
+    neg(TMP2, GetReg<RA_64>(Op->Value.ID()));
    switch (IROp->Size) {
    case 1: ldaddalb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
    case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
@@ -646,7 +642,7 @@ DEF_OP(AtomicFetchSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -656,7 +652,7 @@ DEF_OP(AtomicFetchSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -666,7 +662,7 @@ DEF_OP(AtomicFetchSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -676,7 +672,7 @@ DEF_OP(AtomicFetchSub) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        sub(TMP3, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        sub(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP4, TMP3, MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2);
@@ -689,10 +685,10 @@ DEF_OP(AtomicFetchSub) {

 DEF_OP(AtomicFetchAnd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
-    mvn(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+  if (CTX->HostFeatures.SupportsAtomics) {
+    mvn(TMP2, GetReg<RA_64>(Op->Value.ID()));
    switch (IROp->Size) {
    case 1: ldclralb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
    case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
@@ -708,7 +704,7 @@ DEF_OP(AtomicFetchAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -718,7 +714,7 @@ DEF_OP(AtomicFetchAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -728,7 +724,7 @@ DEF_OP(AtomicFetchAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -738,7 +734,7 @@ DEF_OP(AtomicFetchAnd) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        and_(TMP3, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        and_(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP4, TMP3, MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2);
@@ -751,14 +747,14 @@ DEF_OP(AtomicFetchAnd) {

 DEF_OP(AtomicFetchOr) {
  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: ldsetalb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldsetalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldsetal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldsetal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
+    case 1: ldsetalb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 2: ldsetalh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 4: ldsetal(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 8: ldsetal(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -769,7 +765,7 @@ DEF_OP(AtomicFetchOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -779,7 +775,7 @@ DEF_OP(AtomicFetchOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -789,7 +785,7 @@ DEF_OP(AtomicFetchOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -799,7 +795,7 @@ DEF_OP(AtomicFetchOr) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        orr(TMP3, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        orr(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP4, TMP3, MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2);
@@ -812,14 +808,14 @@ DEF_OP(AtomicFetchOr) {

 DEF_OP(AtomicFetchXor) {
  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

-  if (SupportsAtomics) {
+  if (CTX->HostFeatures.SupportsAtomics) {
    switch (IROp->Size) {
-    case 1: ldeoralb(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldeoralh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldeoral(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldeoral(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
+    case 1: ldeoralb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 2: ldeoralh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 4: ldeoral(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
+    case 8: ldeoral(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
    }
  }
@@ -830,7 +826,7 @@ DEF_OP(AtomicFetchXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -840,7 +836,7 @@ DEF_OP(AtomicFetchXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -850,7 +846,7 @@ DEF_OP(AtomicFetchXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
        cbnz(TMP4.W(), &LoopTop);
        mov(GetReg<RA_32>(Node), TMP2.W());
@@ -860,7 +856,7 @@ DEF_OP(AtomicFetchXor) {
        aarch64::Label LoopTop;
        bind(&LoopTop);
        ldaxr(TMP2, MemOperand(MemSrc));
-        eor(TMP3, TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
+        eor(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
        stlxr(TMP4, TMP3, MemOperand(MemSrc));
        cbnz(TMP4, &LoopTop);
        mov(GetReg<RA_64>(Node), TMP2);
@@ -873,7 +869,7 @@ DEF_OP(AtomicFetchXor) {

 DEF_OP(AtomicFetchNeg) {
  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
-  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());

  // TMP2-TMP3
  switch (IROp->Size) {
@@ -4,6 +4,7 @@ tags: backend|arm64
 $end_info$
 */

+#include "FEXCore/IR/IR.h"
 #include "Interface/Core/LookupCache.h"

 #include "Interface/Core/JIT/Arm64/JITClass.h"
@@ -11,12 +12,13 @@ $end_info$

 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/HLE/SyscallHandler.h>
+#include <FEXCore/Utils/MathUtils.h>
 #include <Interface/HLE/Thunks/Thunks.h>

 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GuestCallDirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }
@@ -25,17 +27,13 @@ DEF_OP(GuestCallIndirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }

-DEF_OP(GuestReturn) {
-  LogMan::Msg::DFmt("Unimplemented");
-}
-
 DEF_OP(SignalReturn) {
  // First we must reset the stack
  ResetStack();

  // Now branch to our signal return helper
  // This can't be a direct branch since the code needs to live at a constant location
-  LoadConstant(x0, ThreadSharedData.SignalReturnInstruction);
+  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.SignalReturnHandler)));
  br(x0);
 }

@@ -48,7 +46,7 @@ DEF_OP(CallbackReturn) {
  ResetStack();

  // We can now lower the ref counter again
-  LoadConstant(x0, reinterpret_cast<uint64_t>(ThreadSharedData.SignalHandlerRefCounterPtr));
+  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.SignalHandlerRefCountPointer)));
  ldr(w2, MemOperand(x0));
  sub(w2, w2, 1);
  str(w2, MemOperand(x0));
@@ -87,7 +85,7 @@ DEF_OP(ExitFunction) {
    RipReg = GetReg<RA_64>(Op->Header.Args[0].ID());

    // L1 Cache
-    LoadConstant(x0, ThreadState->LookupCache->GetL1Pointer());
+    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.L1Pointer)));

    and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
    add(x0, x0, Operand(x3, Shift::LSL, 4));
@@ -98,30 +96,23 @@ DEF_OP(ExitFunction) {
    br(x1);

    bind(&FullLookup);
-    LoadConstant(TMP1, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.DispatcherLoopTop)));
    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
    br(TMP1);
  }
 }

 DEF_OP(Jump) {
-  auto Op = IROp->C<IR::IROp_Jump>();
+  const auto Op = IROp->C<IR::IROp_Jump>();
+  const auto ArgID = Op->Args(0).ID();

-  Label *TargetLabel;
-  auto IsTarget = JumpTargets.find(Op->Header.Args[0].ID());
-  if (IsTarget == JumpTargets.end()) {
-    TargetLabel = &JumpTargets.try_emplace(Op->Header.Args[0].ID()).first->second;
-  }
-  else {
-    TargetLabel = &IsTarget->second;
-  }
-  PendingTargetLabel = TargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(ArgID).first->second;
 }

 #define GRCMP(Node) (Op->CompareSize == 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
 #define GRFCMP(Node) (Op->CompareSize == 4 ? GetDst(Node).S() : GetDst(Node).D())

-Condition MapBranchCC(IR::CondClassType Cond) {
+static Condition MapBranchCC(IR::CondClassType Cond) {
  switch (Cond.Val) {
  case FEXCore::IR::COND_EQ: return Condition::eq;
  case FEXCore::IR::COND_NEQ: return Condition::ne;
@@ -136,7 +127,7 @@ Condition MapBranchCC(IR::CondClassType Cond) {
  case FEXCore::IR::COND_FLU: return Condition::lt;
  case FEXCore::IR::COND_FGE: return Condition::ge;
  case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::hi;
+  case FEXCore::IR::COND_FGT: return Condition::gt;
  case FEXCore::IR::COND_FU:  return Condition::vs;
  case FEXCore::IR::COND_FNU: return Condition::vc;
  case FEXCore::IR::COND_VS:
@@ -153,22 +144,10 @@ Condition MapBranchCC(IR::CondClassType Cond) {
 DEF_OP(CondJump) {
  auto Op = IROp->C<IR::IROp_CondJump>();

-  Label *TrueTargetLabel;
-  Label *FalseTargetLabel;
-
-  auto TrueIter = JumpTargets.find(Op->TrueBlock.ID());
-  auto FalseIter = JumpTargets.find(Op->FalseBlock.ID());
-
-  if (TrueIter == JumpTargets.end()) {
-    TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-  }
-  else {
-    TrueTargetLabel = &TrueIter->second;
-  }
-
+  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;

  uint64_t Const;
-  bool isConst = IsInlineConstant(Op->Cmp2, &Const);
+  const bool isConst = IsInlineConstant(Op->Cmp2, &Const);

  if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
@@ -178,10 +157,11 @@ DEF_OP(CondJump) {
    cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
  } else {
    if (IsGPR(Op->Cmp1.ID())) {
-      if (isConst)
+      if (isConst) {
        cmp(GRCMP(Op->Cmp1.ID()), Const);
-      else
+      } else {
        cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
+      }
    } else if (IsFPR(Op->Cmp1.ID())) {
      fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
    } else {
@@ -191,13 +171,7 @@ DEF_OP(CondJump) {
    b(TrueTargetLabel, MapBranchCC(Op->Cond));
  }

-  if (FalseIter == JumpTargets.end()) {
-    FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-  }
-  else {
-    FalseTargetLabel = &FalseIter->second;
-  }
-  PendingTargetLabel = FalseTargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
 }

 DEF_OP(Syscall) {
@@ -207,8 +181,16 @@ DEF_OP(Syscall) {
  // X1: ThreadState
  // X2: Pointer to SyscallArguments

+  FEXCore::IR::SyscallFlags Flags = Op->Flags;
  PushDynamicRegsAndLR();
-  SpillStaticRegs();
+
+  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) {
+    SpillStaticRegs();
+  }
+  else {
+    // Need to spill all caller saved registers still
+    SpillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
+  }

  uint64_t SPOffset = AlignUp(FEXCore::HLE::SyscallArguments::MAX_ARGS * 8, 16);
  sub(sp, sp, SPOffset);
@@ -217,22 +199,178 @@ DEF_OP(Syscall) {
    str(GetReg<RA_64>(Op->Header.Args[i].ID()), MemOperand(sp, i * 8));
  }

-  LoadConstant(x0, reinterpret_cast<uint64_t>(CTX->SyscallHandler));
+  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.SyscallHandlerObj)));
+  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.SyscallHandlerFunc)));
  mov(x1, STATE);
  mov(x2, sp);
-
-  LoadConstant(x3, reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall));
  blr(x3);

  add(sp, sp, SPOffset);

-  // Result is now in x0
-  // Fix the stack and any values that were stepped on
-  FillStaticRegs();
+  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY &&
+      (Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
+    FillStaticRegs();
+  }
+  else {
+    // Result is now in x0
+    // Fix the stack and any values that were stepped on
+    FillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
+  }
+
  PopDynamicRegsAndLR();

-  // Move result to its destination register
-  mov(GetReg<RA_64>(Node), x0);
+  if ((Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
+    // Move result to its destination register
+    mov(GetReg<RA_64>(Node), x0);
+  }
+}
+
+DEF_OP(InlineSyscall) {
+  auto Op = IROp->C<IR::IROp_InlineSyscall>();
+  // Arguments are passed as follows:
+  // X8: SyscallNumber - RA INTERSECT
+  // X0: Arg0 & Return
+  // X1: Arg1
+  // X2: Arg2
+  // X3: Arg3
+  // X4: Arg4 - RA INTERSECT
+  // X5: Arg5 - RA INTERSECT
+  // X6: Arg6 - Doesn't exist in x86-64 land. RA INTERSECT
+
+  // One argument is removed from the SyscallArguments::MAX_ARGS since the first argument was syscall number
+  const static std::array<vixl::aarch64::Register, FEXCore::HLE::SyscallArguments::MAX_ARGS-1> RegArgs = {{
+    x0, x1, x2, x3, x4, x5
+  }};
+
+  bool Intersects{};
+  // We always need to spill x8 since we can't know if it is live at this SSA location
+  uint32_t SpillMask = 1U << 8;
+  std::vector<vixl::aarch64::Register> IntersectRegs(FEXCore::HLE::SyscallArguments::MAX_ARGS);
+  for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+    if (Op->Header.Args[i].IsInvalid()) break;
+
+    auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+    if (Reg.GetCode() == x8.GetCode() ||
+        Reg.GetCode() == x4.GetCode() ||
+        Reg.GetCode() == x5.GetCode()) {
+
+      SpillMask |= (1U << Reg.GetCode());
+      Intersects = true;
+    }
+  }
+  // XXX: For some reason spilling only the x4, x5, and x8 registers was causing issues
+  // Come back to this once investigation reveals why it fails the gvisor ioctl test
+  // For now override to all GPRs
+  SpillMask = ~0U;
+
+  // Ordering is incredibly important here
+  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
+  // Only spill the registers that intersect with our usage
+  SpillStaticRegs(false, SpillMask);
+
+  // Now that we are spilled, store in the state that we are in a syscall
+  // Still without overwriting registers that matter
+  // 16bit LoadConstant to be a single instruction
+  // We must always spill at least one register (x8) so this value always has a bit set
+  // This gives the signal handler a value to check to see if we are in a syscall at all
+  LoadConstant(x0, SpillMask & 0xFFFF);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+  // Now that we have claimed to be a syscall we can set up the arguments
+  if (Intersects) {
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+        // In the case of intersection with x4, x5, or x8 then these are currently SRA
+        // for registers RAX, RBX, and RSI. Which have just been spilled
+        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
+        if (Reg.GetCode() == x8.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == x4.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == x5.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+      }
+    }
+
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
+        // In the case of intersection with x4, x5, or x8 then these are currently SRA
+        // for registers RAX, RBX, and RSI. Which have just been spilled
+        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
+        if (Reg.GetCode() == x8.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == x4.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == x5.GetCode()) {
+          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+        else {
+          mov(RegArgs[i], Reg);
+        }
+      }
+      else {
+        auto Reg = GetReg<RA_32>(Op->Header.Args[i].ID());
+        if (Reg.GetCode() == w8.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
+        }
+        else if (Reg.GetCode() == w4.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
+        }
+        else if (Reg.GetCode() == w5.GetCode()) {
+          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
+        }
+        else {
+          uxtw(RegArgs[i].W(), Reg);
+        }
+      }
+    }
+  }
+  else {
+    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
+      if (Op->Header.Args[i].IsInvalid()) break;
+
+      if (CTX->Config.Is64BitMode()) {
+        mov(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
+      }
+      else {
+        uxtw(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
+      }
+    }
+  }
+
+  LoadConstant(x8, Op->HostSyscallNumber);
+  svc(0);
+  // On updated signal mask we can receive a signal RIGHT HERE
+
+  if ((Op->Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
+    // Now that we are done in the syscall we need to carefully peel back the state
+    // First unspill the registers from before
+    FillStaticRegs(false, SpillMask);
+
+    // Now the registers we've spilled are back in their original host registers
+    // We can safely claim we are no longer in a syscall
+    str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+    // Result is now in x0
+    // Move result to its destination register
+    if (CTX->Config.Is64BitMode()) {
+      mov(GetReg<RA_64>(Node), x0);
+    }
+    else {
+      uxtw(GetReg<RA_64>(Node), x0);
+    }
+  }
 }

 DEF_OP(Thunk) {
@@ -256,7 +394,6 @@ DEF_OP(Thunk) {
  FillStaticRegs(); // load from ctx after ra64 refill
 }

-
 DEF_OP(ValidateCode) {
  auto Op = IROp->C<IR::IROp_ValidateCode>();
  const auto *OldCode = (const uint8_t *)&Op->CodeOriginalLow;
@@ -315,7 +452,7 @@ DEF_OP(RemoveCodeEntry) {
  mov(x0, STATE);
  LoadConstant(x1, Entry);

-  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.RemoveCodeEntryFromJIT)));
  SpillStaticRegs();
  blr(x2);
  FillStaticRegs();
@@ -332,19 +469,10 @@ DEF_OP(CPUID) {
  // x0 = CPUID Handler
  // x1 = CPUID Function
  // x2 = CPUID Leaf
-  LoadConstant(x0, reinterpret_cast<uint64_t>(&CTX->CPUID));
+  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.CPUIDObj)));
+  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.CPUIDFunction)));
  mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
  mov(x2, GetReg<RA_64>(Op->Header.Args[1].ID()));
-
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t, uint32_t);
-  union PtrCast {
-    ClassPtrType ClassPtr;
-    uintptr_t Data;
-  };
-
-  PtrCast Ptr;
-  Ptr.ClassPtr = &FEXCore::CPUIDEmu::RunFunction;
-  LoadConstant(x3, Ptr.Data);
  SpillStaticRegs();
  blr(x3);
  FillStaticRegs();
@@ -363,13 +491,13 @@ void Arm64JITCore::RegisterBranchHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
  REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
  REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
-  REGISTER_OP(GUESTRETURN,       GuestReturn);
  REGISTER_OP(SIGNALRETURN,      SignalReturn);
  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
  REGISTER_OP(EXITFUNCTION,      ExitFunction);
  REGISTER_OP(JUMP,              Jump);
  REGISTER_OP(CONDJUMP,          CondJump);
  REGISTER_OP(SYSCALL,           Syscall);
+  REGISTER_OP(INLINESYSCALL,     InlineSyscall);
  REGISTER_OP(THUNK,             Thunk);
  REGISTER_OP(VALIDATECODE,      ValidateCode);
  REGISTER_OP(REMOVECODEENTRY,   RemoveCodeEntry);
@@ -10,25 +10,25 @@ namespace FEXCore::CPU {

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VInsGPR) {
  auto Op = IROp->C<IR::IROp_VInsGPR>();
  mov(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
  switch (Op->Header.ElementSize) {
    case 1: {
-      ins(GetDst(Node).V16B(), Op->Index, GetReg<RA_32>(Op->Header.Args[1].ID()));
+      ins(GetDst(Node).V16B(), Op->DestIdx, GetReg<RA_32>(Op->Header.Args[1].ID()));
    break;
    }
    case 2: {
-      ins(GetDst(Node).V8H(), Op->Index, GetReg<RA_32>(Op->Header.Args[1].ID()));
+      ins(GetDst(Node).V8H(), Op->DestIdx, GetReg<RA_32>(Op->Header.Args[1].ID()));
    break;
    }
    case 4: {
-      ins(GetDst(Node).V4S(), Op->Index, GetReg<RA_32>(Op->Header.Args[1].ID()));
+      ins(GetDst(Node).V4S(), Op->DestIdx, GetReg<RA_32>(Op->Header.Args[1].ID()));
    break;
    }
    case 8: {
-      ins(GetDst(Node).V2D(), Op->Index, GetReg<RA_64>(Op->Header.Args[1].ID()));
+      ins(GetDst(Node).V2D(), Op->DestIdx, GetReg<RA_64>(Op->Header.Args[1].ID()));
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
@@ -39,11 +39,11 @@ DEF_OP(VCastFromGPR) {
  auto Op = IROp->C<IR::IROp_VCastFromGPR>();
  switch (Op->Header.ElementSize) {
    case 1:
-      uxtb(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()).W());
+      uxtb(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()));
      fmov(GetDst(Node).S(), TMP1.W());
      break;
    case 2:
-      uxth(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()).W());
+      uxth(TMP1.W(), GetReg<RA_32>(Op->Header.Args[0].ID()));
      fmov(GetDst(Node).S(), TMP1.W());
      break;
    case 4:
@@ -10,7 +10,7 @@ $end_info$
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(AESImc) {
  auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -54,7 +54,7 @@ DEF_OP(AESDecLast) {
 DEF_OP(AESKeyGenAssist) {
 	auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();

-  aarch64::Label Constant;
+  aarch64::Literal ConstantLiteral (0x0C030609'0306090CULL, 0x040B0E01'0B0E0104ULL);
  aarch64::Label PastConstant;

  // Do a "regular" AESE step
@@ -63,8 +63,7 @@ DEF_OP(AESKeyGenAssist) {
  aese(VTMP1.V16B(), VTMP2.V16B());

  // Do a table shuffle to undo ShiftRows
-  adr(TMP1.X(), &Constant);
-  ldr(VTMP3, MemOperand(TMP1.X()));
+  ldr(VTMP3, &ConstantLiteral);

  // Now EOR in the RCON
  if (Op->RCON) {
@@ -80,14 +79,29 @@ DEF_OP(AESKeyGenAssist) {
  }

  b(&PastConstant);
-  bind(&Constant);
-  dc32(0x0B0E0104);
-  dc32(0x040B0E01);
-  dc32(0x0306090C);
-  dc32(0x0C030609);
+  place(&ConstantLiteral);
  bind(&PastConstant);
 }

+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  switch (Op->SrcSize) {
+    case 1:
+      crc32cb(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 2:
+      crc32ch(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 4:
+      crc32cw(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
+      break;
+    case 8:
+      crc32cx(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_64>(Op->Src2.ID()));
+      break;
+    default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", Op->SrcSize);
+  }
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterEncryptionHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
@@ -97,7 +111,7 @@ void Arm64JITCore::RegisterEncryptionHandlers() {
  REGISTER_OP(VAESDEC,     AESDec);
  REGISTER_OP(VAESDECLAST, AESDecLast);
  REGISTER_OP(VAESKEYGENASSIST, AESKeyGenAssist);
-
+  REGISTER_OP(CRC32,             CRC32);
 #undef REGISTER_OP
 }
 }
@@ -10,7 +10,7 @@ namespace FEXCore::CPU {

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
  auto Op = IROp->C<IR::IROp_GetHostFlag>();
  ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Op->Flag, 1);
@@ -21,10 +21,13 @@ $end_info$

 #include "Interface/IR/Passes/RegisterAllocationPass.h"

+#include "Utils/MemberFunctionToPointer.h"
+
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Core/UContext.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+
 #include "Interface/Core/Interpreter/InterpreterOps.h"

 #include <sys/mman.h>
@@ -32,6 +35,40 @@ $end_info$
 #include <unistd.h>
 #include <string.h>

+namespace {
+static uint64_t LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
+  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
+  __uint128_t Res = Source / Divisor;
+  return Res;
+}
+
+static int64_t LDIV(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
+  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+  __int128_t Res = Source / Divisor;
+  return Res;
+}
+
+static uint64_t LUREM(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
+  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
+  __uint128_t Res = Source % Divisor;
+  return Res;
+}
+
+static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
+  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+  __int128_t Res = Source % Divisor;
+  return Res;
+}
+
+static void PrintValue(uint64_t Value) {
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
+}
+
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
+}
+}
+
 namespace FEXCore::CPU {

 void Arm64JITCore::CopyNecessaryDataForCompileThread(CPUBackend *Original) {
@@ -42,7 +79,7 @@ void Arm64JITCore::CopyNecessaryDataForCompileThread(CPUBackend *Original) {
 using namespace vixl;
 using namespace vixl::aarch64;

-void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
+void Arm64JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
  FallbackInfo Info;
  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -56,8 +93,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushDynamicRegsAndLR();

        uxth(w0, GetReg<RA_32>(IROp->Args[0].ID()));
-        LoadConstant(x1, (uintptr_t)Info.fn);
-
+        ldr(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x1);

        PopDynamicRegsAndLR();
@@ -72,8 +108,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushDynamicRegsAndLR();

        fmov(v0.S(), GetSrc(IROp->Args[0].ID()).S()) ;
-        LoadConstant(x0, (uintptr_t)Info.fn);
-
+        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x0);

        PopDynamicRegsAndLR();
@@ -92,8 +127,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushDynamicRegsAndLR();

        mov(v0.D(), GetSrc(IROp->Args[0].ID()).D());
-        LoadConstant(x0, (uintptr_t)Info.fn);
-
+        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x0);

        PopDynamicRegsAndLR();
@@ -118,8 +152,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        else {
          mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
        }
-        LoadConstant(x1, (uintptr_t)Info.fn);
-
+        ldr(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x1);

        PopDynamicRegsAndLR();
@@ -140,8 +173,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -160,8 +192,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -180,8 +211,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -199,8 +229,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -218,8 +247,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -240,8 +268,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
        umov(w3, GetSrc(IROp->Args[1].ID()).V8H(), 4);

-        LoadConstant(x4, (uintptr_t)Info.fn);
-
+        ldr(x4, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x4);

        PopDynamicRegsAndLR();
@@ -259,8 +286,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

-        LoadConstant(x2, (uintptr_t)Info.fn);
-
+        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x2);

        PopDynamicRegsAndLR();
@@ -283,8 +309,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
        umov(w3, GetSrc(IROp->Args[1].ID()).V8H(), 4);

-        LoadConstant(x4, (uintptr_t)Info.fn);
-
+        ldr(x4, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.FallbackHandlerPointers[Info.HandlerIndex])));
        blr(x4);

        PopDynamicRegsAndLR();
@@ -307,7 +332,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
  }
 }

-void Arm64JITCore::Op_NoOp(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
+void Arm64JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
 }

 Arm64JITCore::CodeBuffer Arm64JITCore::AllocateNewCodeBuffer(size_t Size) {
@@ -333,27 +358,9 @@ void Arm64JITCore::FreeCodeBuffer(CodeBuffer Buffer) {
 }

 Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread)
-  : Arm64Emitter(0)
+  : Arm64Emitter(ctx, 0)
  , CTX {ctx}
  , ThreadState {Thread} {
-  {
-    DispatcherConfig config;
-    config.ExitFunctionLink = reinterpret_cast<uintptr_t>(&ExitFunctionLink);
-    config.ExitFunctionLinkThis = reinterpret_cast<uintptr_t>(this);
-    config.StaticRegisterAssignment = ctx->Config.StaticRegisterAllocation;
-
-    Dispatcher = std::make_unique<Arm64Dispatcher>(CTX, ThreadState, config);
-    DispatchPtr = Dispatcher->DispatchPtr;
-    CallbackPtr = Dispatcher->CallbackPtr;
-  }
-
-  // Can't allocate a code buffer until after dispatcher is created
-  InitialCodeBuffer = AllocateNewCodeBuffer(Arm64JITCore::INITIAL_CODE_SIZE);
-  *GetBuffer() = vixl::CodeBuffer(InitialCodeBuffer.Ptr, InitialCodeBuffer.Size);
-  SetAllowAssembler(true);
-
-  CurrentCodeBuffer = &InitialCodeBuffer;
-
  RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");

 #if DEBUG
@@ -393,42 +400,100 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::Intern
  RegisterVectorHandlers();
  RegisterEncryptionHandlers();

+  {
+    DispatcherConfig config;
+    config.ExitFunctionLink = reinterpret_cast<uintptr_t>(&ExitFunctionLink);
+    config.ExitFunctionLinkThis = reinterpret_cast<uintptr_t>(this);
+    config.StaticRegisterAssignment = ctx->Config.StaticRegisterAllocation;
+
+    Dispatcher = std::make_unique<Arm64Dispatcher>(CTX, ThreadState, config);
+    DispatchPtr = Dispatcher->DispatchPtr;
+    CallbackPtr = Dispatcher->CallbackPtr;
+  }
+
  if (!CompileThread) {
    ThreadSharedData.SignalHandlerRefCounterPtr = &Dispatcher->SignalHandlerRefCounter;
    ThreadSharedData.SignalReturnInstruction = Dispatcher->SignalHandlerReturnAddress;
+    ThreadSharedData.UnimplementedInstructionAddress = Dispatcher->UnimplementedInstructionAddress;
+    ThreadSharedData.OverflowExceptionInstructionAddress = Dispatcher->OverflowExceptionInstructionAddress;
+
    ThreadSharedData.Dispatcher = Dispatcher.get();
-
-    // This will register the host signal handler per thread, which is fine
-    CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleSIGILL(Signal, info, ucontext);
-    }, true);
-
-    CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
-
-      if (!Core->Dispatcher->IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext))) {
-        // Wasn't a sigbus in JIT code
-        return false;
-      }
-
-      return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(Core->CTX->Config.ParanoidTSO(), Signal, info, ucontext);
-    }, true);
-
-    CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
-    }, true);
-
-    auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
-      Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-    };
-
-    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
-      CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
-    }
  }
+
+  {
+    // Set up pointers that the JIT needs to load
+    auto &Pointers = ThreadState->CurrentFrame->Pointers.AArch64;
+    // Process specific
+    Pointers.LUDIV = reinterpret_cast<uint64_t>(LUDIV);
+    Pointers.LDIV = reinterpret_cast<uint64_t>(LDIV);
+    Pointers.LUREM = reinterpret_cast<uint64_t>(LUREM);
+    Pointers.LREM = reinterpret_cast<uint64_t>(LREM);
+    Pointers.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
+    Pointers.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
+    Pointers.RemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit);
+    Pointers.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
+
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction);
+      Pointers.CPUIDFunction = PMF.GetConvertedPointer();
+    }
+
+    Pointers.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
+    Pointers.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
+
+    // Fill in the fallback handlers
+    InterpreterOps::FillFallbackIndexPointers(Pointers.FallbackHandlerPointers);
+
+    // Thread Specific
+    Pointers.SignalHandlerRefCountPointer = reinterpret_cast<uint64_t>(&Dispatcher->SignalHandlerRefCounter);
+  }
+
+  // Can't allocate a code buffer until after dispatcher is created
+  InitialCodeBuffer = AllocateNewCodeBuffer(Arm64JITCore::INITIAL_CODE_SIZE);
+  *GetBuffer() = vixl::CodeBuffer(InitialCodeBuffer.Ptr, InitialCodeBuffer.Size);
+  SetAllowAssembler(true);
+  EmitDetectionString();
+
+  CurrentCodeBuffer = &InitialCodeBuffer;
+}
+
+void Arm64JITCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
+  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleSIGILL(Signal, info, ucontext);
+  }, true);
+
+  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
+
+    if (!Core->Dispatcher->IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext))) {
+      // Wasn't a sigbus in JIT code
+      return false;
+    }
+
+    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(Core->CTX->Config.ParanoidTSO(), Signal, info, ucontext);
+  }, true);
+
+  CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
+  }, true);
+
+  auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
+    Arm64JITCore *Core = reinterpret_cast<Arm64JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+  };
+
+  for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
+    CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
+  }
+}
+
+void Arm64JITCore::EmitDetectionString() {
+  const char JITString[] = "FEXJIT::Arm64JITCore::";
+  auto Buffer = GetBuffer();
+  Buffer->EmitString(JITString);
+  Buffer->Align();
 }

 void Arm64JITCore::ClearCache() {
@@ -471,6 +536,7 @@ void Arm64JITCore::ClearCache() {
    EmplaceNewCodeBuffer(NewCodeBuffer);
    *Buffer = vixl::CodeBuffer(NewCodeBuffer.Ptr, NewCodeBuffer.Size);
  }
+  EmitDetectionString();
 }

 Arm64JITCore::~Arm64JITCore() {
@@ -482,7 +548,7 @@ Arm64JITCore::~Arm64JITCore() {
  FreeCodeBuffer(InitialCodeBuffer);
 }

-IR::PhysicalRegister Arm64JITCore::GetPhys(uint32_t Node) const {
+IR::PhysicalRegister Arm64JITCore::GetPhys(IR::NodeID Node) const {
  auto PhyReg = RAData->GetNodeRegister(Node);

  LOGMAN_THROW_A_FMT(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
@@ -491,7 +557,7 @@ IR::PhysicalRegister Arm64JITCore::GetPhys(uint32_t Node) const {
 }

 template<>
-aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(uint32_t Node) const {
+aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(IR::NodeID Node) const {
  auto Reg = GetPhys(Node);

  if (Reg.Class == IR::GPRFixedClass.Val) {
@@ -506,7 +572,7 @@ aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(uint32_t Node) const
 }

 template<>
-aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(uint32_t Node) const {
+aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(IR::NodeID Node) const {
  auto Reg = GetPhys(Node);

  if (Reg.Class == IR::GPRFixedClass.Val) {
@@ -521,18 +587,18 @@ aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(uint32_t Node) const
 }

 template<>
-std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_32>(uint32_t Node) const {
+std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_32>(IR::NodeID Node) const {
  uint32_t Reg = GetPhys(Node).Reg;
  return RA32Pair[Reg];
 }

 template<>
-std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_64>(uint32_t Node) const {
+std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_64>(IR::NodeID Node) const {
  uint32_t Reg = GetPhys(Node).Reg;
  return RA64Pair[Reg];
 }

-aarch64::VRegister Arm64JITCore::GetSrc(uint32_t Node) const {
+aarch64::VRegister Arm64JITCore::GetSrc(IR::NodeID Node) const {
  auto Reg = GetPhys(Node);

  if (Reg.Class == IR::FPRFixedClass.Val) {
@@ -546,7 +612,7 @@ aarch64::VRegister Arm64JITCore::GetSrc(uint32_t Node) const {
  FEX_UNREACHABLE;
 }

-aarch64::VRegister Arm64JITCore::GetDst(uint32_t Node) const {
+aarch64::VRegister Arm64JITCore::GetDst(IR::NodeID Node) const {
  auto Reg = GetPhys(Node);

  if (Reg.Class == IR::FPRFixedClass.Val) {
@@ -580,7 +646,12 @@ bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode,
  if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
    auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
    if (Value) {
-      *Value = Entry + Op->Offset;
+      uint64_t Mask = ~0ULL;
+      uint8_t OpSize = OpHeader->Size;
+      if (OpSize == 4) {
+        Mask = 0xFFFF'FFFFULL;
+      }
+      *Value = (Entry + Op->Offset) & Mask;
    }
    return true;
  } else {
@@ -588,18 +659,18 @@ bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode,
  }
 }

-FEXCore::IR::RegisterClassType Arm64JITCore::GetRegClass(uint32_t Node) const {
+FEXCore::IR::RegisterClassType Arm64JITCore::GetRegClass(IR::NodeID Node) const {
  return FEXCore::IR::RegisterClassType {GetPhys(Node).Class};
 }


-bool Arm64JITCore::IsFPR(uint32_t Node) const {
+bool Arm64JITCore::IsFPR(IR::NodeID Node) const {
  auto Class = GetRegClass(Node);

  return Class == IR::FPRClass || Class == IR::FPRFixedClass;
 }

-bool Arm64JITCore::IsGPR(uint32_t Node) const {
+bool Arm64JITCore::IsGPR(IR::NodeID Node) const {
  auto Class = GetRegClass(Node);

  return Class == IR::GPRClass || Class == IR::GPRFixedClass;
@@ -666,13 +737,13 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
      str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));

      // Stop the thread
-      LoadConstant(x0, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddressSpillSRA);
+      ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.ThreadPauseHandlerSpillSRA)));
      br(x0);
    }
    bind(&RunBlock);
  }

-  //LOGMAN_THROW_A(RAData->HasFullRA(), "Arm64 JIT only works with RA");
+  //LOGMAN_THROW_A_FMT(RAData->HasFullRA(), "Arm64 JIT only works with RA");

  SpillSlots = RAData->SpillSlots();

@@ -694,12 +765,10 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif

+    uintptr_t BlockStartHostCode = GetCursorAddress<uintptr_t>();
    {
-      uint32_t Node = IR->GetID(BlockNode);
-      auto IsTarget = JumpTargets.find(Node);
-      if (IsTarget == JumpTargets.end()) {
-        IsTarget = JumpTargets.try_emplace(Node).first;
-      }
+      const auto Node = IR->GetID(BlockNode);
+      const auto IsTarget = JumpTargets.try_emplace(Node).first;

      // if there's a pending branch, and it is not fall-through
      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second)
@@ -711,12 +780,8 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
      bind(&IsTarget->second);
    }

-    if (DebugData) {
-      DebugData->Subblocks.push_back({GetCursorAddress<uintptr_t>(), 0, IR->GetID(BlockNode)});
-    }
-
    for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
-      uint32_t ID = IR->GetID(CodeNode);
+      const auto ID = IR->GetID(CodeNode);

      // Execute handler
      OpHandler Handler = OpHandlers[IROp->Op];
@@ -724,7 +789,7 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
    }

    if (DebugData) {
-      DebugData->Subblocks.back().HostCodeSize = GetCursorAddress<uintptr_t>() - DebugData->Subblocks.back().HostCodeStart;
+      DebugData->Subblocks.push_back({BlockStartHostCode, static_cast<uint32_t>(GetCursorAddress<uintptr_t>() - BlockStartHostCode)});
    }
  }

@@ -801,4 +866,8 @@ uint64_t Arm64JITCore::ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuSt
 std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
  return std::make_unique<Arm64JITCore>(ctx, Thread, CompileThread);
 }
+
+void InitializeArm64JITSignalHandlers(FEXCore::Context::Context *CTX) {
+  Arm64JITCore::InitializeSignalHandlers(CTX);
+}
 }
@@ -64,6 +64,11 @@ public:
  [[nodiscard]] CodeBuffer AllocateNewCodeBuffer(size_t Size);

  void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true, bool IncludeCompileService = true) const override {
+    return Dispatcher->IsAddressInJITCode(Address, IncludeDispatcher, IncludeCompileService);
+  }
+
+  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);

 private:
  FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
@@ -75,7 +80,7 @@ private:
  FEXCore::IR::IRListView const *IR;
  uint64_t Entry;

-  std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;
+  std::map<IR::NodeID, aarch64::Label> JumpTargets;

  /**
   * @name Register Allocation
@@ -99,30 +104,30 @@ private:
  constexpr static uint8_t RA_FPR = 2;

  template<uint8_t RAType>
-  [[nodiscard]] aarch64::Register GetReg(uint32_t Node) const;
+  [[nodiscard]] aarch64::Register GetReg(IR::NodeID Node) const;

  template<>
-  [[nodiscard]] aarch64::Register GetReg<RA_32>(uint32_t Node) const;
+  [[nodiscard]] aarch64::Register GetReg<RA_32>(IR::NodeID Node) const;
  template<>
-  [[nodiscard]] aarch64::Register GetReg<RA_64>(uint32_t Node) const;
+  [[nodiscard]] aarch64::Register GetReg<RA_64>(IR::NodeID Node) const;

  template<uint8_t RAType>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node) const;
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair(IR::NodeID Node) const;

  template<>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node) const;
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(IR::NodeID Node) const;
  template<>
-  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node) const;
+  [[nodiscard]] std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(IR::NodeID Node) const;

-  [[nodiscard]] aarch64::VRegister GetSrc(uint32_t Node) const;
-  [[nodiscard]] aarch64::VRegister GetDst(uint32_t Node) const;
+  [[nodiscard]] aarch64::VRegister GetSrc(IR::NodeID Node) const;
+  [[nodiscard]] aarch64::VRegister GetDst(IR::NodeID Node) const;

-  [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node) const;
+  [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(IR::NodeID Node) const;

-  [[nodiscard]] IR::PhysicalRegister GetPhys(uint32_t Node) const;
+  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const;

-  [[nodiscard]] bool IsFPR(uint32_t Node) const;
-  [[nodiscard]] bool IsGPR(uint32_t Node) const;
+  [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
+  [[nodiscard]] bool IsGPR(IR::NodeID Node) const;

  [[nodiscard]] MemOperand GenerateMemOperand(uint8_t AccessSize,
                                              aarch64::Register Base,
@@ -172,17 +177,22 @@ private:

  struct CompilerSharedData {
    uint64_t SignalReturnInstruction{};
+    uint64_t UnimplementedInstructionAddress{};
+    uint64_t OverflowExceptionInstructionAddress{};

    uint32_t *SignalHandlerRefCounterPtr{};
    FEXCore::CPU::Dispatcher *Dispatcher{};
  };

  CompilerSharedData ThreadSharedData;
+
+  // This is purely a debugging aid for developers to see if they are in JIT code space when inspecting raw memory
+  void EmitDetectionString();
  IR::RegisterAllocationPass *RAPass;
  IR::RegisterAllocationData *RAData;

-  using OpHandler = void (Arm64JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
-  std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
+  using OpHandler = void (Arm64JITCore::*)(IR::IROp_Header *IROp, IR::NodeID Node);
+  std::array<OpHandler, IR::IROps::OP_LAST + 1> OpHandlers {};
  void RegisterALUHandlers();
  void RegisterAtomicHandlers();
  void RegisterBranchHandlers();
@@ -193,7 +203,7 @@ private:
  void RegisterMoveHandlers();
  void RegisterVectorHandlers();
  void RegisterEncryptionHandlers();
-#define DEF_OP(x) void Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

  ///< Unhandled handler
  DEF_OP(Unhandled);
@@ -229,6 +239,8 @@ private:
  DEF_OP(Rol);
  DEF_OP(Ror);
  DEF_OP(Extr);
+  DEF_OP(PDep);
+  DEF_OP(PExt);
  DEF_OP(LDiv);
  DEF_OP(LUDiv);
  DEF_OP(LRem);
@@ -270,13 +282,13 @@ private:
  ///< Branch ops
  DEF_OP(GuestCallDirect);
  DEF_OP(GuestCallIndirect);
-  DEF_OP(GuestReturn);
  DEF_OP(SignalReturn);
  DEF_OP(CallbackReturn);
  DEF_OP(ExitFunction);
  DEF_OP(Jump);
  DEF_OP(CondJump);
  DEF_OP(Syscall);
+  DEF_OP(InlineSyscall);
  DEF_OP(Thunk);
  DEF_OP(ValidateCode);
  DEF_OP(RemoveCodeEntry);
@@ -297,7 +309,7 @@ private:
  DEF_OP(GetHostFlag);

  ///< Memory ops
-    DEF_OP(LoadContext);
+  DEF_OP(LoadContext);
  DEF_OP(StoreContext);
  DEF_OP(LoadRegister);
  DEF_OP(StoreRegister);
@@ -316,6 +328,7 @@ private:
  DEF_OP(VLoadMemElement);
  DEF_OP(VStoreMemElement);
  DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineZero);

  ///< Misc ops
  DEF_OP(EndBlock);
@@ -326,6 +339,8 @@ private:
  DEF_OP(Print);
  DEF_OP(GetRoundingMode);
  DEF_OP(SetRoundingMode);
+  DEF_OP(ProcessorID);
+  DEF_OP(RDRAND);

  ///< Move ops
  DEF_OP(ExtractElementPair);
@@ -335,8 +350,6 @@ private:
  ///< Vector ops
  DEF_OP(VectorZero);
  DEF_OP(VectorImm);
-  DEF_OP(CreateVector2);
-  DEF_OP(CreateVector4);
  DEF_OP(SplatVector2);
  DEF_OP(SplatVector4);
  DEF_OP(VMov);
@@ -424,6 +437,7 @@ private:
  DEF_OP(VSMull2);
  DEF_OP(VUABDL);
  DEF_OP(VTBL1);
+  DEF_OP(VRev64);

  ///< Encryption ops
  DEF_OP(AESImc);
@@ -432,6 +446,7 @@ private:
  DEF_OP(AESDec);
  DEF_OP(AESDecLast);
  DEF_OP(AESKeyGenAssist);
+  DEF_OP(CRC32);
 #undef DEF_OP
 };

@@ -11,7 +11,7 @@ namespace FEXCore::CPU {

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(LoadContext) {
  auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -623,7 +623,7 @@ DEF_OP(LoadMemTSO) {
    LOGMAN_MSG_A_FMT("LoadMemTSO: No offset allowed");
  }

-  if (SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
+  if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
    if (IROp->Size == 1) {
      // 8bit load is always aligned to natural alignment
      auto Dst = GetReg<RA_64>(Node);
@@ -698,29 +698,29 @@ DEF_OP(LoadMemTSO) {
 DEF_OP(StoreMem) {
  auto Op = IROp->C<IR::IROp_StoreMem>();

-  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+  auto MemReg = GetReg<RA_64>(Op->Addr.ID());

  auto MemSrc = GenerateMemOperand(IROp->Size, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);

  if (Op->Class == FEXCore::IR::GPRClass) {
    switch (IROp->Size) {
      case 1:
-        strb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+        strb(GetReg<RA_64>(Op->Value.ID()), MemSrc);
        break;
      case 2:
-        strh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+        strh(GetReg<RA_64>(Op->Value.ID()), MemSrc);
        break;
      case 4:
-        str(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+        str(GetReg<RA_32>(Op->Value.ID()), MemSrc);
        break;
      case 8:
-        str(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+        str(GetReg<RA_64>(Op->Value.ID()), MemSrc);
        break;
      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", IROp->Size);
    }
  }
  else {
-    auto Src = GetSrc(Op->Header.Args[1].ID());
+    auto Src = GetSrc(Op->Value.ID());
    switch (IROp->Size) {
      case 1:
        str(Src.B(), MemSrc);
@@ -744,7 +744,7 @@ DEF_OP(StoreMem) {

 DEF_OP(StoreMemTSO) {
  auto Op = IROp->C<IR::IROp_StoreMemTSO>();
-  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Addr.ID()));

  if (!Op->Offset.IsInvalid()) {
    LOGMAN_MSG_A_FMT("StoreMemTSO: No offset allowed");
@@ -753,19 +753,19 @@ DEF_OP(StoreMemTSO) {
  if (Op->Class == FEXCore::IR::GPRClass) {
    if (IROp->Size == 1) {
      // 8bit load is always aligned to natural alignment
-      stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+      stlrb(GetReg<RA_64>(Op->Value.ID()), MemSrc);
    }
    else {
      nop();
      switch (IROp->Size) {
        case 2:
-          stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          stlrh(GetReg<RA_64>(Op->Value.ID()), MemSrc);
          break;
        case 4:
-          stlr(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+          stlr(GetReg<RA_32>(Op->Value.ID()), MemSrc);
          break;
        case 8:
-          stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          stlr(GetReg<RA_64>(Op->Value.ID()), MemSrc);
          break;
        default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", IROp->Size);
      }
@@ -774,7 +774,7 @@ DEF_OP(StoreMemTSO) {
  }
  else {
    dmb(InnerShareable, BarrierAll);
-    auto Src = GetSrc(Op->Header.Args[1].ID());
+    auto Src = GetSrc(Op->Value.ID());
    switch (IROp->Size) {
      case 1:
        str(Src.B(), MemSrc);
@@ -800,7 +800,7 @@ DEF_OP(StoreMemTSO) {
 DEF_OP(ParanoidLoadMemTSO) {
  auto Op = IROp->C<IR::IROp_LoadMemTSO>();

-  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Addr.ID()));

  if (!Op->Offset.IsInvalid()) {
    LOGMAN_MSG_A_FMT("ParanoidLoadMemTSO: No offset allowed");
@@ -857,7 +857,7 @@ DEF_OP(ParanoidLoadMemTSO) {

 DEF_OP(ParanoidStoreMemTSO) {
  auto Op = IROp->C<IR::IROp_StoreMemTSO>();
-  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Addr.ID()));

  if (!Op->Offset.IsInvalid()) {
    LOGMAN_MSG_A_FMT("ParanoidStoreMemTSO: No offset allowed");
@@ -866,25 +866,25 @@ DEF_OP(ParanoidStoreMemTSO) {
  if (Op->Class == FEXCore::IR::GPRClass) {
    if (IROp->Size == 1) {
      // 8bit load is always aligned to natural alignment
-      stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+      stlrb(GetReg<RA_64>(Op->Value.ID()), MemSrc);
    }
    else {
      switch (IROp->Size) {
        case 2:
-          stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          stlrh(GetReg<RA_64>(Op->Value.ID()), MemSrc);
          break;
        case 4:
-          stlr(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+          stlr(GetReg<RA_32>(Op->Value.ID()), MemSrc);
          break;
        case 8:
-          stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          stlr(GetReg<RA_64>(Op->Value.ID()), MemSrc);
          break;
        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", IROp->Size);
      }
    }
  }
  else {
-    auto Src = GetSrc(Op->Header.Args[1].ID());
+    auto Src = GetSrc(Op->Value.ID());
    if (IROp->Size == 1) {
      // 8bit load is always aligned to natural alignment
      mov(TMP1.W(), Src.V16B(), 0);
@@ -939,13 +939,35 @@ DEF_OP(CacheLineClear) {
  // Clear dcache only
  // icache doesn't matter here since the guest application shouldn't be calling clflush on JIT code.
  mov(TMP1, MemReg);
-  for (size_t i = 0; i < std::max(1U, DCacheLineSize / 64U); ++i) {
+  for (size_t i = 0; i < std::max(1U, CTX->HostFeatures.DCacheLineSize / 64U); ++i) {
    dc(DataCacheOp::CVAU, TMP1);
-    add(TMP1, TMP1, DCacheLineSize);
+    add(TMP1, TMP1, CTX->HostFeatures.DCacheLineSize);
  }
  dsb(InnerShareable, BarrierAll);
 }

+DEF_OP(CacheLineZero) {
+  auto Op = IROp->C<IR::IROp_CacheLineZero>();
+
+  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  if (CTX->HostFeatures.SupportsCLZERO) {
+    // We can use this instruction directly
+    dc(DataCacheOp::ZVA, MemReg);
+  }
+  else {
+    // We must walk the cacheline ourselves
+    // Force cacheline alignment
+    and_(TMP1, MemReg, ~(CPUIDEmu::CACHELINE_SIZE - 1));
+    // This will end up being four STPs
+    // Depending on uarch it could be slightly more efficient in instructions emitted
+    // and uops to use vector pair STP, but we want the non-temporal bit specifically here
+    for (size_t i = 0; i < CPUIDEmu::CACHELINE_SIZE; i += 16) {
+      stnp(xzr, xzr, MemOperand(TMP1, i, Offset));
+    }
+  }
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterMemoryHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
@@ -972,6 +994,7 @@ void Arm64JITCore::RegisterMemoryHandlers() {
  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
+  REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP
 }
 }
@@ -7,17 +7,9 @@ $end_info$
 #include "Interface/Core/JIT/Arm64/JITClass.h"

 namespace FEXCore::CPU {
-static void PrintValue(uint64_t Value) {
-  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
-}
-
-static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
-}
-
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(Fence) {
  auto Op = IROp->C<IR::IROp_Fence>();
@@ -38,35 +30,39 @@ DEF_OP(Fence) {
 DEF_OP(Break) {
  auto Op = IROp->C<IR::IROp_Break>();
  switch (Op->Reason) {
-    case 0: // Hard fault
-    case 5: // Guest ud2
+    case FEXCore::IR::Break_Unimplemented: // Hard fault
+    case FEXCore::IR::Break_Interrupt: // Guest ud2
      hlt(4);
      break;
-    case 1: // Int <imm8>
-      hlt(4);
+    case FEXCore::IR::Break_Overflow: // overflow
+      ResetStack();
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.OverflowExceptionHandler)));
+      br(TMP1);
      break;
-    case 2: // overflow
-      hlt(4);
-      break;
-    case 3: // int 1
-      hlt(4);
-      break;
-    case 4: { // HLT
+    case FEXCore::IR::Break_Halt: { // HLT
      // Time to quit
      // Set our stack to the starting stack location
      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
      add(sp, TMP1, 0);

      // Now we need to jump to the thread stop handler
-      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddressSpillSRA);
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.ThreadStopHandlerSpillSRA)));
      br(TMP1);
      break;
    }
-    case 6: { // INT3
+    case FEXCore::IR::Break_Interrupt3: { // INT3
+      ResetStack();
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.ThreadPauseHandlerSpillSRA)));
+      br(TMP1);
+      break;
+    }
+    case FEXCore::IR::Break_InvalidInstruction:
+    {
      ResetStack();

-      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddressSpillSRA);
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.UnimplementedInstructionHandler)));
      br(TMP1);
+
      break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
@@ -138,13 +134,13 @@ DEF_OP(Print) {

  if (IsGPR(Op->Header.Args[0].ID())) {
    mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
-    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintValue));
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.PrintValue)));
  }
  else {
    fmov(x0, GetSrc(Op->Header.Args[0].ID()).V1D());
    // Bug in vixl that source vector needs to b V1D rather than V2D?
    fmov(x1, GetSrc(Op->Header.Args[0].ID()).V1D(), 1);
-    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintVectorValue));
+    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.PrintVectorValue)));
  }
  SpillStaticRegs();
  blr(x3);
@@ -153,6 +149,76 @@ DEF_OP(Print) {
  PopDynamicRegsAndLR();
 }

+DEF_OP(ProcessorID) {
+  // We always need to spill x8 since we can't know if it is live at this SSA location
+  uint32_t SpillMask = 1U << 8;
+
+  // Ordering is incredibly important here
+  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
+  // Only spill the registers that intersect with our usage
+  SpillStaticRegs(false, SpillMask);
+
+  // Now that we are spilled, store in the state that we are in a syscall
+  // Still without overwriting registers that matter
+  // 16bit LoadConstant to be a single instruction
+  // We must always spill at least one register (x8) so this value always has a bit set
+  // This gives the signal handler a value to check to see if we are in a syscall at all
+  LoadConstant(x0, SpillMask & 0xFFFF);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+  // Allocate some temporary space for storing the uint32_t CPU and Node IDs
+  sub(sp, sp, 16);
+
+  // Load the getcpu syscall number
+  LoadConstant(x8, SYS_getcpu);
+
+  // CPU pointer in x0
+  add(x0, sp, 0);
+  // Node in x1
+  add(x1, sp, 4);
+
+  svc(0);
+  // On updated signal mask we can receive a signal RIGHT HERE
+
+  // Load the values returned by the kernel
+  ldp(w0, w1, MemOperand(sp));
+  // Deallocate stack space
+  sub(sp, sp, 16);
+
+  // Now that we are done in the syscall we need to carefully peel back the state
+  // First unspill the registers from before
+  FillStaticRegs(false, SpillMask);
+
+  // Now the registers we've spilled are back in their original host registers
+  // We can safely claim we are no longer in a syscall
+  str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
+
+
+  // Now store the result in the destination in the expected format
+  // uint32_t Res = (node << 12) | cpu;
+  // CPU is in w0
+  // Node is in w1
+  orr(GetReg<RA_64>(Node), x0, Operand(x1, LSL, 12));
+}
+
+DEF_OP(RDRAND) {
+  auto Op = IROp->C<IR::IROp_RDRAND>();
+
+  // Results are in x0, x1
+  // Results want to be in a i64v2 vector
+  auto Dst = GetSrcPair<RA_64>(Node);
+
+  if (Op->GetReseeded) {
+    mrs(Dst.first, RNDRRS);
+  }
+  else {
+    mrs(Dst.first, RNDR);
+  }
+
+  // If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
+  cset(Dst.second, Condition::ne);
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterMiscHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
@@ -169,6 +235,9 @@ void Arm64JITCore::RegisterMiscHandlers() {
  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
+  REGISTER_OP(PROCESSORID,   ProcessorID);
+  REGISTER_OP(RDRAND, RDRAND);
+
 #undef REGISTER_OP
 }
 }
@@ -10,7 +10,7 @@ namespace FEXCore::CPU {

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
  switch (Op->Header.Size) {
@@ -37,7 +37,7 @@ DEF_OP(CreateElementPair) {
  aarch64::Register RegSecond;
  aarch64::Register RegTmp;

-  switch (Op->Header.Size) {
+  switch (IROp->ElementSize) {
    case 4: {
      Dst = GetSrcPair<RA_32>(Node);
      RegFirst = GetReg<RA_32>(Op->Header.Args[0].ID());
@@ -10,7 +10,7 @@ namespace FEXCore::CPU {

 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VectorZero) {
  uint8_t OpSize = IROp->Size;
  switch (OpSize) {
@@ -42,14 +42,6 @@ DEF_OP(VectorImm) {
  }
 }

-DEF_OP(CreateVector2) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(CreateVector4) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
 DEF_OP(SplatVector2) {
  auto Op = IROp->C<IR::IROp_SplatVector2>();
  uint8_t OpSize = IROp->Size;
@@ -1758,8 +1750,7 @@ DEF_OP(VInsScalarElement) {

 DEF_OP(VExtractElement) {
  auto Op = IROp->C<IR::IROp_VExtractElement>();
-  uint8_t OpSize = IROp->Size;
-  switch (OpSize) {
+  switch (Op->Header.Size) {
    case 1:
      mov(GetDst(Node).B(), GetSrc(Op->Header.Args[0].ID()).V16B(), Op->Index);
    break;
@@ -1772,7 +1763,7 @@ DEF_OP(VExtractElement) {
    case 8:
      mov(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Index);
    break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled VExtractElement element size: {}", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled VExtractElement element size: {}", Op->Header.Size);
  }
 }

@@ -2318,13 +2309,27 @@ DEF_OP(VTBL1) {
  }
 }

+DEF_OP(VRev64) {
+  auto Op = IROp->C<IR::IROp_VRev64>();
+  uint8_t OpSize = IROp->Size;
+  uint8_t Elements = OpSize / Op->Header.ElementSize;
+  // Vector
+  switch (Op->Header.ElementSize) {
+    case 1:
+    case 2:
+    case 4:
+      rev64(GetDst(Node).VCast(OpSize * 8, Elements), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements));
+      break;
+    case 8:
+    default: LOGMAN_MSG_A_FMT("Invalid Element Size: {}", Op->Header.ElementSize); break;
+  }
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterVectorHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
  REGISTER_OP(VECTORZERO,        VectorZero);
  REGISTER_OP(VECTORIMM,         VectorImm);
-  REGISTER_OP(CREATEVECTOR2,     CreateVector2);
-  REGISTER_OP(CREATEVECTOR4,     CreateVector4);
  REGISTER_OP(SPLATVECTOR2,      SplatVector2);
  REGISTER_OP(SPLATVECTOR4,      SplatVector4);
  REGISTER_OP(VMOV,              VMov);
@@ -2413,6 +2418,7 @@ void Arm64JITCore::RegisterVectorHandlers() {
  REGISTER_OP(VSMULL2,           VSMull2);
  REGISTER_OP(VUABDL,            VUABDL);
  REGISTER_OP(VTBL1,             VTBL1);
+  REGISTER_OP(VREV64,            VRev64);
 #undef REGISTER_OP
 }
 }
@@ -16,8 +16,11 @@ class CPUBackend;
 [[nodiscard]] std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx,
                                                           FEXCore::Core::InternalThreadState *Thread,
                                                           bool CompileThread);
+void InitializeX86JITSignalHandlers(FEXCore::Context::Context *CTX);

 [[nodiscard]] std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx,
                                                             FEXCore::Core::InternalThreadState *Thread,
                                                             bool CompileThread);
+void InitializeArm64JITSignalHandlers(FEXCore::Context::Context *CTX);
+
 } // namespace FEXCore::CPU
@@ -20,11 +20,11 @@ namespace FEXCore::CPU {
 #define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
 #define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(TruncElementPair) {
  auto Op = IROp->C<IR::IROp_TruncElementPair>();

-  switch (Op->Size) {
+  switch (IROp->Size) {
    case 4: {
      auto Dst = GetSrcPair<RA_32>(Node);
      auto Src = GetSrcPair<RA_32>(Op->Header.Args[0].ID());
@@ -32,7 +32,7 @@ DEF_OP(TruncElementPair) {
      mov(Dst.second, Src.second);
      break;
    }
-    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", IROp->Size); break;
  }
 }

@@ -45,7 +45,13 @@ DEF_OP(EntrypointOffset) {
  auto Op = IROp->C<IR::IROp_EntrypointOffset>();

  auto Constant = Entry + Op->Offset;
-  mov(GetDst<RA_64>(Node), Constant);
+  uint64_t Mask = ~0ULL;
+  uint8_t OpSize = IROp->Size;
+  if (OpSize == 4) {
+    Mask = 0xFFFF'FFFFULL;
+  }
+
+  mov(GetDst<RA_64>(Node), Constant & Mask);
 }

 DEF_OP(InlineConstant) {
@@ -671,6 +677,36 @@ DEF_OP(Extr) {
  }
 }

+DEF_OP(PDep) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const auto Input = GRS(Op->Args(0).ID());
+  const auto Mask  = GRS(Op->Args(1).ID());
+  const auto Dest  = GRD(Node);
+
+  if (OpSize == 4) {
+    pdep(Dest.cvt32(), Input.cvt32(), Mask.cvt32());
+  } else {
+    pdep(Dest.cvt64(), Input.cvt64(), Mask.cvt64());
+  }
+}
+
+DEF_OP(PExt) {
+  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto OpSize = IROp->Size;
+
+  const auto Input = GRS(Op->Args(0).ID());
+  const auto Mask  = GRS(Op->Args(1).ID());
+  const auto Dest  = GRD(Node);
+
+  if (OpSize == 4) {
+    pext(Dest.cvt32(), Input.cvt32(), Mask.cvt32());
+  } else {
+    pext(Dest.cvt64(), Input.cvt64(), Mask.cvt64());
+  }
+}
+
 DEF_OP(LDiv) {
  auto Op = IROp->C<IR::IROp_LDiv>();
  uint8_t OpSize = IROp->Size;
@@ -1114,19 +1150,19 @@ DEF_OP(VExtractToGPR) {

  switch (Op->Header.ElementSize) {
    case 1: {
-      pextrb(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
+      pextrb(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Index);
    break;
    }
    case 2: {
-      pextrw(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
+      pextrw(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Index);
    break;
    }
    case 4: {
-      pextrd(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
+      pextrd(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Index);
    break;
    }
    case 8: {
-      pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
+      pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Index);
    break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
@@ -1248,6 +1284,8 @@ void X86JITCore::RegisterALUHandlers() {
  REGISTER_OP(ASHR,              Ashr);
  REGISTER_OP(ROR,               Ror);
  REGISTER_OP(EXTR,              Extr);
+  REGISTER_OP(PDEP,              PDep);
+  REGISTER_OP(PEXT,              PExt);
  REGISTER_OP(LDIV,              LDiv);
  REGISTER_OP(LUDIV,             LUDiv);
  REGISTER_OP(LREM,              LRem);
@@ -15,23 +15,19 @@ $end_info$
 #include <xbyak/xbyak.h>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(CASPair) {
  auto Op = IROp->C<IR::IROp_CAS>();
-  uint8_t OpSize = IROp->Size;

-  // Args[0]: Desired
-  // Args[1]: Expected
-  // Args[2]: Pointer
  // DataSrc = *Src1
  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
  // This will write to memory! Careful!
  // Third operand must be a calculated guest memory address
  //OrderedNode *CASResult = _CAS(Src3, Src2, Src1);
  auto Dst = GetSrcPair<RA_64>(Node);
-  auto Expected = GetSrcPair<RA_64>(Op->Header.Args[0].ID());
-  auto Desired = GetSrcPair<RA_64>(Op->Header.Args[1].ID());
-  auto MemSrc = GetSrc<RA_64>(Op->Header.Args[2].ID());
+  auto Expected = GetSrcPair<RA_64>(Op->Expected.ID());
+  auto Desired = GetSrcPair<RA_64>(Op->Desired.ID());
+  auto MemSrc = GetSrc<RA_64>(Op->Addr.ID());

  Xbyak::Reg MemReg = MemSrc;

@@ -47,7 +43,7 @@ DEF_OP(CASPair) {

  lock();

-  switch (OpSize) {
+  switch (IROp->ElementSize) {
    case 4: {
      cmpxchg8b(dword [MemReg]);
      // EDX:EAX now contains the result
@@ -62,7 +58,7 @@ DEF_OP(CASPair) {
      mov(Dst.second, rdx);
    break;
    }
-    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
  }
 }

@@ -70,18 +66,15 @@ DEF_OP(CAS) {
  auto Op = IROp->C<IR::IROp_CAS>();
  uint8_t OpSize = IROp->Size;

-  // Args[0]: Desired
-  // Args[1]: Expected
-  // Args[2]: Pointer
  // DataSrc = *Src1
  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
  // This will write to memory! Careful!
  // Third operand must be a calculated guest memory address
  //OrderedNode *CASResult = _CAS(Src3, Src2, Src1);

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[2].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());

-  mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov(rax, GetSrc<RA_64>(Op->Expected.ID()));

  // RCX now contains pointer
  // RAX contains our expected value
@@ -90,23 +83,23 @@ DEF_OP(CAS) {
  lock();
  switch (OpSize) {
  case 1: {
-    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Desired.ID()));
    movzx(GetDst<RA_64>(Node), al);
  break;
  }
  case 2: {
-    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Desired.ID()));
    movzx(GetDst<RA_64>(Node), ax);
  break;
  }
  case 4: {
-    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Desired.ID()));
    // RAX now contains the result
    mov (GetDst<RA_64>(Node), eax);
  break;
  }
  case 8: {
-    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Desired.ID()));
    // RAX now contains the result
    mov (GetDst<RA_64>(Node), rax);
  break;
@@ -118,21 +111,21 @@ DEF_OP(CAS) {
 DEF_OP(AtomicAdd) {
  auto Op = IROp->C<IR::IROp_AtomicAdd>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());

  lock();
  switch (IROp->Size) {
    case 1:
-      add(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      add(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
      break;
    case 2:
-      add(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      add(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
      break;
    case 4:
-      add(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      add(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
      break;
    case 8:
-      add(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      add(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
      break;
    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
  }
@@ -141,20 +134,20 @@ DEF_OP(AtomicAdd) {
 DEF_OP(AtomicSub) {
  auto Op = IROp->C<IR::IROp_AtomicSub>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  lock();
  switch (IROp->Size) {
    case 1:
-      sub(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      sub(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
      break;
    case 2:
-      sub(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      sub(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
      break;
    case 4:
-      sub(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      sub(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
      break;
    case 8:
-      sub(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      sub(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
      break;
    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
  }
@@ -163,20 +156,20 @@ DEF_OP(AtomicSub) {
 DEF_OP(AtomicAnd) {
  auto Op = IROp->C<IR::IROp_AtomicAnd>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  lock();
  switch (IROp->Size) {
    case 1:
-      and_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      and_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
      break;
    case 2:
-      and_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      and_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
      break;
    case 4:
-      and_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      and_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
      break;
    case 8:
-      and_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      and_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
      break;
    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
  }
@@ -185,20 +178,20 @@ DEF_OP(AtomicAnd) {
 DEF_OP(AtomicOr) {
  auto Op = IROp->C<IR::IROp_AtomicOr>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  lock();
  switch (IROp->Size) {
    case 1:
-      or_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      or_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
      break;
    case 2:
-      or_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      or_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
      break;
    case 4:
-      or_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      or_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
      break;
    case 8:
-      or_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      or_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
      break;
    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
  }
@@ -207,20 +200,20 @@ DEF_OP(AtomicOr) {
 DEF_OP(AtomicXor) {
  auto Op = IROp->C<IR::IROp_AtomicXor>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  lock();
  switch (IROp->Size) {
    case 1:
-      xor_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      xor_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
      break;
    case 2:
-      xor_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      xor_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
      break;
    case 4:
-      xor_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      xor_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
      break;
    case 8:
-      xor_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      xor_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
      break;
    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
  }
@@ -230,26 +223,26 @@ DEF_OP(AtomicSwap) {
  auto Op = IROp->C<IR::IROp_AtomicSwap>();

  Xbyak::Reg MemReg = rax;
-  mov(MemReg, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov(MemReg, GetSrc<RA_64>(Op->Addr.ID()));

  switch (IROp->Size) {
    case 1:
-      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Value.ID()));
      lock();
      xchg(byte [MemReg], GetDst<RA_8>(Node));
      break;
    case 2:
-      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Value.ID()));
      lock();
      xchg(word [MemReg], GetDst<RA_16>(Node));
      break;
    case 4:
-      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Value.ID()));
      lock();
      xchg(dword [MemReg], GetDst<RA_32>(Node));
      break;
    case 8:
-      mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Value.ID()));
      lock();
      xchg(qword [MemReg], GetDst<RA_64>(Node));
      break;
@@ -260,28 +253,28 @@ DEF_OP(AtomicSwap) {
 DEF_OP(AtomicFetchAdd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  switch (IROp->Size) {
    case 1:
-      movzx(rcx, GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_8>(Op->Value.ID()));
      lock();
      xadd(byte [MemReg], cl);
      movzx(GetDst<RA_32>(Node), cl);
      break;
    case 2:
-      movzx(rcx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_16>(Op->Value.ID()));
      lock();
      xadd(word [MemReg], cx);
      movzx(GetDst<RA_32>(Node), cx);
      break;
    case 4:
-      mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(ecx, GetSrc<RA_32>(Op->Value.ID()));
      lock();
      xadd(dword [MemReg], ecx);
      mov(GetDst<RA_64>(Node), ecx);
      break;
    case 8:
-      mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      mov(rcx, GetSrc<RA_64>(Op->Value.ID()));
      lock();
      xadd(qword [MemReg], rcx);
      mov(GetDst<RA_64>(Node), rcx);
@@ -293,31 +286,31 @@ DEF_OP(AtomicFetchAdd) {
 DEF_OP(AtomicFetchSub) {
  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  switch (IROp->Size) {
    case 1:
-      mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      mov(cl, GetSrc<RA_8>(Op->Value.ID()));
      neg(cl);
      lock();
      xadd(byte [MemReg], cl);
      movzx(GetDst<RA_32>(Node), cl);
      break;
    case 2:
-      mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      mov(cx, GetSrc<RA_16>(Op->Value.ID()));
      neg(cx);
      lock();
      xadd(word [MemReg], cx);
      movzx(GetDst<RA_32>(Node), cx);
      break;
    case 4:
-      mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(ecx, GetSrc<RA_32>(Op->Value.ID()));
      neg(ecx);
      lock();
      xadd(dword [MemReg], ecx);
      mov(GetDst<RA_32>(Node), ecx);
      break;
    case 8:
-      mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      mov(rcx, GetSrc<RA_64>(Op->Value.ID()));
      neg(rcx);
      lock();
      xadd(qword [MemReg], rcx);
@@ -331,7 +324,7 @@ DEF_OP(AtomicFetchAnd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();

  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());

  switch (IROp->Size) {
    case 1: {
@@ -341,7 +334,7 @@ DEF_OP(AtomicFetchAnd) {
      L(Loop);
      mov(TMP2.cvt8(), TMP1.cvt8());
      mov(TMP3.cvt8(), TMP1.cvt8());
-      and_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -357,7 +350,7 @@ DEF_OP(AtomicFetchAnd) {
      L(Loop);
      mov(TMP2.cvt16(), TMP1.cvt16());
      mov(TMP3.cvt16(), TMP1.cvt16());
-      and_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -374,7 +367,7 @@ DEF_OP(AtomicFetchAnd) {
      L(Loop);
      mov(TMP2.cvt32(), TMP1.cvt32());
      mov(TMP3.cvt32(), TMP1.cvt32());
-      and_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -391,7 +384,7 @@ DEF_OP(AtomicFetchAnd) {
      L(Loop);
      mov(TMP2.cvt64(), TMP1.cvt64());
      mov(TMP3.cvt64(), TMP1.cvt64());
-      and_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -409,7 +402,7 @@ DEF_OP(AtomicFetchOr) {
  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();

  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  switch (IROp->Size) {
    case 1: {
      mov(TMP1.cvt8(), byte [MemReg]);
@@ -418,7 +411,7 @@ DEF_OP(AtomicFetchOr) {
      L(Loop);
      mov(TMP2.cvt8(), TMP1.cvt8());
      mov(TMP3.cvt8(), TMP1.cvt8());
-      or_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -434,7 +427,7 @@ DEF_OP(AtomicFetchOr) {
      L(Loop);
      mov(TMP2.cvt16(), TMP1.cvt16());
      mov(TMP3.cvt16(), TMP1.cvt16());
-      or_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -451,7 +444,7 @@ DEF_OP(AtomicFetchOr) {
      L(Loop);
      mov(TMP2.cvt32(), TMP1.cvt32());
      mov(TMP3.cvt32(), TMP1.cvt32());
-      or_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -468,7 +461,7 @@ DEF_OP(AtomicFetchOr) {
      L(Loop);
      mov(TMP2.cvt64(), TMP1.cvt64());
      mov(TMP3.cvt64(), TMP1.cvt64());
-      or_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -486,7 +479,7 @@ DEF_OP(AtomicFetchXor) {
  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();

  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  switch (IROp->Size) {
    case 1: {
      mov(TMP1.cvt8(), byte [MemReg]);
@@ -495,7 +488,7 @@ DEF_OP(AtomicFetchXor) {
      L(Loop);
      mov(TMP2.cvt8(), TMP1.cvt8());
      mov(TMP3.cvt8(), TMP1.cvt8());
-      xor_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -511,7 +504,7 @@ DEF_OP(AtomicFetchXor) {
      L(Loop);
      mov(TMP2.cvt16(), TMP1.cvt16());
      mov(TMP3.cvt16(), TMP1.cvt16());
-      xor_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -528,7 +521,7 @@ DEF_OP(AtomicFetchXor) {
      L(Loop);
      mov(TMP2.cvt32(), TMP1.cvt32());
      mov(TMP3.cvt32(), TMP1.cvt32());
-      xor_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -545,7 +538,7 @@ DEF_OP(AtomicFetchXor) {
      L(Loop);
      mov(TMP2.cvt64(), TMP1.cvt64());
      mov(TMP3.cvt64(), TMP1.cvt64());
-      xor_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));

      // Updates RAX with the value from memory
      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -562,7 +555,7 @@ DEF_OP(AtomicFetchXor) {
 DEF_OP(AtomicFetchNeg) {
  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();

-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
  switch (IROp->Size) {
    case 1: {
      mov(TMP1.cvt8(), byte [MemReg]);
@@ -28,7 +28,7 @@ $end_info$
 #include <xbyak/xbyak.h>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GuestCallDirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }
@@ -37,18 +37,13 @@ DEF_OP(GuestCallIndirect) {
  LogMan::Msg::DFmt("Unimplemented");
 }

-DEF_OP(GuestReturn) {
-  LogMan::Msg::DFmt("Unimplemented");
-}
-
 DEF_OP(SignalReturn) {
  // Adjust the stack first for a regular return
  if (SpillSlots) {
    add(rsp, SpillSlots * 16); // + 8 to consume return address
  }

-  mov(TMP1, ThreadSharedData.SignalHandlerReturnAddress);
-  jmp(TMP1);
+  jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.SignalReturnHandler)]);
 }

 DEF_OP(CallbackReturn) {
@@ -58,8 +53,7 @@ DEF_OP(CallbackReturn) {
  }

  // Make sure to adjust the refcounter so we don't clear the cache now
-  mov(rax, reinterpret_cast<uint64_t>(ThreadSharedData.SignalHandlerRefCounterPtr));
-  sub(dword [rax], 1);
+  sub(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.SignalHandlerRefCountPointer)], 1);

  // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
  add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 8);
@@ -104,7 +98,8 @@ DEF_OP(ExitFunction) {
    Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());

    // L1 Cache
-    mov(rcx, ThreadState->LookupCache->GetL1Pointer());
+    mov(rcx, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.L1Pointer)]);
+
    mov(rax, RipReg);

    and_(rax, LookupCache::L1_ENTRIES_MASK);
@@ -117,9 +112,8 @@ DEF_OP(ExitFunction) {
    jmp(qword[LookupBase + 0]);

    L(FullLookup);
-    mov(rax, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], RipReg);
-    jmp(rax);
+    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.DispatcherLoopTop)]);
  }

 #ifdef BLOCKSTATS
@@ -128,18 +122,10 @@ DEF_OP(ExitFunction) {
 }

 DEF_OP(Jump) {
-  auto Op = IROp->C<IR::IROp_Jump>();
+  const auto Op = IROp->C<IR::IROp_Jump>();
+  const auto ArgID = Op->Args(0).ID();

-  Label *TargetLabel;
-  auto IsTarget = JumpTargets.find(Op->Header.Args[0].ID());
-  if (IsTarget == JumpTargets.end()) {
-    TargetLabel = &JumpTargets.try_emplace(Op->Header.Args[0].ID()).first->second;
-  }
-  else {
-    TargetLabel = &IsTarget->second;
-  }
-
-  PendingTargetLabel = TargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(ArgID).first->second;
 }

 #define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
@@ -147,18 +133,7 @@ DEF_OP(Jump) {
 DEF_OP(CondJump) {
  auto Op = IROp->C<IR::IROp_CondJump>();

-  Label *TrueTargetLabel;
-  Label *FalseTargetLabel;
-
-  auto TrueIter = JumpTargets.find(Op->TrueBlock.ID());
-  auto FalseIter = JumpTargets.find(Op->FalseBlock.ID());
-
-  if (TrueIter == JumpTargets.end()) {
-    TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-  }
-  else {
-    TrueTargetLabel = &TrueIter->second;
-  }
+  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;

  if (IsGPR(Op->Cmp1.ID())) {
    uint64_t Const;
@@ -168,24 +143,18 @@ DEF_OP(CondJump) {
      cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
    }
  } else if (IsFPR(Op->Cmp1.ID())) {
-    if (Op->CompareSize  == 4)
+    if (Op->CompareSize == 4) {
      ucomiss(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
-    else
+    } else {
      ucomisd(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
+    }
  }

  auto [_, __, JCC] = GetCC(Op->Cond);

  (this->*JCC)(*TrueTargetLabel, T_NEAR);

-  if (FalseIter == JumpTargets.end()) {
-    FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-  }
-  else {
-    FalseTargetLabel = &FalseIter->second;
-  }
-
-  PendingTargetLabel = FalseTargetLabel;
+  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
 }

 DEF_OP(Syscall) {
@@ -212,15 +181,13 @@ DEF_OP(Syscall) {
  }

  mov(rsi, STATE); // Move thread in to rsi
-  mov(rdi, reinterpret_cast<uint64_t>(CTX->SyscallHandler));
+  mov(rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.SyscallHandlerObj)]);
  mov(rdx, rsp);

-  mov(rax, reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall));
-
  if (NumPush & 1)
    sub(rsp, 8); // Align
  // {rdi, rsi, rdx}
-  call(rax);
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.SyscallHandlerFunc)]);

  if (NumPush & 1)
    add(rsp, 8); // Align
@@ -305,9 +272,7 @@ DEF_OP(RemoveCodeEntry) {
  mov(rax, Entry); // imm64 move
  mov(rsi, rax);

-
-  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
-  call(rax);
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.RemoveCodeEntryFromJIT)]);

  if (NumPush & 1)
    add(rsp, 8); // Align
@@ -319,13 +284,6 @@ DEF_OP(RemoveCodeEntry) {
 DEF_OP(CPUID) {
  auto Op = IROp->C<IR::IROp_CPUID>();

-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function, uint32_t Leaf);
-  union {
-    ClassPtrType ClassPtr;
-    uint64_t Raw;
-  } Ptr;
-  Ptr.ClassPtr = &CPUIDEmu::RunFunction;
-
  for (auto &Reg : RA64)
    push(Reg);

@@ -338,18 +296,15 @@ DEF_OP(CPUID) {
  // rsi can be in the source registers, so copy argument to edx first
  mov (edx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
  mov (esi, GetSrc<RA_32>(Op->Header.Args[0].ID()));
-  mov (rdi, reinterpret_cast<uint64_t>(&CTX->CPUID));
+  mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.CPUIDObj)]);

  auto NumPush = RA64.size();

  if (NumPush & 1)
    sub(rsp, 8); // Align

-  mov(rax, Ptr.Raw);
-
  // {rdi, rsi, rdx}
-
-  call(rax);
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.CPUIDFunction)]);

  if (NumPush & 1)
    add(rsp, 8); // Align
@@ -367,7 +322,6 @@ void X86JITCore::RegisterBranchHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
  REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
  REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
-  REGISTER_OP(GUESTRETURN,       GuestReturn);
  REGISTER_OP(SIGNALRETURN,      SignalReturn);
  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
  REGISTER_OP(EXITFUNCTION,      ExitFunction);
@@ -15,26 +15,26 @@ $end_info$

 namespace FEXCore::CPU {

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VInsGPR) {
  auto Op = IROp->C<IR::IROp_VInsGPR>();
-  movapd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+  movapd(GetDst(Node), GetSrc(Op->DestVector.ID()));

  switch (Op->Header.ElementSize) {
    case 1: {
-      pinsrb(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()), Op->Index);
+      pinsrb(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()), Op->DestIdx);
      break;
    }
    case 2: {
-      pinsrw(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()), Op->Index);
+      pinsrw(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()), Op->DestIdx);
      break;
    }
    case 4: {
-      pinsrd(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()), Op->Index);
+      pinsrd(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()), Op->DestIdx);
      break;
    }
    case 8: {
-      pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()), Op->Index);
+      pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()), Op->DestIdx);
      break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
@@ -13,7 +13,7 @@ $end_info$
 #include <xbyak/xbyak.h>

 namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(AESImc) {
  auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -45,6 +45,36 @@ DEF_OP(AESKeyGenAssist) {
  vaeskeygenassist(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), Op->RCON);
 }

+DEF_OP(CRC32) {
+  auto Op = IROp->C<IR::IROp_CRC32>();
+  switch (IROp->Size) {
+  case 4:
+    mov(TMP1, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));
+  break;
+  case 8:
+    mov(TMP1, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  break;
+  default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", IROp->Size);
+  }
+
+  switch (Op->SrcSize) {
+    case 1:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt8());
+      break;
+    case 2:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt16());
+      break;
+    case 4:
+      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt32());
+      break;
+    case 8:
+      crc32(GetDst<RA_64>(Node).cvt64(), TMP1.cvt64());
+      break;
+  }
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterEncryptionHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
@@ -54,7 +84,7 @@ void X86JITCore::RegisterEncryptionHandlers() {
  REGISTER_OP(VAESDEC,     AESDec);
  REGISTER_OP(VAESDECLAST, AESDecLast);
  REGISTER_OP(VAESKEYGENASSIST, AESKeyGenAssist);
-
+  REGISTER_OP(CRC32,             CRC32);
 #undef REGISTER_OP
 }
 }
@@ -14,7 +14,7 @@ $end_info$

 namespace FEXCore::CPU {

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
  auto Op = IROp->C<IR::IROp_GetHostFlag>();

@@ -15,6 +15,8 @@ $end_info$
 #include "Interface/IR/PassManager.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"

+#include "Utils/MemberFunctionToPointer.h"
+
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/SignalDelegator.h>
@@ -27,7 +29,6 @@ $end_info$

 #include <algorithm>
 #include <array>
-#include <bits/types/stack_t.h>
 #include <memory>
 #include <stddef.h>
 #include <stdint.h>
@@ -42,6 +43,16 @@ $end_info$
 // #define DEBUG_RA 1
 // #define DEBUG_CYCLES

+namespace {
+static void PrintValue(uint64_t Value) {
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
+}
+
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
+}
+}
+
 namespace FEXCore::CPU {

 CodeBuffer AllocateNewCodeBuffer(FEXCore::Context::Context *CTX, size_t Size) {
@@ -98,7 +109,7 @@ void X86JITCore::PopRegs() {
  add(rsp, 16 * RAXMM_x.size());
 }

-void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
+void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
  FallbackInfo Info;
  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -109,9 +120,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
      case FABI_VOID_U16: {
        PushRegs();
        mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();
        break;
@@ -120,9 +129,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushRegs();

        movss(xmm0, GetSrc(IROp->Args[0].ID()));
-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -136,9 +143,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushRegs();

        movsd(xmm0, GetSrc(IROp->Args[0].ID()));
-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -153,9 +158,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        PushRegs();

        mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -171,9 +174,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -187,9 +188,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -203,9 +202,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -218,9 +215,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -233,9 +228,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -251,9 +244,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdx, GetSrc(IROp->Args[1].ID()));
        pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -266,9 +257,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdi, GetSrc(IROp->Args[0].ID()));
        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -286,9 +275,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
        movq(rdx, GetSrc(IROp->Args[1].ID()));
        pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1);

-        mov(rax, (uintptr_t)Info.fn);
-
-        call(rax);
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.FallbackHandlerPointers[Info.HandlerIndex])]);

        PopRegs();

@@ -308,7 +295,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
  }
 }

-void X86JITCore::Op_NoOp(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
+void X86JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
 }

 X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread)
@@ -318,6 +305,7 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
  , InitialCodeBuffer {Buffer}
 {
  CurrentCodeBuffer = &InitialCodeBuffer;
+  EmitDetectionString();

  RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");

@@ -350,6 +338,7 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
    DispatcherConfig config;
    config.ExitFunctionLink = reinterpret_cast<uintptr_t>(&ExitFunctionLink);
    config.ExitFunctionLinkThis = reinterpret_cast<uintptr_t>(this);
+    config.StaticRegisterAssignment = ctx->Config.StaticRegisterAllocation;

    Dispatcher = std::make_unique<X86Dispatcher>(CTX, ThreadState, config);
    DispatchPtr = Dispatcher->DispatchPtr;
@@ -357,27 +346,55 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh

    ThreadSharedData.SignalHandlerRefCounterPtr = &Dispatcher->SignalHandlerRefCounter;
    ThreadSharedData.SignalHandlerReturnAddress = Dispatcher->SignalHandlerReturnAddress;
+    ThreadSharedData.UnimplementedInstructionAddress = Dispatcher->UnimplementedInstructionAddress;
+    ThreadSharedData.OverflowExceptionInstructionAddress = Dispatcher->OverflowExceptionInstructionAddress;
+
    ThreadSharedData.Dispatcher = Dispatcher.get();
+  }

-    // This will register the host signal handler per thread, which is fine
-    CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleSIGILL(Signal, info, ucontext);
-    }, true);
+  {
+    // Set up pointers that the JIT needs to load
+    auto &Pointers = ThreadState->CurrentFrame->Pointers.X86;
+    // Process specific
+    Pointers.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
+    Pointers.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
+    Pointers.RemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit);
+    Pointers.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);

-    CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
-    }, true);
-
-    auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
-      X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
-      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-    };
-
-    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
-      CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction);
+      Pointers.CPUIDFunction = PMF.GetConvertedPointer();
    }
+
+    Pointers.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
+    Pointers.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
+
+    // Fill in the fallback handlers
+    InterpreterOps::FillFallbackIndexPointers(Pointers.FallbackHandlerPointers);
+
+    // Thread Specific
+    Pointers.SignalHandlerRefCountPointer = reinterpret_cast<uint64_t>(&Dispatcher->SignalHandlerRefCounter);
+  }
+}
+
+void X86JITCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
+  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleSIGILL(Signal, info, ucontext);
+  }, true);
+
+  CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
+    X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
+  }, true);
+
+  auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
+    X86JITCore *Core = reinterpret_cast<X86JITCore*>(Thread->CPUBackend.get());
+    return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+  };
+
+  for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
+    CTX->SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
  }
 }

@@ -391,6 +408,13 @@ X86JITCore::~X86JITCore() {
  FreeCodeBuffer(InitialCodeBuffer);
 }

+void X86JITCore::EmitDetectionString() {
+  const char JITString[] = "FEXJIT::X86JITCore::";
+  for (char c : JITString) {
+    db(c);
+  }
+}
+
 void X86JITCore::ClearCache() {
  if (*ThreadSharedData.SignalHandlerRefCounterPtr == 0) {
    if (!CodeBuffers.empty()) {
@@ -429,9 +453,11 @@ void X86JITCore::ClearCache() {
    EmplaceNewCodeBuffer(NewCodeBuffer);
    setNewBuffer(NewCodeBuffer.Ptr, NewCodeBuffer.Size);
  }
+
+  EmitDetectionString();
 }

-IR::PhysicalRegister X86JITCore::GetPhys(uint32_t Node) const {
+IR::PhysicalRegister X86JITCore::GetPhys(IR::NodeID Node) const {
  auto PhyReg = RAData->GetNodeRegister(Node);

  LOGMAN_THROW_A_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
@@ -439,16 +465,16 @@ IR::PhysicalRegister X86JITCore::GetPhys(uint32_t Node) const {
  return PhyReg;
 }

-bool X86JITCore::IsFPR(uint32_t Node) const {
+bool X86JITCore::IsFPR(IR::NodeID Node) const {
  return RAData->GetNodeRegister(Node).Class == IR::FPRClass.Val;
 }

-bool X86JITCore::IsGPR(uint32_t Node) const {
+bool X86JITCore::IsGPR(IR::NodeID Node) const {
  return RAData->GetNodeRegister(Node).Class == IR::GPRClass.Val;
 }

 template<uint8_t RAType>
-Xbyak::Reg X86JITCore::GetSrc(uint32_t Node) const {
+Xbyak::Reg X86JITCore::GetSrc(IR::NodeID Node) const {
  // rax, rcx, rdx, rsi, r8, r9,
  // r10
  // Callee Saved
@@ -467,24 +493,24 @@ Xbyak::Reg X86JITCore::GetSrc(uint32_t Node) const {
 }

 template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_64>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_64>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_32>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_32>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_16>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_16>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_8>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_8>(IR::NodeID Node) const;

-Xbyak::Xmm X86JITCore::GetSrc(uint32_t Node) const {
+Xbyak::Xmm X86JITCore::GetSrc(IR::NodeID Node) const {
  auto PhyReg = GetPhys(Node);
  return RAXMM_x[PhyReg.Reg];
 }

 template<uint8_t RAType>
-Xbyak::Reg X86JITCore::GetDst(uint32_t Node) const {
+Xbyak::Reg X86JITCore::GetDst(IR::NodeID Node) const {
  auto PhyReg = GetPhys(Node);
  if constexpr (RAType == RA_64)
    return RA64[PhyReg.Reg].cvt64();
@@ -499,19 +525,19 @@ Xbyak::Reg X86JITCore::GetDst(uint32_t Node) const {
 }

 template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_64>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_64>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_32>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_32>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_16>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_16>(IR::NodeID Node) const;

 template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_8>(uint32_t Node) const;
+Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_8>(IR::NodeID Node) const;

 template<uint8_t RAType>
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair(uint32_t Node) const {
+std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair(IR::NodeID Node) const {
  auto PhyReg = GetPhys(Node);
  if constexpr (RAType == RA_64)
    return RA64Pair[PhyReg.Reg];
@@ -520,12 +546,12 @@ std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair(uint32_t Node) const {
 }

 template
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_64>(uint32_t Node) const;
+std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_64>(IR::NodeID Node) const;

 template
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_32>(uint32_t Node) const;
+std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_32>(IR::NodeID Node) const;

-Xbyak::Xmm X86JITCore::GetDst(uint32_t Node) const {
+Xbyak::Xmm X86JITCore::GetDst(IR::NodeID Node) const {
  auto PhyReg = GetPhys(Node);
  return RAXMM_x[PhyReg.Reg];
 }
@@ -550,7 +576,12 @@ bool X86JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, u
  if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
    auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
    if (Value) {
-      *Value = Entry + Op->Offset;
+      uint64_t Mask = ~0ULL;
+      uint8_t OpSize = OpHeader->Size;
+      if (OpSize == 4) {
+        Mask = 0xFFFF'FFFFULL;
+      }
+      *Value = (Entry + Op->Offset) & Mask;
    }
    return true;
  } else {
@@ -687,15 +718,11 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
      LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif

-      uint32_t Node = IR->GetID(BlockNode);
-      auto IsTarget = JumpTargets.find(Node);
-      if (IsTarget == JumpTargets.end()) {
-        IsTarget = JumpTargets.try_emplace(Node).first;
-      }
+      const auto Node = IR->GetID(BlockNode);
+      const auto IsTarget = JumpTargets.try_emplace(Node).first;

      // if there is a pending branch, and it is not fall-through
-      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second)
-      {
+      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second) {
        jmp(*PendingTargetLabel, T_NEAR);
      }
      PendingTargetLabel = nullptr;
@@ -724,10 +751,10 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
          Inst << "\t" << Name << " ";
        }

-        uint8_t NumArgs = IR::GetArgs(IROp->Op);
+        const uint8_t NumArgs = IR::GetArgs(IROp->Op);
        for (uint8_t i = 0; i < NumArgs; ++i) {
-          uint32_t ArgNode = IROp->Args[i].ID();
-          uint64_t PhysReg = RAPass->GetNodeRegister(ArgNode);
+          const auto ArgNode = IROp->Args[i].ID();
+          const uint64_t PhysReg = RAPass->GetNodeRegister(ArgNode);
          if (PhysReg >= GPRPairBase)
            Inst << "Pair" << GetPhys(ArgNode) << (i + 1 == NumArgs ? "" : ", ");
          else if (PhysReg >= XMMBase)
@@ -739,7 +766,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
        LogMan::Msg::DFmt("{}", Inst.str());
      }
      #endif
-      uint32_t ID = IR->GetID(CodeNode);
+      const auto ID = IR->GetID(CodeNode);

      // Execute handler
      OpHandler Handler = OpHandlers[IROp->Op];
@@ -789,4 +816,9 @@ uint64_t X86JITCore::ExitFunctionLink(X86JITCore *core, FEXCore::Core::CpuStateF
 std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
  return std::make_unique<X86JITCore>(ctx, Thread, AllocateNewCodeBuffer(ctx, CompileThread ? X86JITCore::MAX_CODE_SIZE : X86JITCore::INITIAL_CODE_SIZE), CompileThread);
 }
+
+void InitializeX86JITSignalHandlers(FEXCore::Context::Context *CTX) {
+  X86JITCore::InitializeSignalHandlers(CTX);
+}
+
 }
@@ -9,8 +9,6 @@ $end_info$
 #include "Interface/Core/BlockSamplingData.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"

-#include "Common/MathUtils.h"
-
 #define XBYAK64
 #include <xbyak/xbyak.h>
 #include <xbyak/xbyak_util.h>
@@ -20,6 +18,7 @@ using namespace Xbyak;
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/Utils/MathUtils.h>
 #include "Interface/IR/Passes/RegisterAllocationPass.h"

 #include <tuple>
@@ -80,6 +79,12 @@ public:
  static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 256;
  void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;

+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true, bool IncludeCompileService = true) const override {
+    return Dispatcher->IsAddressInJITCode(Address, IncludeDispatcher, IncludeCompileService);
+  }
+
+  static void InitializeSignalHandlers(FEXCore::Context::Context *CTX);
+
 private:
  Label* PendingTargetLabel{};
  FEXCore::Context::Context *CTX;
@@ -88,7 +93,7 @@ private:
  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
  uint64_t Entry;

-  std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, Label> JumpTargets;
+  std::unordered_map<IR::NodeID, Label> JumpTargets;
  Xbyak::util::Cpu Features{};

  bool MemoryDebug = false;
@@ -114,21 +119,21 @@ private:
  constexpr static uint8_t RA_64 = 3;
  constexpr static uint8_t RA_XMM = 4;

-  [[nodiscard]] IR::PhysicalRegister GetPhys(uint32_t Node) const;
+  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const;

-  [[nodiscard]] bool IsFPR(uint32_t Node) const;
-  [[nodiscard]] bool IsGPR(uint32_t Node) const;
+  [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
+  [[nodiscard]] bool IsGPR(IR::NodeID Node) const;

  template<uint8_t RAType>
-  [[nodiscard]] Xbyak::Reg GetSrc(uint32_t Node) const;
+  [[nodiscard]] Xbyak::Reg GetSrc(IR::NodeID Node) const;
  template<uint8_t RAType>
-  [[nodiscard]] std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(uint32_t Node) const;
+  [[nodiscard]] std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(IR::NodeID Node) const;

  template<uint8_t RAType>
-  [[nodiscard]] Xbyak::Reg GetDst(uint32_t Node) const;
+  [[nodiscard]] Xbyak::Reg GetDst(IR::NodeID Node) const;

-  [[nodiscard]] Xbyak::Xmm GetSrc(uint32_t Node) const;
-  [[nodiscard]] Xbyak::Xmm GetDst(uint32_t Node) const;
+  [[nodiscard]] Xbyak::Xmm GetSrc(IR::NodeID Node) const;
+  [[nodiscard]] Xbyak::Xmm GetDst(IR::NodeID Node) const;

  [[nodiscard]] Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset,
                                            IR::MemOffsetType OffsetType, uint8_t OffsetScale) const;
@@ -149,6 +154,9 @@ private:

  static uint64_t ExitFunctionLink(X86JITCore* code, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);

+  // This is purely a debugging aid for developers to see if they are in JIT code space when inspecting raw memory
+  void EmitDetectionString();
+
  // This is the initial code buffer that we will fall back to
  // In a program without signals and code clearing, we will typically
  // only have this code buffer
@@ -163,6 +171,8 @@ private:

  struct CompilerSharedData {
    uint64_t SignalHandlerReturnAddress{};
+    uint64_t UnimplementedInstructionAddress{};
+    uint64_t OverflowExceptionInstructionAddress{};

    uint32_t *SignalHandlerRefCounterPtr{};
    FEXCore::CPU::Dispatcher *Dispatcher{};
@@ -177,8 +187,8 @@ private:

  std::tuple<SetCC, CMovCC, JCC> GetCC(IR::CondClassType cond);

-  using OpHandler = void (X86JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
-  std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
+  using OpHandler = void (X86JITCore::*)(IR::IROp_Header *IROp, IR::NodeID Node);
+  std::array<OpHandler, IR::IROps::OP_LAST + 1> OpHandlers {};
  void RegisterALUHandlers();
  void RegisterAtomicHandlers();
  void RegisterBranchHandlers();
@@ -192,7 +202,7 @@ private:

  void PushRegs();
  void PopRegs();
-#define DEF_OP(x) void Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

  ///< Unhandled handler
  DEF_OP(Unhandled);
@@ -228,6 +238,8 @@ private:
  DEF_OP(Rol);
  DEF_OP(Ror);
  DEF_OP(Extr);
+  DEF_OP(PDep);
+  DEF_OP(PExt);
  DEF_OP(LDiv);
  DEF_OP(LUDiv);
  DEF_OP(LRem);
@@ -269,7 +281,6 @@ private:
  ///< Branch ops
  DEF_OP(GuestCallDirect);
  DEF_OP(GuestCallIndirect);
-  DEF_OP(GuestReturn);
  DEF_OP(SignalReturn);
  DEF_OP(CallbackReturn);
  DEF_OP(ExitFunction);
@@ -310,6 +321,7 @@ private:
  DEF_OP(VLoadMemElement);
  DEF_OP(VStoreMemElement);
  DEF_OP(CacheLineClear);
+  DEF_OP(CacheLineZero);

  ///< Misc ops
  DEF_OP(EndBlock);
@@ -320,6 +332,8 @@ private:
  DEF_OP(Print);
  DEF_OP(GetRoundingMode);
  DEF_OP(SetRoundingMode);
+  DEF_OP(ProcessorID);
+  DEF_OP(RDRAND);

  ///< Move ops
  DEF_OP(ExtractElementPair);
@@ -329,8 +343,6 @@ private:
  ///< Vector ops
  DEF_OP(VectorZero);
  DEF_OP(VectorImm);
-  DEF_OP(CreateVector2);
-  DEF_OP(CreateVector4);
  DEF_OP(SplatVector);
  DEF_OP(VMov);
  DEF_OP(VAnd);
@@ -417,6 +429,7 @@ private:
  DEF_OP(VSMull2);
  DEF_OP(VUABDL);
  DEF_OP(VTBL1);
+  DEF_OP(VRev64);

  ///< Encryption ops
  DEF_OP(AESImc);
@@ -425,6 +438,7 @@ private:
  DEF_OP(AESDec);
  DEF_OP(AESDecLast);
  DEF_OP(AESKeyGenAssist);
+  DEF_OP(CRC32);
 #undef DEF_OP
 };

@@ -17,13 +17,13 @@ $end_info$

 namespace FEXCore::CPU {

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(LoadContext) {
  auto Op = IROp->C<IR::IROp_LoadContext>();
  uint8_t OpSize = IROp->Size;

-  if (Op->Class.Val == 0) {
+  if (Op->Class == IR::GPRClass) {
    switch (OpSize) {
    case 1: {
      movzx(GetDst<RA_32>(Node), byte [STATE + Op->Offset]);
@@ -84,23 +84,23 @@ DEF_OP(StoreContext) {
  auto Op = IROp->C<IR::IROp_StoreContext>();
  uint8_t OpSize = IROp->Size;

-  if (Op->Class.Val == 0) {
+  if (Op->Class == IR::GPRClass) {
    switch (OpSize) {
    case 1: {
-      mov(byte [STATE + Op->Offset], GetSrc<RA_8>(Op->Header.Args[0].ID()));
+      mov(byte [STATE + Op->Offset], GetSrc<RA_8>(Op->Value.ID()));
    }
    break;

    case 2: {
-      mov(word [STATE + Op->Offset], GetSrc<RA_16>(Op->Header.Args[0].ID()));
+      mov(word [STATE + Op->Offset], GetSrc<RA_16>(Op->Value.ID()));
    }
    break;
    case 4: {
-      mov(dword [STATE + Op->Offset], GetSrc<RA_32>(Op->Header.Args[0].ID()));
+      mov(dword [STATE + Op->Offset], GetSrc<RA_32>(Op->Value.ID()));
    }
    break;
    case 8: {
-      mov(qword [STATE + Op->Offset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
+      mov(qword [STATE + Op->Offset], GetSrc<RA_64>(Op->Value.ID()));
    }
    break;
    case 16:
@@ -112,27 +112,27 @@ DEF_OP(StoreContext) {
  else {
    switch (OpSize) {
    case 1: {
-      pextrb(byte [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()), 0);
+      pextrb(byte [STATE + Op->Offset], GetSrc(Op->Value.ID()), 0);
    }
    break;

    case 2: {
-      pextrw(word [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()), 0);
+      pextrw(word [STATE + Op->Offset], GetSrc(Op->Value.ID()), 0);
    }
    break;
    case 4: {
-      vmovd(dword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
+      vmovd(dword [STATE + Op->Offset], GetSrc(Op->Value.ID()));
    }
    break;
    case 8: {
-      vmovq(qword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
+      vmovq(qword [STATE + Op->Offset], GetSrc(Op->Value.ID()));
    }
    break;
    case 16: {
      if (Op->Offset % 16 == 0)
-        movaps(xword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
+        movaps(xword [STATE + Op->Offset], GetSrc(Op->Value.ID()));
      else
-        movups(xword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
+        movups(xword [STATE + Op->Offset], GetSrc(Op->Value.ID()));
    }
    break;
    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
@@ -143,9 +143,9 @@ DEF_OP(StoreContext) {
 DEF_OP(LoadContextIndexed) {
  auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
  size_t size = IROp->Size;
-  Reg index = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  Reg index = GetSrc<RA_64>(Op->Index.ID());

-  if (Op->Class.Val == 0) {
+  if (Op->Class == IR::GPRClass) {
    switch (Op->Stride) {
    case 1:
    case 2:
@@ -245,11 +245,11 @@ DEF_OP(LoadContextIndexed) {

 DEF_OP(StoreContextIndexed) {
  auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
-  Reg index = GetSrc<RA_64>(Op->Header.Args[1].ID());
+  Reg index = GetSrc<RA_64>(Op->Index.ID());
  size_t size = IROp->Size;

-  if (Op->Class.Val == 0) {
-    auto value = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  if (Op->Class == IR::GPRClass) {
+    auto value = GetSrc<RA_64>(Op->Value.ID());
    lea(rax, dword [STATE + Op->BaseOffset]);

    switch (Op->Stride) {
@@ -269,7 +269,7 @@ DEF_OP(StoreContextIndexed) {
    }
  }
  else {
-    auto value = GetSrc(Op->Header.Args[0].ID());
+    auto value = GetSrc(Op->Value.ID());
    switch (Op->Stride) {
    case 1:
    case 2:
@@ -339,19 +339,19 @@ DEF_OP(SpillRegister) {
  if (Op->Class == FEXCore::IR::GPRClass) {
    switch (OpSize) {
      case 1: {
-        mov(byte [rsp + SlotOffset], GetSrc<RA_8>(Op->Header.Args[0].ID()));
+        mov(byte [rsp + SlotOffset], GetSrc<RA_8>(Op->Value.ID()));
        break;
      }
      case 2: {
-        mov(word [rsp + SlotOffset], GetSrc<RA_16>(Op->Header.Args[0].ID()));
+        mov(word [rsp + SlotOffset], GetSrc<RA_16>(Op->Value.ID()));
        break;
      }
      case 4: {
-        mov(dword [rsp + SlotOffset], GetSrc<RA_32>(Op->Header.Args[0].ID()));
+        mov(dword [rsp + SlotOffset], GetSrc<RA_32>(Op->Value.ID()));
        break;
      }
      case 8: {
-        mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
+        mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Value.ID()));
        break;
      }
      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
@@ -359,15 +359,15 @@ DEF_OP(SpillRegister) {
  } else if (Op->Class == FEXCore::IR::FPRClass) {
    switch (OpSize) {
      case 4: {
-        movss(dword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
+        movss(dword [rsp + SlotOffset], GetSrc(Op->Value.ID()));
        break;
      }
      case 8: {
-        movsd(qword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
+        movsd(qword [rsp + SlotOffset], GetSrc(Op->Value.ID()));
        break;
      }
      case 16: {
-        movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
+        movaps(xword [rsp + SlotOffset], GetSrc(Op->Value.ID()));
        break;
      }
      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
@@ -435,7 +435,7 @@ DEF_OP(LoadFlag) {
 DEF_OP(StoreFlag) {
  auto Op = IROp->C<IR::IROp_StoreFlag>();

-  mov (rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov (rax, GetSrc<RA_64>(Op->Value.ID()));
  mov(byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], al);
 }

@@ -469,7 +469,7 @@ DEF_OP(LoadMem) {

  auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);

-  if (Op->Class.Val == 0) {
+  if (Op->Class == IR::GPRClass) {
    auto Dst = GetDst<RA_64>(Node);

    switch (IROp->Size) {
@@ -537,19 +537,19 @@ DEF_OP(StoreMem) {

  auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);

-  if (Op->Class.Val == 0) {
+  if (Op->Class == IR::GPRClass) {
    switch (IROp->Size) {
    case 1:
-      mov(byte [MemPtr], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      mov(byte [MemPtr], GetSrc<RA_8>(Op->Value.ID()));
    break;
    case 2:
-      mov(word [MemPtr], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      mov(word [MemPtr], GetSrc<RA_16>(Op->Value.ID()));
    break;
    case 4:
-      mov(dword [MemPtr], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(dword [MemPtr], GetSrc<RA_32>(Op->Value.ID()));
    break;
    case 8:
-      mov(qword [MemPtr], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      mov(qword [MemPtr], GetSrc<RA_64>(Op->Value.ID()));
    break;
    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", IROp->Size);
    }
@@ -557,22 +557,22 @@ DEF_OP(StoreMem) {
  else {
    switch (IROp->Size) {
    case 1:
-      pextrb(byte [MemPtr], GetSrc(Op->Header.Args[1].ID()), 0);
+      pextrb(byte [MemPtr], GetSrc(Op->Value.ID()), 0);
    break;
    case 2:
-      pextrw(word [MemPtr], GetSrc(Op->Header.Args[1].ID()), 0);
+      pextrw(word [MemPtr], GetSrc(Op->Value.ID()), 0);
    break;
    case 4:
-      vmovd(dword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
+      vmovd(dword [MemPtr], GetSrc(Op->Value.ID()));
    break;
    case 8:
-      vmovq(qword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
+      vmovq(qword [MemPtr], GetSrc(Op->Value.ID()));
    break;
    case 16:
      if (IROp->Size == Op->Align)
-        movups(xword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
+        movups(xword [MemPtr], GetSrc(Op->Value.ID()));
      else
-        movups(xword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
+        movups(xword [MemPtr], GetSrc(Op->Value.ID()));
    break;
    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", IROp->Size);
    }
@@ -595,6 +595,23 @@ DEF_OP(CacheLineClear) {
  clflush(ptr [MemReg]);
 }

+DEF_OP(CacheLineZero) {
+  auto Op = IROp->C<IR::IROp_CacheLineZero>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+
+  // Align by cacheline
+  mov (TMP1, CPUIDEmu::CACHELINE_SIZE - 1);
+  andn(TMP1, TMP1, MemReg.cvt64());
+  xor_(TMP2, TMP2);
+
+  using DataType = uint64_t;
+  // 64-byte cache line zero
+  for (size_t i = 0; i < CPUIDEmu::CACHELINE_SIZE; i += sizeof(DataType)) {
+    mov (qword [TMP1 + i], TMP2);
+  }
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterMemoryHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
@@ -615,6 +632,7 @@ void X86JITCore::RegisterMemoryHandlers() {
  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
+  REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP
 }
 }
@@ -18,15 +18,7 @@ $end_info$
 #include <xbyak/xbyak.h>

 namespace FEXCore::CPU {
-static void PrintValue(uint64_t Value) {
-  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
-}
-
-static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
-}
-
-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

 DEF_OP(Fence) {
  auto Op = IROp->C<IR::IROp_Fence>();
@@ -47,30 +39,24 @@ DEF_OP(Fence) {
 DEF_OP(Break) {
  auto Op = IROp->C<IR::IROp_Break>();
  switch (Op->Reason) {
-    case 0: // Hard fault
-    case 5: // Guest ud2
-      ud2();
-    break;
-    case 1: // Int <imm8>
-      ud2();
-    break;
-    case 2: // overflow
+    case FEXCore::IR::Break_Unimplemented: // Hard fault
+    case FEXCore::IR::Break_Interrupt: // Guest ud2
      ud2();
      break;
-    case 3: // int 1
-      ud2();
+    case FEXCore::IR::Break_Overflow: // overflow
+      // Need to be outside of JIT cache space to ensure cache clearing correctness
+      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.OverflowExceptionHandler)]);
      break;
-    case 4: { // HLT
+    case FEXCore::IR::Break_Halt: { // HLT
      // Time to quit
      // Set our stack to the starting stack location
      mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);

      // Now we need to jump to the thread stop handler
-      mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
-      jmp(TMP1);
+      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.ThreadStopHandler)]);
      break;
    }
-    case 6: // INT3
+    case FEXCore::IR::Break_Interrupt3: // INT3
    {
      if (CTX->GetGdbServerStatus()) {
        // Adjust the stack first for a regular return
@@ -79,8 +65,7 @@ DEF_OP(Break) {
        }

        // This jump target needs to be a constant offset here
-        mov(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddress);
-        jmp(TMP1);
+        jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.ThreadPauseHandler)]);
      }
      else {
        // If we don't have a gdb server attached then....crash?
@@ -88,11 +73,20 @@ DEF_OP(Break) {
        mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);

        // Now we need to jump to the thread stop handler
-        mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
-        jmp(TMP1);
+        jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.ThreadStopHandler)]);
      }
    break;
    }
+    case FEXCore::IR::Break_InvalidInstruction:
+    {
+      if (SpillSlots) {
+        add(rsp, SpillSlots * 16);
+      }
+
+      // Need to be outside of JIT cache space to ensure cache clearing correctness
+      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.UnimplementedInstructionHandler)]);
+      break;
+    }
    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
  }
 }
@@ -136,21 +130,42 @@ DEF_OP(Print) {
  PushRegs();
  if (IsGPR(Op->Header.Args[0].ID())) {
    mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-
-    mov(rax, reinterpret_cast<uintptr_t>(PrintValue));
+    call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.PrintValue)]);
  }
  else {
    pextrq(rdi, GetSrc(Op->Header.Args[0].ID()), 0);
    pextrq(rsi, GetSrc(Op->Header.Args[0].ID()), 1);

-    mov(rax, reinterpret_cast<uintptr_t>(PrintVectorValue));
+    call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.X86.PrintVectorValue)]);
  }

-  call(rax);
-
  PopRegs();
 }

+DEF_OP(ProcessorID) {
+  // Cyclecounter in EDX:EAX
+  // IA32_TSC_AUX in ECX
+  rdtscp();
+  mov (GetDst<RA_32>(Node), ecx);
+}
+
+DEF_OP(RDRAND) {
+  auto Op = IROp->C<IR::IROp_RDRAND>();
+
+  auto Dst = GetSrcPair<RA_64>(Node);
+
+  if (Op->GetReseeded) {
+    rdrand(Dst.first);
+  }
+  else {
+    rdseed(Dst.first);
+  }
+
+  // In the case of RDRAND or RDSEED returning a valid number then CF = 1, else 0
+  mov (Dst.second, 0);
+  setc(Dst.second.cvt8());
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterMiscHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
@@ -167,6 +182,8 @@ void X86JITCore::RegisterMiscHandlers() {
  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
+  REGISTER_OP(PROCESSORID,   ProcessorID);
+  REGISTER_OP(RDRAND, RDRAND);
 #undef REGISTER_OP
 }
 }
@@ -15,7 +15,7 @@ $end_info$

 namespace FEXCore::CPU {

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
  switch (Op->Header.Size) {
@@ -42,7 +42,7 @@ DEF_OP(CreateElementPair) {
  Xbyak::Reg RegSecond;
  Xbyak::Reg RegTmp;

-  switch (Op->Header.Size) {
+  switch (IROp->ElementSize) {
    case 4: {
      Dst = GetSrcPair<RA_32>(Node);
      RegFirst = GetSrc<RA_32>(Op->Header.Args[0].ID());
@@ -16,7 +16,7 @@ $end_info$

 namespace FEXCore::CPU {

-#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VectorZero) {
  auto Dst = GetDst(Node);
  vpxor(Dst, Dst, Dst);
@@ -67,14 +67,6 @@ DEF_OP(VectorImm) {
  }
 }

-DEF_OP(CreateVector2) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(CreateVector4) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
 DEF_OP(SplatVector) {
  auto Op = IROp->C<IR::IROp_SplatVector2>();
  uint8_t OpSize = IROp->Size;
@@ -1545,7 +1537,7 @@ DEF_OP(VInsScalarElement) {
 DEF_OP(VExtractElement) {
  auto Op = IROp->C<IR::IROp_VExtractElement>();

-  switch (Op->Header.ElementSize) {
+  switch (Op->Header.Size) {
    case 1: {
      pextrb(eax, GetSrc(Op->Header.Args[0].ID()), Op->Index);
      pinsrb(GetDst(Node), eax, 0);
@@ -1566,7 +1558,7 @@ DEF_OP(VExtractElement) {
      pinsrq(GetDst(Node), rax, 0);
      break;
    }
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.Size); break;
  }
 }

@@ -2151,13 +2143,79 @@ DEF_OP(VTBL1) {
  }
 }

+DEF_OP(VRev64) {
+  auto Op = IROp->C<IR::IROp_VDupElement>();
+
+  switch (Op->Header.ElementSize) {
+    case 1: {
+      mov(rax, 0x00'01'02'03'04'05'06'07); // Lower
+      vmovq(xmm15, rax);
+      if (IROp->Size == 16) {
+        // Full 8bit byteswap in each 64-bit element
+        mov(rcx, 0x08'09'0A'0B'0C'0D'0E'0F); // Upper
+        pinsrq(xmm15, rcx, 1);
+      }
+      else {
+        // 8byte, upper bits get zero
+        // Full 8bit byteswap in each 64-bit element
+        mov(rcx, 0x80'80'80'80'80'80'80'80); // Upper
+        pinsrq(xmm15, rcx, 1);
+      }
+
+      vpshufb(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), xmm15);
+      break;
+    }
+    case 2: {
+      // Full 16-bit byteswap in each 64-bit element
+      mov(rax, 0x01'00'03'02'05'04'07'06); // Lower
+      vmovq(xmm15, rax);
+      if (IROp->Size == 16) {
+        mov(rcx, 0x09'08'0B'0A'0D'0C'0F'0E); // Upper
+        pinsrq(xmm15, rcx, 1);
+      }
+      else {
+        // 8byte, upper bits get zero
+        // Full 8bit byteswap in each 64-bit element
+        mov(rcx, 0x80'80'80'80'80'80'80'80); // Upper
+        pinsrq(xmm15, rcx, 1);
+      }
+      vpshufb(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), xmm15);
+      break;
+    }
+    case 4: {
+      if (IROp->Size == 16) {
+      vpshufd(GetDst(Node),
+        GetSrc(Op->Header.Args[0].ID()),
+        (0b11 << 0) |
+        (0b10 << 2) |
+        (0b01 << 4) |
+        (0b00 << 6));
+      }
+      else {
+
+      vpshufd(GetDst(Node),
+        GetSrc(Op->Header.Args[0].ID()),
+        (0b01 << 0) |
+        (0b00 << 2) |
+        (0b11 << 4) | // Last two don't matter, will be overwritten with zero
+        (0b11 << 6));
+
+        // Zero upper 64-bits
+        mov(rcx, 0);
+        pinsrq(GetDst(Node), rcx, 1);
+      }
+      break;
+    }
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
+  }
+}
+
+
 #undef DEF_OP
 void X86JITCore::RegisterVectorHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
  REGISTER_OP(VECTORZERO,        VectorZero);
  REGISTER_OP(VECTORIMM,         VectorImm);
-  REGISTER_OP(CREATEVECTOR2,     CreateVector2);
-  REGISTER_OP(CREATEVECTOR4,     CreateVector4);
  REGISTER_OP(SPLATVECTOR2,      SplatVector);
  REGISTER_OP(SPLATVECTOR4,      SplatVector);
  REGISTER_OP(VMOV,              VMov);
@@ -2246,6 +2304,7 @@ void X86JITCore::RegisterVectorHandlers() {
  REGISTER_OP(VSMULL2,           VSMull2);
  REGISTER_OP(VUABDL,            VUABDL);
  REGISTER_OP(VTBL1,             VTBL1);
+  REGISTER_OP(VREV64,            VRev64);
 #undef REGISTER_OP
 }
 }
@@ -37,11 +37,11 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX)
  // We currently limit to 128MB of real memory for caching for the total cache size.
  // Can end up being inefficient if we compile a small number of blocks per page
  PageMemory = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_A(PageMemory != -1ULL, "Failed to allocate page memory");
+  LOGMAN_THROW_A_FMT(PageMemory != -1ULL, "Failed to allocate page memory");

  // L1 Cache
  L1Pointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_A(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
+  LOGMAN_THROW_A_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer");

  VirtualMemSize = ctx->Config.VirtualMemSize;
 }
@@ -50,7 +50,7 @@ public:
    auto InsertPoint =
 #endif
    BlockList.emplace(Address, (uintptr_t)HostCode);
-    LOGMAN_THROW_A(InsertPoint.second == true, "Dupplicate block mapping added");
+    LOGMAN_THROW_A_FMT(InsertPoint.second == true, "Dupplicate block mapping added");

    for (auto CurrentPage = Start >> 12, EndPage = (Start + Length) >> 12; CurrentPage <= EndPage; CurrentPage++) {
      CodePages[CurrentPage].push_back(Address);
@@ -5,6 +5,7 @@

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
+#include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/IR.h>
@@ -13,6 +14,7 @@
 #include <FEXCore/Utils/LogManager.h>

 #include <cstdint>
+#include <fmt/format.h>
 #include <map>
 #include <stddef.h>
 #include <utility>
@@ -26,18 +28,52 @@ class OpDispatchBuilder final : public IREmitter {
 friend class FEXCore::IR::Pass;
 friend class FEXCore::IR::PassManager;

-enum {
-  FLAGS_OP_NONE,  // must rely on x86 flags
-  FLAGS_OP_CMP,   // flags were set by a CMP between flagsOpDest/flagsOpDestSigned and flagsOpSrc/flagsOpSrcSigned with flagsOpSize size
-  FLAGS_OP_AND,   // flags were set by an AND/TEST, flagsOpDest contains the resulting value of flagsOpSize size
-  FLAGS_OP_FCMP,  // flags were set by a ucomis* / comis*
+enum class SelectionFlag {
+  Nothing,  // must rely on x86 flags
+  CMP,      // flags were set by a CMP between flagsOpDest/flagsOpDestSigned and flagsOpSrc/flagsOpSrcSigned with flagsOpSize size
+  AND,      // flags were set by an AND/TEST, flagsOpDest contains the resulting value of flagsOpSize size
+  FCMP,     // flags were set by a ucomis* / comis*
 };

 public:
-  int flagsOp;
-  uint8_t flagsOpSize;
-  OrderedNode* flagsOpDest, *flagsOpSrc;
-  OrderedNode* flagsOpDestSigned, *flagsOpSrcSigned;
+  enum class FlagsGenerationType : uint8_t {
+    TYPE_NONE,
+    TYPE_ADC,
+    TYPE_SBB,
+    TYPE_SUB,
+    TYPE_ADD,
+    TYPE_MUL,
+    TYPE_UMUL,
+    TYPE_LOGICAL,
+    TYPE_LSHL,
+    TYPE_LSHLI,
+    TYPE_LSHR,
+    TYPE_LSHRI,
+    TYPE_ASHR,
+    TYPE_ASHRI,
+    TYPE_ROR,
+    TYPE_RORI,
+    TYPE_ROL,
+    TYPE_ROLI,
+    TYPE_FCMP,
+    TYPE_BEXTR,
+    TYPE_BLSI,
+    TYPE_BLSMSK,
+    TYPE_BLSR,
+    TYPE_POPCOUNT,
+    TYPE_BZHI,
+    TYPE_TZCNT,
+    TYPE_LZCNT,
+    TYPE_BITSELECT,
+    TYPE_RDRAND,
+  };
+
+  SelectionFlag flagsOp{};
+  uint8_t flagsOpSize{};
+  OrderedNode* flagsOpDest{};
+  OrderedNode* flagsOpSrc{};
+  OrderedNode* flagsOpDestSigned{};
+  OrderedNode* flagsOpSrcSigned{};

  FEXCore::Context::Context *CTX{};
  bool ShouldDump {false};
@@ -51,7 +87,7 @@ public:

  OrderedNode* GetNewJumpBlock(uint64_t RIP) {
    auto it = JumpTargets.find(RIP);
-    LOGMAN_THROW_A(it != JumpTargets.end(), "Couldn't find block generated for 0x%lx", RIP);
+    LOGMAN_THROW_A_FMT(it != JumpTargets.end(), "Couldn't find block generated for 0x{:x}", RIP);
    return it->second.BlockEntry;
  }

@@ -69,7 +105,7 @@ public:
  }

  void StartNewBlock() {
-    flagsOp = FLAGS_OP_NONE;
+    flagsOp = SelectionFlag::Nothing;
  }

  bool FinishOp(uint64_t NextRIP, bool LastOp) {
@@ -84,6 +120,9 @@ public:
    //  cmp qword [rdi-8], 0
    //  jne .label
    if (LastOp && !BlockSetRIP) {
+      // Calculate flags first
+      CalculateDeferredFlags();
+
      auto it = JumpTargets.find(NextRIP);
      if (it == JumpTargets.end()) {

@@ -98,6 +137,11 @@ public:
        return true;
      }
    }
+
+    if (LastOp) {
+      LOGMAN_THROW_A_FMT(IsDeferredFlagsStored(), "FinishOp: Deferred flags weren't generated at end of block");
+    }
+
    BlockSetRIP = false;

    return false;
@@ -230,10 +274,12 @@ public:
  void XADDOp(OpcodeArgs);
  void PopcountOp(OpcodeArgs);
  void XLATOp(OpcodeArgs);
+  template<bool Reseed>
+  void RDRANDOp(OpcodeArgs);

-  enum Segment {
-    Segment_FS,
-    Segment_GS,
+  enum class Segment {
+    FS,
+    GS,
  };
  template<Segment Seg>
  void ReadSegmentReg(OpcodeArgs);
@@ -253,9 +299,14 @@ public:
  template<FEXCore::IR::IROps IROp, size_t ElementSize>
  void VectorALUOp(OpcodeArgs);
  template<FEXCore::IR::IROps IROp, size_t ElementSize>
+  void VectorALUROp(OpcodeArgs);
+  template<FEXCore::IR::IROps IROp, size_t ElementSize>
  void VectorScalarALUOp(OpcodeArgs);
  template<FEXCore::IR::IROps IROp, size_t ElementSize, bool Scalar>
  void VectorUnaryOp(OpcodeArgs);
+  template<FEXCore::IR::IROps IROp, size_t ElementSize>
+  void VectorUnaryDuplicateOp(OpcodeArgs);
+
  void MOVQOp(OpcodeArgs);
  template<size_t ElementSize>
  void PADDQOp(OpcodeArgs);
@@ -324,13 +375,24 @@ public:
  template<size_t ElementSize>
  void PSIGN(OpcodeArgs);

-  // BMI Ops
+  // BMI1 Ops
  void ANDNBMIOp(OpcodeArgs);
  void BEXTRBMIOp(OpcodeArgs);
  void BLSIBMIOp(OpcodeArgs);
  void BLSMSKBMIOp(OpcodeArgs);
  void BLSRBMIOp(OpcodeArgs);

+  // BMI2 Ops
+  void BMI2Shift(OpcodeArgs);
+  void BZHI(OpcodeArgs);
+  void MULX(OpcodeArgs);
+  void PDEP(OpcodeArgs);
+  void PEXT(OpcodeArgs);
+  void RORX(OpcodeArgs);
+
+  // ADX Ops
+  void ADXOp(OpcodeArgs);
+
  // X87 Ops
  template<size_t width>
  void FLD(OpcodeArgs);
@@ -431,6 +493,17 @@ public:
  template<size_t ElementSize>
  void ADDSUBPOp(OpcodeArgs);

+  void PFNACCOp(OpcodeArgs);
+  void PFPNACCOp(OpcodeArgs);
+  void PSWAPDOp(OpcodeArgs);
+
+  template<uint8_t CompType>
+  void VPFCMPOp(OpcodeArgs);
+  void PI2FWOp(OpcodeArgs);
+  void PF2IWOp(OpcodeArgs);
+
+  void PMULHRWOp(OpcodeArgs);
+
  void PMADDWD(OpcodeArgs);
  void PMADDUBSW(OpcodeArgs);

@@ -457,6 +530,8 @@ public:
  void FenceOp(OpcodeArgs);

  void StoreFenceOrCLFlush(OpcodeArgs);
+  void CLZeroOp(OpcodeArgs);
+  void RDTSCPOp(OpcodeArgs);

  void PSADBW(OpcodeArgs);

@@ -484,8 +559,12 @@ public:

  void MPSADBWOp(OpcodeArgs);

+  void CRC32(OpcodeArgs);
+
  void UnimplementedOp(OpcodeArgs);

+  void InvalidOp(OpcodeArgs);
+
 #undef OpcodeArgs

  void SetPackedRFLAG(bool Lower8, OrderedNode *Src);
@@ -501,24 +580,35 @@ private:

  OrderedNode *AppendSegmentOffset(OrderedNode *Value, uint32_t Flags, uint32_t DefaultPrefix = 0, bool Override = false);

-  OrderedNode *GetDynamicPC(FEXCore::X86Tables::DecodedOp const& Op, int64_t Offset = 0);
+  OrderedNode *GetRelocatedPC(FEXCore::X86Tables::DecodedOp const& Op, int64_t Offset = 0);
  OrderedNode *LoadSource(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint32_t Flags, int8_t Align, bool LoadData = true, bool ForceLoad = false);
  OrderedNode *LoadSource_WithOpSize(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint8_t OpSize, uint32_t Flags, int8_t Align, bool LoadData = true, bool ForceLoad = false);
  void StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, uint8_t OpSize, int8_t Align);
  void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, int8_t Align);
  void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src, int8_t Align);

-  uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op) const;
-  uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op) const;
+  [[nodiscard]] static uint32_t GPROffset(X86State::X86Reg reg) {
+    LOGMAN_THROW_A_FMT(reg <= X86State::X86Reg::REG_R15, "Invalid reg used");
+    return static_cast<uint32_t>(offsetof(Core::CPUState, gregs[static_cast<size_t>(reg)]));
+  }
+
+  [[nodiscard]] static uint32_t MMBaseOffset() {
+    return static_cast<uint32_t>(offsetof(Core::CPUState, mm[0][0]));
+  }
+
+  [[nodiscard]] uint8_t GetDstSize(X86Tables::DecodedOp Op) const;
+  [[nodiscard]] uint8_t GetSrcSize(X86Tables::DecodedOp Op) const;
+  [[nodiscard]] uint32_t GetDstBitSize(X86Tables::DecodedOp Op) const;
+  [[nodiscard]] uint32_t GetSrcBitSize(X86Tables::DecodedOp Op) const;

  template<unsigned BitOffset>
  void SetRFLAG(OrderedNode *Value) {
-    flagsOp = FLAGS_OP_NONE;
+    flagsOp = SelectionFlag::Nothing;
    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
  }

  void SetRFLAG(OrderedNode *Value, unsigned BitOffset) {
-    flagsOp = FLAGS_OP_NONE;
+    flagsOp = SelectionFlag::Nothing;
    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
  }

@@ -528,32 +618,533 @@ private:

  OrderedNode *SelectCC(uint8_t OP, OrderedNode *TrueValue, OrderedNode *FalseValue);

-  void GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
-  void GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
-  void GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High);
-  void GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High);
-  void GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void GenerateFlags_SignShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  /**
+   * @name Deferred RFLAG calculation and generation.
+   *
+   * Only handles the six flags that ALU ops typically generate.
+   * Specifically: CF, PF, AF, ZF, SF, OF
+   *  These six flags are heavily generated through basic ALU ops and balloon the IR if not early eliminated.
+   *  This tracking structure only tracks single blocks and requires RFLAGS calculation at block-ending ops.
+   *  Some flags generating ALU ops only touch part of the registers, In these cases it will do calculation up front.
+   *  This means we still need our IR passes to eliminate all redundant flags accesses but this light OpcodeDispatcher optimization
+   *  doesn't take it to that level.
+   * @{ */
+
+  // Deferred flag generation tracking structure.
+  // This structure is used to track RFlags from ALU ops for invalidation.
+  //
+  // Future ideas: Use an invalidation mask to do partial generation of flags.
+  // Particularly for the instructions that don't do the full set of flags calculations.
+  // These instructions currently calculate the deferred RFLAGS immediately then overwrite rflags state.
+  // RCLSE IR pass will catch and remove redundant rflags stores like this currently.
+  struct DeferredFlagData {
+    // What type of flags to generate
+    FlagsGenerationType Type {FlagsGenerationType::TYPE_NONE};
+
+    // Source size of the op
+    uint8_t SrcSize;
+
+    // Every flag generation type has a result
+    OrderedNode *Res{};
+
+    union {
+      // UMUL, BEXTR, BLSI, BLSMSK, POPCOUNT, TZCNT, LZCNT, BITSELECT, RDRAND
+      struct {
+      } NoSource;
+
+      // MUL, BLSR, BZHI
+      struct {
+        OrderedNode *Src1;
+      } OneSource;
+
+      // Logical, LSHL, LSHR, ASHR, ROR, ROL
+      struct {
+        OrderedNode *Src1;
+        OrderedNode *Src2;
+      } TwoSource;
+
+      // ADC, SBB
+      struct {
+        OrderedNode *Src1;
+        OrderedNode *Src2;
+        OrderedNode *Src3;
+      } ThreeSource;
+
+      // LSHLI, LSHRI, ASHRI, RORI, ROLI
+      struct {
+        OrderedNode *Src1;
+        uint64_t Imm;
+      } OneSrcImmediate;
+
+      // ADD, SUB
+      struct {
+        OrderedNode *Src1;
+        OrderedNode *Src2;
+
+        bool UpdateCF;
+      } TwoSrcImmediate;
+    } Sources{};
+  };
+
+  DeferredFlagData CurrentDeferredFlags{};
+
+  /**
+   * @brief Takes the current deferred flag state and stores the result in to RFLAGS.
+   *
+   * Once executed there will no longer be any deferred flag state and RFLAGS will have the correct flags in it.
+   * Necessary to do when leaving a IR block, or if an instruction is doing a partial overwrite of the flags.
+   */
+  void CalculateDeferredFlags(uint32_t FlagsToCalculateMask = ~0U);
+
+  /**
+   * @brief Invalidates the current deferred flags structure.
+   *
+   * If the emulated instruction is going to overwrite all of the flags but isn't tracked using the deferred flag system
+   * then use this function to stop tracking the current active deferred flags.
+   */
+  void InvalidateDeferredFlags() {
+    CurrentDeferredFlags.Type = FlagsGenerationType::TYPE_NONE;
+  }
+
+  /**
+   * @brief Checks if there is any deferred flag state active.
+   *
+   * @return True if RFLAGs contains the flags. False if deferred flags is tracking the data.
+   */
+  bool IsDeferredFlagsStored() const {
+    return CurrentDeferredFlags.Type == FlagsGenerationType::TYPE_NONE;
+  }
+
+  /**
+   * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs.
+   * @{ */
+  void CalculcateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
+  void CalculcateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
+  void CalculcateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  void CalculcateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  void CalculcateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High);
+  void CalculcateFlags_UMUL(OrderedNode *High);
+  void CalculcateFlags_Logical(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_ShiftLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_ShiftLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculcateFlags_ShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_ShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculcateFlags_SignShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_SignShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculcateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculcateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculcateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculcateFlags_BEXTR(OrderedNode *Src);
+  void CalculcateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src);
+  void CalculcateFlags_BLSMSK(OrderedNode *Src);
+  void CalculcateFlags_BLSR(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src);
+  void CalculcateFlags_POPCOUNT(OrderedNode *Src);
+  void CalculcateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src);
+  void CalculcateFlags_TZCNT(OrderedNode *Src);
+  void CalculcateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src);
+  void CalculcateFlags_BITSELECT(OrderedNode *Src);
+  void CalculcateFlags_RDRAND(OrderedNode *Src);
+  /**  @} */
+
+  /**
+   * @name These functions generated deferred RFLAGs tracking.
+   *
+   * Depending on the operation it may force a RFLAGs calculation before storing the new deferred state.
+   * @{ */
+  void GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ADC,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .ThreeSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+          .Src3 = CF,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_SBB,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .ThreeSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+          .Src3 = CF,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true) {
+    if (!UpdateCF) {
+      // If we aren't updating CF then we need to calculate flags. Invalidation mask would make this not required.
+      CalculateDeferredFlags();
+    }
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_SUB,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSrcImmediate = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+          .UpdateCF = UpdateCF,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true) {
+    if (!UpdateCF) {
+      // If we aren't updating CF then we need to calculate flags. Invalidation mask would make this not required.
+      CalculateDeferredFlags();
+    }
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ADD,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSrcImmediate = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+          .UpdateCF = UpdateCF,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_MUL,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSource = {
+          .Src1 = High,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_UMUL,
+      .SrcSize = GetSrcSize(Op),
+      .Res = High,
+    };
+  }
+
+  void GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LOGICAL,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    // Flags need to be used, generate incoming flags first.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LSHL,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    // Flags need to be used, generate incoming flags first.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LSHR,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_SignShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    // Flags need to be used, generate incoming flags first.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ASHR,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    // No flags changed if shift is zero.
+    if (Shift == 0) return;
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LSHLI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    // No flags changed if shift is zero.
+    if (Shift == 0) return;
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ASHRI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    // No flags changed if shift is zero.
+    if (Shift == 0) return;
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LSHRI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    // Doesn't set all the flags, needs to calculate.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ROR,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    // Doesn't set all the flags, needs to calculate.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ROL,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    if (Shift == 0) return;
+
+    // Doesn't set all the flags, needs to calculate.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_RORI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    if (Shift == 0) return;
+
+    // Doesn't set all the flags, needs to calculate.
+    CalculateDeferredFlags();
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_ROLI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      }
+    };
+  }
+
+  void GenerateFlags_FCMP(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_FCMP,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .TwoSource = {
+          .Src1 = Src1,
+          .Src2 = Src2,
+        },
+      }
+    };
+  }
+
+  void GenerateFlags_BEXTR(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BEXTR,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_BLSI(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BLSI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_BLSMSK(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BLSMSK,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_BLSR(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BLSR,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSource = {
+          .Src1 = Src,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_POPCOUNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_POPCOUNT,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_BZHI(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Result, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BZHI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Result,
+      .Sources = {
+        .OneSource = {
+          .Src1 = Src,
+        },
+      },
+    };
+  }
+
+  void GenerateFlags_TZCNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_TZCNT,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_LZCNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LZCNT,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_BITSELECT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_BITSELECT,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  void GenerateFlags_RDRAND(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_RDRAND,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Src,
+    };
+  }
+
+  /**  @} */
+  /**  @} */

  OrderedNode * GetX87Top();
-  enum X87Tag {
-    TAG_VALID   = 0b00,
-    TAG_ZERO    = 0b01,
-    TAG_SPECIAL = 0b10,
-    TAG_EMPTY   = 0b11
+  enum class X87Tag {
+    Valid   = 0b00,
+    Zero    = 0b01,
+    Special = 0b10,
+    Empty   = 0b11
  };
-  void SetX87TopTag(OrderedNode *Value, uint32_t Tag);
+  void SetX87TopTag(OrderedNode *Value, X87Tag Tag);
  OrderedNode *GetX87FTW(OrderedNode *Value);
  void SetX87Top(OrderedNode *Value);

@@ -571,24 +1162,37 @@ private:
  bool Multiblock{};
  uint64_t Entry;

-  OrderedNode* _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *ssa0, OrderedNode *ssa1, uint8_t Align = 1) {
+  OrderedNode* _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *Addr, OrderedNode *Value, uint8_t Align = 1) {
    if (CTX->Config.TSOEnabled)
-    	return _StoreMemTSO(ssa0, ssa1, Invalid(), Align, Class, MEM_OFFSET_SXTX, 1, Size);
+      return _StoreMemTSO(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
    else
-      return _StoreMem(ssa0, ssa1, Invalid(), Align, Class, MEM_OFFSET_SXTX, 1, Size);
+      return _StoreMem(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
  }

  OrderedNode* _LoadMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *ssa0, uint8_t Align = 1) {
    if (CTX->Config.TSOEnabled)
-      return _LoadMemTSO(ssa0, Invalid(), Align, Class, MEM_OFFSET_SXTX, 1, Size);
+      return _LoadMemTSO(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
    else
-      return _LoadMem(ssa0, Invalid(), Align, Class, MEM_OFFSET_SXTX, 1, Size);
+      return _LoadMem(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
  }

-
+  void InstallHostSpecificOpcodeHandlers();
 };

 void InstallOpcodeHandlers(Context::OperatingMode Mode);

 }
+template <>
+struct fmt::formatter<FEXCore::IR::OpDispatchBuilder::FlagsGenerationType> : fmt::formatter<int> {
+  using Base = fmt::formatter<int>;
+
+  // Pass-through the underlying value, so IDs can
+  // be formatted like any integral value.
+  template <typename FormatContext>
+  auto format(const FEXCore::IR::OpDispatchBuilder::FlagsGenerationType& ID, FormatContext& ctx) {
+    return Base::format(static_cast<int>(ID), ctx);
+  }
+};
+
+

@@ -53,7 +53,7 @@ void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {

 void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t RCON = Op->Src[1].Data.Literal.Value;

  auto Res = _VAESKeyGenAssist(Src, RCON);
@@ -39,35 +39,229 @@ constexpr std::array<uint32_t, 17> FlagOffsets = {
 };

 void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, OrderedNode *Src) {
-  uint8_t NumFlags = FlagOffsets.size();
+  size_t NumFlags = FlagOffsets.size();
  if (Lower8) {
+    // Calculate flags early.
+    // Could use InvalidateDeferredFlags() if we had masked invalidation.
+    // This is only a partial overwrite of flags since OF isn't stored here.
+    CalculateDeferredFlags();
    NumFlags = 5;
  }
+  else {
+    // We are overwriting all RFLAGS. Invalidate the deferred flag state.
+    InvalidateDeferredFlags();
+  }
+
  auto OneConst = _Constant(1);
-  for (int i = 0; i < NumFlags; ++i) {
-    auto Tmp = _And(_Lshr(Src, _Constant(FlagOffsets[i])), OneConst);
-    SetRFLAG(Tmp, FlagOffsets[i]);
+  for (size_t i = 0; i < NumFlags; ++i) {
+    const auto FlagOffset = FlagOffsets[i];
+    auto Tmp = _And(_Lshr(Src, _Constant(FlagOffset)), OneConst);
+    SetRFLAG(Tmp, FlagOffset);
  }
 }

 OrderedNode *OpDispatchBuilder::GetPackedRFLAG(bool Lower8) {
+  // Calculate flags early.
+  CalculateDeferredFlags();
+
  OrderedNode *Original = _Constant(2);
-  uint8_t NumFlags = FlagOffsets.size();
+  size_t NumFlags = FlagOffsets.size();
  if (Lower8) {
    NumFlags = 5;
  }

-  for (int i = 0; i < NumFlags; ++i) {
-    OrderedNode *Flag = _LoadFlag(FlagOffsets[i]);
+  for (size_t i = 0; i < NumFlags; ++i) {
+    const auto FlagOffset = FlagOffsets[i];
+    OrderedNode *Flag = _LoadFlag(FlagOffset);
    Flag = _Bfe(4, 32, 0, Flag);
-    Flag = _Lshl(Flag, _Constant(FlagOffsets[i]));
+    Flag = _Lshl(Flag, _Constant(FlagOffset));
    Original = _Or(Original, Flag);
  }
  return Original;
 }

-void OpDispatchBuilder::GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
-  auto Size = GetSrcSize(Op) * 8;
+void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
+  if (CurrentDeferredFlags.Type == FlagsGenerationType::TYPE_NONE) {
+    // Nothing to do
+    return;
+  }
+
+  switch (CurrentDeferredFlags.Type) {
+    case FlagsGenerationType::TYPE_ADC:
+      CalculcateFlags_ADC(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.ThreeSource.Src1,
+        CurrentDeferredFlags.Sources.ThreeSource.Src2,
+        CurrentDeferredFlags.Sources.ThreeSource.Src3);
+      break;
+    case FlagsGenerationType::TYPE_SBB:
+      CalculcateFlags_SBB(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.ThreeSource.Src1,
+        CurrentDeferredFlags.Sources.ThreeSource.Src2,
+        CurrentDeferredFlags.Sources.ThreeSource.Src3);
+      break;
+    case FlagsGenerationType::TYPE_SUB:
+      CalculcateFlags_SUB(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src2,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.UpdateCF);
+      break;
+    case FlagsGenerationType::TYPE_ADD:
+      CalculcateFlags_ADD(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src2,
+        CurrentDeferredFlags.Sources.TwoSrcImmediate.UpdateCF);
+      break;
+    case FlagsGenerationType::TYPE_MUL:
+      CalculcateFlags_MUL(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSource.Src1);
+      break;
+    case FlagsGenerationType::TYPE_UMUL:
+      CalculcateFlags_UMUL(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_LOGICAL:
+      CalculcateFlags_Logical(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_LSHL:
+      CalculcateFlags_ShiftLeft(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_LSHLI:
+      CalculcateFlags_ShiftLeftImmediate(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
+      break;
+    case FlagsGenerationType::TYPE_LSHR:
+      CalculcateFlags_ShiftRight(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_LSHRI:
+      CalculcateFlags_ShiftRightImmediate(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
+      break;
+    case FlagsGenerationType::TYPE_ASHR:
+      CalculcateFlags_SignShiftRight(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_ASHRI:
+      CalculcateFlags_SignShiftRightImmediate(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
+      break;
+    case FlagsGenerationType::TYPE_ROR:
+      CalculcateFlags_RotateRight(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_RORI:
+      CalculcateFlags_RotateRightImmediate(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
+      break;
+    case FlagsGenerationType::TYPE_ROL:
+      CalculcateFlags_RotateLeft(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_ROLI:
+      CalculcateFlags_RotateLeftImmediate(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
+        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
+      break;
+    case FlagsGenerationType::TYPE_FCMP:
+      CalculcateFlags_FCMP(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.TwoSource.Src1,
+        CurrentDeferredFlags.Sources.TwoSource.Src2);
+      break;
+    case FlagsGenerationType::TYPE_BEXTR:
+      CalculcateFlags_BEXTR(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_BLSI:
+      CalculcateFlags_BLSI(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_BLSMSK:
+      CalculcateFlags_BLSMSK(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_BLSR:
+      CalculcateFlags_BLSR(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSource.Src1);
+      break;
+    case FlagsGenerationType::TYPE_POPCOUNT:
+      CalculcateFlags_POPCOUNT(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_BZHI:
+      CalculcateFlags_BZHI(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSource.Src1);
+      break;
+    case FlagsGenerationType::TYPE_TZCNT:
+      CalculcateFlags_TZCNT(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_LZCNT:
+      CalculcateFlags_LZCNT(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_BITSELECT:
+      CalculcateFlags_BITSELECT(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_RDRAND:
+      CalculcateFlags_RDRAND(CurrentDeferredFlags.Res);
+      break;
+    case FlagsGenerationType::TYPE_NONE:
+    default: ERROR_AND_DIE_FMT("Unhandled flags type {}", CurrentDeferredFlags.Type);
+  }
+
+  // Done calculating
+  CurrentDeferredFlags.Type = FlagsGenerationType::TYPE_NONE;
+}
+
+void OpDispatchBuilder::CalculcateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+  auto Size = SrcSize * 8;
  // AF
  {
    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
@@ -77,7 +271,7 @@ void OpDispatchBuilder::GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, Orde

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(Size - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -130,13 +324,15 @@ void OpDispatchBuilder::GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, Orde
    case 64:
      AndOp1 = _Bfe(1, 63, AndOp1);
    break;
-    default: LOGMAN_MSG_A("Unknown BFESize: %d", Size); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown BFE size: {}", Size);
+    break;
    }
    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
  }
 }

-void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+void OpDispatchBuilder::CalculcateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
  // AF
  {
    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
@@ -146,7 +342,7 @@ void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, Orde

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -185,7 +381,7 @@ void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, Orde
    auto XorOp2 = _Xor(Res, Src1);
    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);

-    switch (GetSrcSize(Op)) {
+    switch (SrcSize) {
    case 1:
      AndOp1 = _Bfe(1, 7, AndOp1);
    break;
@@ -198,13 +394,15 @@ void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, Orde
    case 8:
      AndOp1 = _Bfe(1, 63, AndOp1);
    break;
-    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown BFE size: {}", SrcSize);
+    break;
    }
    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
  }
 }

-void OpDispatchBuilder::GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+void OpDispatchBuilder::CalculcateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
  // AF
  {
    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
@@ -214,7 +412,7 @@ void OpDispatchBuilder::GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, Orde

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -255,13 +453,13 @@ void OpDispatchBuilder::GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, Orde
    auto XorOp2 = _Xor(Res, Src1);
    OrderedNode *FinalAnd = _And(XorOp1, XorOp2);

-    FinalAnd = _Bfe(1, GetSrcSize(Op) * 8 - 1, FinalAnd);
+    FinalAnd = _Bfe(1, SrcSize * 8 - 1, FinalAnd);

    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(FinalAnd);
  }
 }

-void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+void OpDispatchBuilder::CalculcateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
  // AF
  {
    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
@@ -271,7 +469,7 @@ void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, Orde

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -308,7 +506,7 @@ void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, Orde

    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);

-    switch (GetSrcSize(Op)) {
+    switch (SrcSize) {
    case 1:
      AndOp1 = _Bfe(1, 7, AndOp1);
    break;
@@ -321,13 +519,15 @@ void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, Orde
    case 8:
      AndOp1 = _Bfe(1, 63, AndOp1);
    break;
-    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown BFE size: {}", SrcSize);
+    break;
    }
    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
  }
 }

-void OpDispatchBuilder::GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High) {
+void OpDispatchBuilder::CalculcateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High) {
  // PF/AF/ZF/SF
  // Undefined
  {
@@ -342,7 +542,7 @@ void OpDispatchBuilder::GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, Orde
    // CF and OF are set if the result of the operation can't be fit in to the destination register
    // If the value can fit then the top bits will be zero

-    auto SignBit = _Sbfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    auto SignBit = _Sbfe(1, SrcSize * 8 - 1, Res);

    auto SelectOp = _Select(FEXCore::IR::COND_EQ, High, SignBit, _Constant(0), _Constant(1));

@@ -351,7 +551,7 @@ void OpDispatchBuilder::GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, Orde
  }
 }

-void OpDispatchBuilder::GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High) {
+void OpDispatchBuilder::CalculcateFlags_UMUL(OrderedNode *High) {
  // AF/SF/PF/ZF
  // Undefined
  {
@@ -373,7 +573,7 @@ void OpDispatchBuilder::GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, Ord
  }
 }

-void OpDispatchBuilder::GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+void OpDispatchBuilder::CalculcateFlags_Logical(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
  // AF
  {
    // Undefined
@@ -383,7 +583,7 @@ void OpDispatchBuilder::GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op,

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -418,11 +618,11 @@ auto oldflag = GetRFLAG(FEXCore::X86State::flag);\
 auto newval = _Select(FEXCore::IR::COND_EQ, cond, _Constant(0), oldflag, newflag);\
 SetRFLAG<FEXCore::X86State::flag>(newval);

-void OpDispatchBuilder::GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+void OpDispatchBuilder::CalculcateFlags_ShiftLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
  // CF
  {
    // Extract the last bit shifted in to CF
-    auto Size = _Constant(GetSrcSize(Op) * 8);
+    auto Size = _Constant(SrcSize * 8);
    auto ShiftAmt = _Sub(Size, Src2);
    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
@@ -454,7 +654,7 @@ void OpDispatchBuilder::GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op

  // SF
  {
-    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    auto val = _Bfe(1, SrcSize * 8 - 1, Res);
    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
  }

@@ -462,12 +662,12 @@ void OpDispatchBuilder::GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op
  {
    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
    // When Shift > 1 then OF is undefined
-    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    auto val = _Bfe(1, SrcSize * 8 - 1, _Xor(Src1, Res));
    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
  }
 }

-void OpDispatchBuilder::GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+void OpDispatchBuilder::CalculcateFlags_ShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
  // CF
  {
    // Extract the last bit shifted in to CF
@@ -502,7 +702,7 @@ void OpDispatchBuilder::GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp O

  // SF
  {
-    auto val =_Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    auto val =_Bfe(1, SrcSize * 8 - 1, Res);
    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
  }

@@ -510,12 +710,12 @@ void OpDispatchBuilder::GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp O
  {
    // Only defined when Shift is 1 else undefined
    // OF flag is set if a sign change occurred
-    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    auto val = _Bfe(1, SrcSize * 8 - 1, _Xor(Src1, Res));
    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
  }
 }

-void OpDispatchBuilder::GenerateFlags_SignShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+void OpDispatchBuilder::CalculcateFlags_SignShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
  // CF
  {
    // Extract the last bit shifted in to CF
@@ -550,7 +750,7 @@ void OpDispatchBuilder::GenerateFlags_SignShiftRight(FEXCore::X86Tables::Decoded

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    COND_FLAG_SET(Src2, RFLAG_SF_LOC, LshrOp);
@@ -562,14 +762,14 @@ void OpDispatchBuilder::GenerateFlags_SignShiftRight(FEXCore::X86Tables::Decoded
  }
 }

-void OpDispatchBuilder::GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+void OpDispatchBuilder::CalculcateFlags_ShiftLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
  // No flags changed if shift is zero
  if (Shift == 0) return;

  // CF
  {
    // Extract the last bit shifted in to CF
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - Shift, Src1));
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, SrcSize * 8 - Shift, Src1));
  }

  // PF
@@ -598,20 +798,20 @@ void OpDispatchBuilder::GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::Dec

  // SF
  {
-    auto LshrOp = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    auto LshrOp = _Bfe(1, SrcSize * 8 - 1, Res);

    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);

    // OF
    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
    if (Shift == 1) {
-      auto SourceBit = _Bfe(1, GetSrcSize(Op) * 8 - 1, Src1);
+      auto SourceBit = _Bfe(1, SrcSize * 8 - 1, Src1);
      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(SourceBit, LshrOp));
    }
  }
 }

-void OpDispatchBuilder::GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+void OpDispatchBuilder::CalculcateFlags_SignShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
  // No flags changed if shift is zero
  if (Shift == 0) return;

@@ -647,7 +847,7 @@ void OpDispatchBuilder::GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -662,7 +862,7 @@ void OpDispatchBuilder::GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables
  }
 }

-void OpDispatchBuilder::GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+void OpDispatchBuilder::CalculcateFlags_ShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
  // No flags changed if shift is zero
  if (Shift == 0) return;

@@ -698,7 +898,7 @@ void OpDispatchBuilder::GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::De

  // SF
  {
-    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+    auto SignBitConst = _Constant(SrcSize * 8 - 1);

    auto LshrOp = _Lshr(Res, SignBitConst);
    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
@@ -709,13 +909,13 @@ void OpDispatchBuilder::GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::De
    // Only defined when Shift is 1 else undefined
    // Is set to the MSB of the original value
    if (Shift == 1) {
-      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - 1, Src1));
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Bfe(1, SrcSize * 8 - 1, Src1));
    }
  }
 }

-void OpDispatchBuilder::GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-  auto OpSize = GetSrcSize(Op) * 8;
+void OpDispatchBuilder::CalculcateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = SrcSize * 8;

  // Extract the last bit shifted in to CF
  auto NewCF = _Bfe(1, OpSize - 1, Res);
@@ -743,8 +943,8 @@ void OpDispatchBuilder::GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp
  }
 }

-void OpDispatchBuilder::GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-  auto OpSize = GetSrcSize(Op) * 8;
+void OpDispatchBuilder::CalculcateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = SrcSize * 8;

  // Extract the last bit shifted in to CF
  //auto Size = _Constant(GetSrcSize(Res) * 8);
@@ -773,10 +973,10 @@ void OpDispatchBuilder::GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp O
  }
 }

-void OpDispatchBuilder::GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+void OpDispatchBuilder::CalculcateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
  if (Shift == 0) return;

-  auto OpSize = GetSrcSize(Op) * 8;
+  auto OpSize = SrcSize * 8;

  auto NewCF = _Bfe(1, OpSize - Shift, Src1);

@@ -795,10 +995,10 @@ void OpDispatchBuilder::GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::D
  }
 }

-void OpDispatchBuilder::GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+void OpDispatchBuilder::CalculcateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
  if (Shift == 0) return;

-  auto OpSize = GetSrcSize(Op) * 8;
+  auto OpSize = SrcSize * 8;

  // CF
  {
@@ -815,4 +1015,264 @@ void OpDispatchBuilder::GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::De
  }
 }

+void OpDispatchBuilder::CalculcateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  OrderedNode *HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT);
+  OrderedNode *HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ);
+  OrderedNode *HostFlag_Unordered  = _GetHostFlag(Res, FCMP_FLAG_UNORDERED);
+
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
+  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
+  SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
+
+  auto ZeroConst = _Constant(0);
+  SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(ZeroConst);
+}
+
+void OpDispatchBuilder::CalculcateFlags_BEXTR(OrderedNode *Src) {
+  // Handle flag setting.
+  //
+  // All that matters primarily for this instruction is
+  // that we only set the ZF flag properly.
+  //
+  // CF and OF are defined as being set to zero
+  //
+  SetRFLAG<X86State::RFLAG_CF_LOC>(_Constant(0));
+  SetRFLAG<X86State::RFLAG_OF_LOC>(_Constant(0));
+
+  // Every other flag is considered undefined after a
+  // BEXTR instruction, but we opt to reliably clear them.
+  //
+  SetRFLAG<X86State::RFLAG_AF_LOC>(_Constant(0));
+  SetRFLAG<X86State::RFLAG_SF_LOC>(_Constant(0));
+
+  // PF
+  if (CTX->Config.ABINoPF) {
+    _InvalidateFlags(1UL << X86State::RFLAG_PF_LOC);
+  } else {
+    SetRFLAG<X86State::RFLAG_PF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  auto ZeroOp = _Select(IR::COND_EQ,
+                        Src, _Constant(0),
+                        _Constant(1), _Constant(0));
+  SetRFLAG<X86State::RFLAG_ZF_LOC>(ZeroOp);
+}
+
+void OpDispatchBuilder::CalculcateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src) {
+  // Now for the flags:
+  //
+  // Only CF, SF, ZF and OF are defined as being updated
+  // CF is cleared if Src is zero, otherwise it's set.
+  // SF is set to the value of the most significant operand bit of Result.
+  // OF is always cleared
+  // ZF is set, as usual, if Result is zero or not.
+  //
+  // AF and PF are documented as being in an undefined state after
+  // a BLSI operation, however, we choose to reliably clear them.
+
+  auto Zero = _Constant(0);
+  auto One = _Constant(1);
+
+  SetRFLAG<X86State::RFLAG_OF_LOC>(Zero);
+  SetRFLAG<X86State::RFLAG_AF_LOC>(Zero);
+  if (CTX->Config.ABINoPF) {
+    _InvalidateFlags(1UL << X86State::RFLAG_PF_LOC);
+  } else {
+    SetRFLAG<X86State::RFLAG_PF_LOC>(Zero);
+  }
+
+  // ZF
+  {
+    auto ZFOp = _Select(IR::COND_EQ,
+                        Src, Zero,
+                        One, Zero);
+    SetRFLAG<X86State::RFLAG_ZF_LOC>(ZFOp);
+  }
+
+  // CF
+  {
+    auto CFOp = _Select(IR::COND_EQ,
+                        Src, Zero,
+                        Zero, One);
+    SetRFLAG<X86State::RFLAG_CF_LOC>(CFOp);
+  }
+
+  // SF
+  {
+    auto SignBit = _Constant(SrcSize * 8 - 1);
+    auto SFOp = _Lshr(Src, SignBit);
+
+    SetRFLAG<X86State::RFLAG_SF_LOC>(SFOp);
+  }
+}
+
+void OpDispatchBuilder::CalculcateFlags_BLSMSK(OrderedNode *Src) {
+  // Now for the flags.
+
+  auto Zero = _Constant(0);
+  auto One = _Constant(1);
+
+  SetRFLAG<X86State::RFLAG_ZF_LOC>(Zero);
+  SetRFLAG<X86State::RFLAG_OF_LOC>(Zero);
+  SetRFLAG<X86State::RFLAG_AF_LOC>(Zero);
+  if (CTX->Config.ABINoPF) {
+    _InvalidateFlags(1UL << X86State::RFLAG_PF_LOC);
+  } else {
+    SetRFLAG<X86State::RFLAG_PF_LOC>(Zero);
+  }
+
+  auto CFOp = _Select(IR::COND_EQ,
+                      Src, Zero,
+                      Zero, One);
+  SetRFLAG<X86State::RFLAG_CF_LOC>(CFOp);
+}
+
+void OpDispatchBuilder::CalculcateFlags_BLSR(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
+  // Now for flags.
+  auto Zero = _Constant(0);
+  auto One = _Constant(1);
+
+  SetRFLAG<X86State::RFLAG_OF_LOC>(Zero);
+  SetRFLAG<X86State::RFLAG_AF_LOC>(Zero);
+  if (CTX->Config.ABINoPF) {
+    _InvalidateFlags(1UL << X86State::RFLAG_PF_LOC);
+  } else {
+    SetRFLAG<X86State::RFLAG_PF_LOC>(Zero);
+  }
+
+  // ZF
+  {
+    auto ZFOp = _Select(IR::COND_EQ,
+                        Result, Zero,
+                        One, Zero);
+    SetRFLAG<X86State::RFLAG_ZF_LOC>(ZFOp);
+  }
+
+  // CF
+  {
+    auto CFOp = _Select(IR::COND_EQ,
+                        Src, Zero,
+                        Zero, One);
+    SetRFLAG<X86State::RFLAG_CF_LOC>(CFOp);
+  }
+
+  // SF
+  {
+    auto SignBit = _Constant(SrcSize * 8 - 1);
+    auto SFOp = _Lshr(Result, SignBit);
+
+    SetRFLAG<X86State::RFLAG_SF_LOC>(SFOp);
+  }
+}
+
+void OpDispatchBuilder::CalculcateFlags_POPCOUNT(OrderedNode *Src) {
+  // Set ZF
+  auto Zero = _Constant(0);
+  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
+      Src,  Zero,
+      _Constant(1), Zero);
+
+  // Set flags
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(ZFResult);
+  SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(Zero);
+}
+
+void OpDispatchBuilder::CalculcateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
+  // Now for the flags
+
+  auto Bounds = _Constant(SrcSize * 8- 1);
+  auto Zero = _Constant(0);
+  auto One = _Constant(1);
+
+  SetRFLAG<X86State::RFLAG_OF_LOC>(Zero);
+  SetRFLAG<X86State::RFLAG_AF_LOC>(Zero);
+  if (CTX->Config.ABINoPF) {
+    _InvalidateFlags(1UL << X86State::RFLAG_PF_LOC);
+  } else {
+    SetRFLAG<X86State::RFLAG_PF_LOC>(Zero);
+  }
+
+  // ZF
+  {
+    auto ZFOp = _Select(IR::COND_EQ,
+                        Result, Zero,
+                        One, Zero);
+    SetRFLAG<X86State::RFLAG_ZF_LOC>(ZFOp);
+  }
+
+  // CF
+  {
+    auto CFOp = _Select(IR::COND_UGT,
+                        Src, Bounds,
+                        One, Zero);
+    SetRFLAG<X86State::RFLAG_CF_LOC>(CFOp);
+  }
+
+  // SF
+  {
+    auto SFOp = _Lshr(Result, Bounds);
+
+    SetRFLAG<X86State::RFLAG_SF_LOC>(SFOp);
+  }
+}
+
+void OpDispatchBuilder::CalculcateFlags_TZCNT(OrderedNode *Src) {
+  // OF, SF, AF, PF all undefined
+  auto Zero = _Constant(0);
+  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
+      Src,  Zero,
+      _Constant(1), Zero);
+
+  // Set flags
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(ZFResult);
+  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Bfe(1, 0, Src));
+}
+
+void OpDispatchBuilder::CalculcateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src) {
+  // OF, SF, AF, PF all undefined
+
+  auto Zero = _Constant(0);
+  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
+      Src,  Zero,
+      _Constant(1), Zero);
+
+  // Set flags
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(ZFResult);
+  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Bfe(1, SrcSize * 8 - 1, Src));
+}
+
+void OpDispatchBuilder::CalculcateFlags_BITSELECT(OrderedNode *Src) {
+  // OF, SF, AF, PF, CF all undefined
+
+  auto ZeroConst = _Constant(0);
+  auto OneConst = _Constant(1);
+
+  // ZF is set to 1 if the source was zero
+  auto ZFSelectOp = _Select(FEXCore::IR::COND_EQ,
+      Src, ZeroConst,
+      OneConst, ZeroConst);
+
+  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(ZFSelectOp);
+}
+
+void OpDispatchBuilder::CalculcateFlags_RDRAND(OrderedNode *Src) {
+  // OF, SF, ZF, AF, PF all zero
+  // CF is set to the incoming source
+
+  auto ZeroConst = _Constant(0);
+  SetRFLAG<X86State::RFLAG_OF_LOC>(ZeroConst);
+  SetRFLAG<X86State::RFLAG_SF_LOC>(ZeroConst);
+  SetRFLAG<X86State::RFLAG_ZF_LOC>(ZeroConst);
+  SetRFLAG<X86State::RFLAG_AF_LOC>(ZeroConst);
+  SetRFLAG<X86State::RFLAG_PF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Src);
+}
+
 }
@@ -241,6 +241,8 @@ void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 2>(OpcodeArgs);
 template
 void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 4>(OpcodeArgs);
 template
+void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPGT, 8>(OpcodeArgs);
+template
 void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPEQ, 1>(OpcodeArgs);
 template
 void OpDispatchBuilder::VectorALUOp<IR::OP_VCMPEQ, 2>(OpcodeArgs);
@@ -295,6 +297,24 @@ void OpDispatchBuilder::VectorALUOp<IR::OP_VUQSUB, 1>(OpcodeArgs);
 template
 void OpDispatchBuilder::VectorALUOp<IR::OP_VUQSUB, 2>(OpcodeArgs);

+template<FEXCore::IR::IROps IROp, size_t ElementSize>
+void OpDispatchBuilder::VectorALUROp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+
+  auto ALUOp = _VAdd(Size, ElementSize, Src, Dest);
+  // Overwrite our IR's op type
+  ALUOp.first->Header.Op = IROp;
+
+  StoreResult(FPRClass, Op, ALUOp, -1);
+}
+
+template
+void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 4>(OpcodeArgs);
+template
+void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 8>(OpcodeArgs);
+
 template<FEXCore::IR::IROps IROp, size_t ElementSize>
 void OpDispatchBuilder::VectorScalarALUOp(OpcodeArgs) {
  auto Size = GetSrcSize(Op);
@@ -390,14 +410,35 @@ void OpDispatchBuilder::VectorUnaryOp<IR::OP_VABS, 2, false>(OpcodeArgs);
 template
 void OpDispatchBuilder::VectorUnaryOp<IR::OP_VABS, 4, false>(OpcodeArgs);

+template<FEXCore::IR::IROps IROp, size_t ElementSize>
+void OpDispatchBuilder::VectorUnaryDuplicateOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  auto ALUOp = _VFSqrt(ElementSize, ElementSize, Src);
+  // Overwrite our IR's op type
+  ALUOp.first->Header.Op = IROp;
+
+  // Duplicate the lower bits
+  auto Result = _VDupElement(Size, ElementSize, ALUOp, 0);
+  StoreResult(FPRClass, Op, Result, -1);
+}
+
+template
+void OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRSQRT, 4>(OpcodeArgs);
+template
+void OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRECP, 4>(OpcodeArgs);
+
 void OpDispatchBuilder::MOVQOp(OpcodeArgs) {
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
  // This instruction is a bit special that if the destination is a register then it'll ZEXT the 64bit source to 128bit
  if (Op->Dest.IsGPR()) {
    const auto gpr = Op->Dest.Data.GPR.GPR;
-    _StoreContext(FPRClass, 8, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][0]), Src);
+
+    _StoreContext(8, FPRClass, Src, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][0]));
    auto Const = _Constant(0);
-    _StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][1]), Const);
+    _StoreContext(8, GPRClass, Const, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][1]));
  }
  else {
    // This is simple, just store the result
@@ -438,14 +479,15 @@ void OpDispatchBuilder::MOVMSKOpOne(OpcodeArgs) {
  //TODO: We could remove this VCastFromGOR + VInsGPR pair if we had a VDUPFromGPR instruction that maps directly to AArch64.
  auto M = _Constant(0x80'40'20'10'08'04'02'01ULL);
  OrderedNode *VMask = _VCastFromGPR(16, 8, M);
-  VMask = _VInsGPR(16, 8, VMask, M, 1);

-  auto VCMP = _VCMPLTZ(Src, 16, 1);
-  auto VAnd = _VAnd(VCMP, VMask, 16, 1);
+  VMask = _VInsGPR(16, 8, 1, VMask, M);

-  auto VAdd1 = _VAddP(VAnd, VAnd, 16, 1);
-  auto VAdd2 = _VAddP(VAdd1, VAdd1, 8, 1);
-  auto VAdd3 = _VAddP(VAdd2, VAdd2, 8, 1);
+  auto VCMP = _VCMPLTZ(16, 1, Src);
+  auto VAnd = _VAnd(16, 1, VCMP, VMask);
+
+  auto VAdd1 = _VAddP(16, 1, VAnd, VAnd);
+  auto VAdd2 = _VAddP(8, 1, VAdd1, VAdd1);
+  auto VAdd3 = _VAddP(8, 1, VAdd2, VAdd2);

  StoreResult(GPRClass, Op, _VExtractToGPR(16, 2, VAdd3, 0), -1);
 }
@@ -502,11 +544,11 @@ void OpDispatchBuilder::PSHUFBOp(OpcodeArgs) {
  // Bits [6:4] is reserved for 128bit
  // Bits [6:3] is reserved for 64bit
  if (Size == 8) {
-    auto MaskVector = _VectorImm(0b1000'0111, Size, 1);
+    auto MaskVector = _VectorImm(Size, 1, 0b1000'0111);
    Src = _VAnd(Size, Size, Src, MaskVector);
  }
  else {
-    auto MaskVector = _VectorImm(0b1000'1111, Size, 1);
+    auto MaskVector = _VectorImm(Size, 1, 0b1000'1111);
    Src = _VAnd(Size, Size, Src, MaskVector);
  }
  auto Res = _VTBL1(Size, Dest, Src);
@@ -515,8 +557,8 @@ void OpDispatchBuilder::PSHUFBOp(OpcodeArgs) {

 template<size_t ElementSize, bool HalfSize, bool Low>
 void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) {
-  LOGMAN_THROW_A(ElementSize != 0, "What. No element size?");
-  auto Size = GetSrcSize(Op);
+  LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?");
+  const auto Size = GetSrcSize(Op);
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
  uint8_t Shuffle = Op->Src[1].Data.Literal.Value;

@@ -552,8 +594,8 @@ void OpDispatchBuilder::PSHUFDOp<4, false, true>(OpcodeArgs);

 template<size_t ElementSize>
 void OpDispatchBuilder::SHUFOp(OpcodeArgs) {
-  LOGMAN_THROW_A(ElementSize != 0, "What. No element size?");
-  auto Size = GetSrcSize(Op);
+  LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?");
+  const auto Size = GetSrcSize(Op);
  OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
  OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
  uint8_t Shuffle = Op->Src[1].Data.Literal.Value;
@@ -620,14 +662,14 @@ void OpDispatchBuilder::PINSROp(OpcodeArgs) {
    Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], ElementSize, Op->Flags, -1);
  }
  OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Index = Op->Src[1].Data.Literal.Value;

  uint8_t NumElements = Size / ElementSize;
  Index &= NumElements - 1;

  // This maps 1:1 to an AArch64 NEON Op
-  auto ALUOp = _VInsGPR(Size, ElementSize, Dest, Src, Index);
+  auto ALUOp = _VInsGPR(Size, ElementSize, Index, Dest, Src);
  StoreResult(FPRClass, Op, ALUOp, -1);
 }

@@ -641,7 +683,7 @@ template
 void OpDispatchBuilder::PINSROp<8>(OpcodeArgs);

 void OpDispatchBuilder::InsertPSOp(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint8_t Imm = Op->Src[1].Data.Literal.Value;
  uint8_t CountS = (Imm >> 6);
  uint8_t CountD = (Imm >> 4) & 0b11;
@@ -670,10 +712,10 @@ void OpDispatchBuilder::InsertPSOp(OpcodeArgs) {

  // ZMask happens after insert
  if (ZMask == 0xF) {
-    Dest = _VectorImm(0, 16, 4);
+    Dest = _VectorImm(16, 4, 0);
  }
  else if (ZMask) {
-    auto Zero = _VectorImm(0, 16, 4);
+    auto Zero = _VectorImm(16, 4, 0);
    for (size_t i = 0; i < 4; ++i) {
      if (ZMask & (1 << i)) {
        Dest = _VInsElement(GetDstSize(Op), 4, i, 0, Dest, Zero);
@@ -689,7 +731,7 @@ void OpDispatchBuilder::PExtrOp(OpcodeArgs) {
  const auto Size = GetSrcSize(Op);

  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Index = Op->Src[1].Data.Literal.Value;

  const uint8_t NumElements = Size / ElementSize;
@@ -766,7 +808,7 @@ void OpDispatchBuilder::PSRLDOp(OpcodeArgs) {
  OrderedNode *Result{};

  // Incoming element size for the shift source is always 8
-  auto MaxShift = _VectorImm(ElementSize * 8, 8, 8);
+  auto MaxShift = _VectorImm(8, 8, ElementSize * 8);
  Src = _VUMin(8, 8, MaxShift, Src);
  Result = _VUShrS(Size, ElementSize, Dest, Src);

@@ -784,7 +826,7 @@ template<size_t ElementSize>
 void OpDispatchBuilder::PSRLI(OpcodeArgs) {
  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);

-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t ShiftConstant = Op->Src[1].Data.Literal.Value;

  auto Size = GetSrcSize(Op);
@@ -804,7 +846,7 @@ template<size_t ElementSize>
 void OpDispatchBuilder::PSLLI(OpcodeArgs) {
  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);

-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t ShiftConstant = Op->Src[1].Data.Literal.Value;

  auto Size = GetSrcSize(Op);
@@ -830,7 +872,7 @@ void OpDispatchBuilder::PSLL(OpcodeArgs) {
  OrderedNode *Result{};

  // Incoming element size for the shift source is always 8
-  auto MaxShift = _VectorImm(ElementSize * 8, 8, 8);
+  auto MaxShift = _VectorImm(8, 8, ElementSize * 8);
  Src = _VUMin(8, 8, MaxShift, Src);
  Result = _VUShlS(Size, ElementSize, Dest, Src);

@@ -854,7 +896,7 @@ void OpDispatchBuilder::PSRAOp(OpcodeArgs) {
  OrderedNode *Result{};

  // Incoming element size for the shift source is always 8
-  auto MaxShift = _VectorImm(ElementSize * 8, 8, 8);
+  auto MaxShift = _VectorImm(8, 8, ElementSize * 8);
  Src = _VUMin(8, 8, MaxShift, Src);
  Result = _VSShrS(Size, ElementSize, Dest, Src);

@@ -867,7 +909,7 @@ template
 void OpDispatchBuilder::PSRAOp<4>(OpcodeArgs);

 void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Shift = Op->Src[1].Data.Literal.Value;

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
@@ -879,7 +921,7 @@ void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
 }

 void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Shift = Op->Src[1].Data.Literal.Value;

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
@@ -892,7 +934,7 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {

 template<size_t ElementSize>
 void OpDispatchBuilder::PSRAIOp(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Shift = Op->Src[1].Data.Literal.Value;

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
@@ -957,12 +999,11 @@ void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) {
  // Source Element size is determined by instruction
  size_t GPRSize = GetDstSize(Op);

-  size_t ElementSize = SrcElementSize;
  if constexpr (HostRoundingMode) {
-    Src = _Float_ToGPR_S(Src, ElementSize, GPRSize);
+    Src = _Float_ToGPR_S(GPRSize, SrcElementSize, Src);
  }
  else {
-    Src = _Float_ToGPR_ZS(Src, ElementSize, GPRSize);
+    Src = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src);
  }

  StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Src, GPRSize, -1);
@@ -985,11 +1026,11 @@ void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs) {
  size_t ElementSize = SrcElementSize;
  size_t Size = GetDstSize(Op);
  if constexpr (Widen) {
-    Src = _VSXTL(Src, Size, ElementSize);
+    Src = _VSXTL(Size, ElementSize, Src);
    ElementSize <<= 1;
  }

-  Src = _Vector_SToF(Src, Size, ElementSize);
+  Src = _Vector_SToF(Size, ElementSize, Src);

  StoreResult(FPRClass, Op, Src, -1);
 }
@@ -1007,15 +1048,15 @@ void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs) {
  size_t Size = GetDstSize(Op);

  if constexpr (Narrow) {
-    Src = _Vector_FToF(Size, SrcElementSize >> 1, SrcElementSize, Src);
+    Src = _Vector_FToF(Size, SrcElementSize >> 1, Src, SrcElementSize);
    ElementSize >>= 1;
  }

  if constexpr (HostRoundingMode) {
-    Src = _Vector_FToS(Src, Size, ElementSize);
+    Src = _Vector_FToS(Size, ElementSize, Src);
  }
  else {
-    Src = _Vector_FToZS(Src, Size, ElementSize);
+    Src = _Vector_FToZS(Size, ElementSize, Src);
  }

  StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, -1);
@@ -1025,6 +1066,8 @@ template
 void OpDispatchBuilder::Vector_CVT_Float_To_Int<4, false, false>(OpcodeArgs);
 template
 void OpDispatchBuilder::Vector_CVT_Float_To_Int<4, false, true>(OpcodeArgs);
+template
+void OpDispatchBuilder::Vector_CVT_Float_To_Int<4, true, false>(OpcodeArgs);

 template
 void OpDispatchBuilder::Vector_CVT_Float_To_Int<8, true, true>(OpcodeArgs);
@@ -1053,10 +1096,10 @@ void OpDispatchBuilder::Vector_CVT_Float_To_Float(OpcodeArgs) {
  size_t Size = GetDstSize(Op);

  if constexpr (DstElementSize > SrcElementSize) {
-    Src = _Vector_FToF(Size, SrcElementSize << 1, SrcElementSize, Src);
+    Src = _Vector_FToF(Size, SrcElementSize << 1, Src, SrcElementSize);
  }
  else {
-    Src = _Vector_FToF(Size, SrcElementSize >> 1, SrcElementSize, Src);
+    Src = _Vector_FToF(Size, SrcElementSize >> 1, Src, SrcElementSize);
  }

  StoreResult(FPRClass, Op, Src, -1);
@@ -1074,12 +1117,12 @@ void OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs) {
  size_t ElementSize = SrcElementSize;
  size_t DstSize = GetDstSize(Op);
  if constexpr (Widen) {
-    Src = _VSXTL(Src, DstSize, ElementSize);
+    Src = _VSXTL(DstSize, ElementSize, Src);
    ElementSize <<= 1;
  }

  // Always signed
-  Src = _Vector_SToF(Src, DstSize, ElementSize);
+  Src = _Vector_SToF(DstSize, ElementSize, Src);

  OrderedNode *Dest{};
  if constexpr (Widen) {
@@ -1107,14 +1150,14 @@ void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs) {
  size_t Size = GetDstSize(Op);

  // Always narrows
-  Src = _Vector_FToF(Size, SrcElementSize >> 1, SrcElementSize, Src);
+  Src = _Vector_FToF(Size, SrcElementSize >> 1, Src, SrcElementSize);
  ElementSize >>= 1;

  if constexpr (HostRoundingMode) {
-    Src = _Vector_FToS(Src, Size, ElementSize);
+    Src = _Vector_FToS(Size, ElementSize, Src);
  }
  else {
-    Src = _Vector_FToZS(Src, Size, ElementSize);
+    Src = _Vector_FToZS(Size, ElementSize, Src);
  }

  StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, -1);
@@ -1133,7 +1176,7 @@ void OpDispatchBuilder::MASKMOVOp(OpcodeArgs) {
  OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
  OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);

-  OrderedNode *MemDest = _LoadContext(GPRSize, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), GPRClass);
+  OrderedNode *MemDest = _LoadContext(GPRSize, GPRClass, GPROffset(X86State::REG_RDI));

  const size_t NumElements = Size / 64;
  for (size_t Element = 0; Element < NumElements; ++Element) {
@@ -1187,13 +1230,6 @@ void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
  auto Size = GetSrcSize(Op);
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
  OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
-  OrderedNode *Src2{};
-  if constexpr (Scalar) {
-    Src2 = _VExtractElement(GetDstSize(Op), Size, Dest, 0);
-  }
-  else {
-    Src2 = Dest;
-  }
  uint8_t CompType = Op->Src[1].Data.Literal.Value;

  OrderedNode *Result{};
@@ -1201,32 +1237,34 @@ void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
  //auto ALUOp = _VCMPGT(Size, ElementSize, Dest, Src);
  switch (CompType) {
    case 0x00: case 0x08: case 0x10: case 0x18: // EQ
-      Result = _VFCMPEQ(Size, ElementSize, Src2, Src);
+      Result = _VFCMPEQ(Size, ElementSize, Dest, Src);
    break;
    case 0x01: case 0x09: case 0x11: case 0x19: // LT, GT(Swapped operand)
-      Result = _VFCMPLT(Size, ElementSize, Src2, Src);
+      Result = _VFCMPLT(Size, ElementSize, Dest, Src);
    break;
    case 0x02: case 0x0A: case 0x12: case 0x1A: // LE, GE(Swapped operand)
-      Result = _VFCMPLE(Size, ElementSize, Src2, Src);
+      Result = _VFCMPLE(Size, ElementSize, Dest, Src);
    break;
    case 0x03: case 0x0B: case 0x13: case 0x1B: // Unordered
-      Result = _VFCMPUNO(Size, ElementSize, Src2, Src);
+      Result = _VFCMPUNO(Size, ElementSize, Dest, Src);
    break;
    case 0x04: case 0x0C: case 0x14: case 0x1C: // NEQ
-      Result = _VFCMPNEQ(Size, ElementSize, Src2, Src);
+      Result = _VFCMPNEQ(Size, ElementSize, Dest, Src);
    break;
    case 0x05: case 0x0D: case 0x15: case 0x1D: // NLT, NGT(Swapped operand)
-      Result = _VFCMPLT(Size, ElementSize, Src2, Src);
+      Result = _VFCMPLT(Size, ElementSize, Dest, Src);
      Result = _VNot(Size, ElementSize, Result);
    break;
    case 0x06: case 0x0E: case 0x16: case 0x1E: // NLE, NGE(Swapped operand)
-      Result = _VFCMPLE(Size, ElementSize, Src2, Src);
+      Result = _VFCMPLE(Size, ElementSize, Dest, Src);
      Result = _VNot(Size, ElementSize, Result);
    break;
    case 0x07: case 0x0F: case 0x17: case 0x1F: // Ordered
-      Result = _VFCMPORD(Size, ElementSize, Src2, Src);
+      Result = _VFCMPORD(Size, ElementSize, Dest, Src);
+    break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Comparison type: {}", CompType);
    break;
-    default: LOGMAN_MSG_A("Unknown Comparison type: %d", CompType);
  }

  if constexpr (Scalar) {
@@ -1266,7 +1304,7 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
  }

  {
-    auto FCW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FCW), GPRClass);
+    auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW));
    _StoreMem(GPRClass, 2, Mem, FCW, 2);
  }

@@ -1292,7 +1330,7 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
  {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(4));
-    auto FTW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FTW), GPRClass);
+    auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
    _StoreMem(GPRClass, 2, MemLocation, FTW, 2);
  }

@@ -1341,7 +1379,7 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
  // If OSFXSR bit in CR4 is not set than FXSAVE /may/ not save the XMM registers
  // This is implementation dependent
  for (unsigned i = 0; i < 8; ++i) {
-    OrderedNode *MMReg = _LoadContext(16, offsetof(FEXCore::Core::CPUState, mm[i]), FPRClass);
+    OrderedNode *MMReg = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, mm[i]));
    OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 32));

    _StoreMem(FPRClass, 16, MemLocation, MMReg, 16);
@@ -1349,7 +1387,7 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;

  for (unsigned i = 0; i < NumRegs; ++i) {
-    OrderedNode *XMMReg = _LoadContext(16, offsetof(FEXCore::Core::CPUState, xmm[i]), FPRClass);
+    OrderedNode *XMMReg = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[i]));
    OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));

    _StoreMem(FPRClass, 16, MemLocation, XMMReg, 16);
@@ -1362,7 +1400,7 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {

  auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2);
  _F80LoadFCW(NewFCW);
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FCW), NewFCW);
+  _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));

  {
    OrderedNode *MemLocation = _Add(Mem, _Constant(2));
@@ -1387,20 +1425,20 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(4));
    auto NewFTW = _LoadMem(GPRClass, 2, MemLocation, 2);
-    _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), NewFTW);
+    _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
  }

  for (unsigned i = 0; i < 8; ++i) {
    OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 32));
    auto MMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
-    _StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, mm[i]), MMReg);
+    _StoreContext(16, FPRClass, MMReg, offsetof(FEXCore::Core::CPUState, mm[i]));
  }
  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;

  for (unsigned i = 0; i < NumRegs; ++i) {
    OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));
    auto XMMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
-    _StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, xmm[i]), XMMReg);
+    _StoreContext(16, FPRClass, XMMReg, offsetof(FEXCore::Core::CPUState, xmm[i]));
  }
 }

@@ -1425,25 +1463,14 @@ template<size_t ElementSize>
 void OpDispatchBuilder::UCOMISxOp(OpcodeArgs) {
  OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
  OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
-  OrderedNode *Res = _FCmp(Src1, Src2, ElementSize,
+  OrderedNode *Res = _FCmp(ElementSize, Src1, Src2,
    (1 << FCMP_FLAG_EQ) |
    (1 << FCMP_FLAG_LT) |
    (1 << FCMP_FLAG_UNORDERED));

-  OrderedNode *HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT);
-  OrderedNode *HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ);
-  OrderedNode *HostFlag_Unordered  = _GetHostFlag(Res, FCMP_FLAG_UNORDERED);
+  GenerateFlags_FCMP(Op, Res, Src1, Src2);

-  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
-  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
-  SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
-
-  auto ZeroConst = _Constant(0);
-  SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(ZeroConst);
-  SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(ZeroConst);
-  SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(ZeroConst);
-
-  flagsOp = FLAGS_OP_FCMP;
+  flagsOp = SelectionFlag::FCMP;
  flagsOpDest = Src1;
  flagsOpSrc = Src2;
  flagsOpSize = GetSrcSize(Op);
@@ -1557,8 +1584,8 @@ void OpDispatchBuilder::MOVQ2DQ(OpcodeArgs) {

  // This instruction is a bit special in that if the source is MMX then it zexts to 128bit
  if constexpr (ToXMM) {
-    Src = _VMov(Src, 16);
-    _StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, xmm[Op->Dest.Data.GPR.GPR - FEXCore::X86State::REG_XMM_0][0]), Src);
+    Src = _VMov(16, Src);
+    _StoreContext(16, FPRClass, Src, offsetof(FEXCore::Core::CPUState, xmm[Op->Dest.Data.GPR.GPR - FEXCore::X86State::REG_XMM_0][0]));
  }
  else {
    // This is simple, just store the result
@@ -1647,11 +1674,151 @@ void OpDispatchBuilder::ADDSUBPOp(OpcodeArgs) {
  StoreResult(FPRClass, Op, ResAdd, -1);
 }

+void OpDispatchBuilder::PFNACCOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  OrderedNode *ResSubSrc{};
+  OrderedNode *ResSubDest{};
+  auto UpperSubDest = _VExtractElement(Size, 4, Dest, 1);
+  auto UpperSubSrc = _VExtractElement(Size, 4, Src, 1);
+
+  ResSubDest = _VFSub(4, 4, Dest, UpperSubDest);
+  ResSubSrc = _VFSub(4, 4, Src, UpperSubSrc);
+
+  auto Result = _VInsElement(8, 4, 1, 0, ResSubDest, ResSubSrc);
+
+  StoreResult(FPRClass, Op, Result, -1);
+}
+
+void OpDispatchBuilder::PFPNACCOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  OrderedNode *ResAdd{};
+  OrderedNode *ResSub{};
+  auto UpperSubDest = _VExtractElement(Size, 4, Dest, 1);
+
+  ResSub = _VFSub(4, 4, Dest, UpperSubDest);
+  ResAdd = _VFAddP(Size, 4, Src, Src);
+
+  auto Result = _VInsElement(8, 4, 1, 0, ResSub, ResAdd);
+
+  StoreResult(FPRClass, Op, Result, -1);
+}
+
+void OpDispatchBuilder::PSWAPDOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  auto Result = _VRev64(Size, 4, Src);
+  StoreResult(FPRClass, Op, Result, -1);
+}
+
 template
 void OpDispatchBuilder::ADDSUBPOp<4>(OpcodeArgs);
 template
 void OpDispatchBuilder::ADDSUBPOp<8>(OpcodeArgs);

+void OpDispatchBuilder::PI2FWOp(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  size_t Size = GetDstSize(Op);
+
+  // We now need to transpose the lower 16-bits of each element together
+  // Only needing to move the upper element down in this case
+  Src = _VInsElement(Size, 2, 1, 2, Src, Src);
+
+  // Now we need to sign extend the 16bit value to 32-bit
+  Src = _VSXTL(Size, 2, Src);
+
+  // int32_t to float
+  Src = _Vector_SToF(Size, 4, Src);
+
+  StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, -1);
+}
+
+void OpDispatchBuilder::PF2IWOp(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  size_t Size = GetDstSize(Op);
+
+  // Float to int32_t
+  Src = _Vector_FToZS(Size, 4, Src);
+
+  // We now need to transpose the lower 16-bits of each element together
+  // Only needing to move the upper element down in this case
+  Src = _VInsElement(Size, 2, 1, 2, Src, Src);
+
+  // Now we need to sign extend the 16bit value to 32-bit
+  Src = _VSXTL(Size, 2, Src);
+  StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, -1);
+}
+
+void OpDispatchBuilder::PMULHRWOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  OrderedNode *Res{};
+
+  // Implementation is more efficient for 8byte registers
+  // Multiplies 4 16bit values in to 4 32bit values
+  Res = _VSMull(Size * 2, 2, Dest, Src);
+  //TODO: We could remove this VCastFromGOR + VInsGPR pair if we had a VDUPFromGPR instruction that maps directly to AArch64.
+  auto M = _Constant(0x0000'8000'0000'8000ULL);
+  OrderedNode *VConstant = _VCastFromGPR(16, 8, M);
+  VConstant = _VInsGPR(16, 8, 1, VConstant, M);
+
+  Res = _VAdd(Size * 2, 4, Res, VConstant);
+
+  // Now shift and narrow to convert 32-bit values to 16bit, storing the top 16bits
+  Res = _VUShrNI(Size * 2, 4, Res, 16);
+
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+template<uint8_t CompType>
+void OpDispatchBuilder::VPFCMPOp(OpcodeArgs) {
+  auto Size = GetSrcSize(Op);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
+
+  OrderedNode *Result{};
+  // This maps 1:1 to an AArch64 NEON Op
+  //auto ALUOp = _VCMPGT(Size, 4, Dest, Src);
+  LogMan::Msg::DFmt("CompType: {} Size: {}", CompType, Size);
+  switch (CompType) {
+    case 0x00: // EQ
+      Result = _VFCMPEQ(Size, 4, Dest, Src);
+    break;
+    case 0x01: // GE(Swapped operand)
+      Result = _VFCMPLE(Size, 4, Src, Dest);
+    break;
+    case 0x02: // GT
+      Result = _VFCMPGT(Size, 4, Dest, Src);
+    break;
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Comparison type: {}", CompType);
+    break;
+  }
+
+  StoreResult(FPRClass, Op, Result, -1);
+  ShouldDump = true;
+}
+
+template
+void OpDispatchBuilder::VPFCMPOp<0>(OpcodeArgs);
+template
+void OpDispatchBuilder::VPFCMPOp<1>(OpcodeArgs);
+template
+void OpDispatchBuilder::VPFCMPOp<2>(OpcodeArgs);
+
 void OpDispatchBuilder::PMADDWD(OpcodeArgs) {
  // This is a pretty curious operation
  // Does two MADD operations across 4 16bit signed integers and accumulates to 32bit integers in the destination
@@ -1804,7 +1971,7 @@ void OpDispatchBuilder::PMULHRSW(OpcodeArgs) {
    // Implementation is more efficient for 8byte registers
    Res = _VSMull(Size * 2, 2, Dest, Src);
    Res = _VSShrI(Size * 2, 4, Res, 14);
-    auto OneVector = _VectorImm(1, Size * 2, 4);
+    auto OneVector = _VectorImm(Size * 2, 4, 1);
    Res = _VAdd(Size * 2, 4, Res, OneVector);
    Res = _VUShrNI(Size * 2, 4, Res, 1);
  }
@@ -1818,7 +1985,7 @@ void OpDispatchBuilder::PMULHRSW(OpcodeArgs) {

    ResultLow = _VSShrI(Size, 4, ResultLow, 14);
    ResultHigh = _VSShrI(Size, 4, ResultHigh, 14);
-    auto OneVector = _VectorImm(1, Size, 4);
+    auto OneVector = _VectorImm(Size, 4, 1);

    ResultLow = _VAdd(Size, 4, ResultLow, OneVector);
    ResultHigh = _VAdd(Size, 4, ResultHigh, OneVector);
@@ -2073,10 +2240,10 @@ void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) {
       CurrentElementSize != DstElementSize;
       CurrentElementSize <<= 1) {
    if constexpr (Signed) {
-      Result = _VSXTL(Result, Size, CurrentElementSize);
+      Result = _VSXTL(Size, CurrentElementSize, Result);
    }
    else {
-      Result = _VUXTL(Result, Size, CurrentElementSize);
+      Result = _VUXTL(Size, CurrentElementSize, Result);
    }
  }
  StoreResult(FPRClass, Op, Result, -1);
@@ -2110,7 +2277,7 @@ void OpDispatchBuilder::ExtendVectorElements<4, 8, true>(OpcodeArgs);

 template<size_t ElementSize, bool Scalar>
 void OpDispatchBuilder::VectorRound(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint64_t Mode = Op->Src[1].Data.Literal.Value;
  uint64_t RoundControlSource = (Mode >> 2) & 1;
  uint64_t RoundControl = Mode & 0b11;
@@ -2130,7 +2297,7 @@ void OpDispatchBuilder::VectorRound(OpcodeArgs) {
    FEXCore::IR::Round_Host,
  };

-  Src = _Vector_FToI(Src, SourceModes[(RoundControlSource << 2) | RoundControl], Size, ElementSize);
+  Src = _Vector_FToI(Size, ElementSize, Src, SourceModes[(RoundControlSource << 2) | RoundControl]);

  if constexpr (Scalar) {
    // Insert the lower bits
@@ -2155,7 +2322,7 @@ void OpDispatchBuilder::VectorRound<8, true>(OpcodeArgs);

 template<size_t ElementSize>
 void OpDispatchBuilder::VectorBlend(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint8_t Select = Op->Src[1].Data.Literal.Value;

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
@@ -2184,13 +2351,14 @@ void OpDispatchBuilder::VectorVariableBlend(OpcodeArgs) {
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);

  // The mask is hardcoded to be xmm0 in this instruction
-  OrderedNode *Mask = _LoadContext(16, offsetof(FEXCore::Core::CPUState, xmm[0]), FPRClass);
+  OrderedNode *Mask = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[0]));
  // Each element is selected by the high bit of that element size
  // Dest[ElementIdx] = Xmm0[ElementIndex][HighBit] ? Src : Dest;
  //
  // To emulate this on AArch64
  // Arithmetic shift right by the element size, then use BSL to select the registers
  Mask = _VSShrI(Size, ElementSize, Mask, (ElementSize * 8) - 1);
+
  auto Result = _VBSL(Mask, Src, Dest);

  StoreResult(FPRClass, Op, Result, -1);
@@ -2203,13 +2371,16 @@ template
 void OpDispatchBuilder::VectorVariableBlend<8>(OpcodeArgs);

 void OpDispatchBuilder::PTestOp(OpcodeArgs) {
+  // Invalidate deferred flags early
+  InvalidateDeferredFlags();
+
  auto Size = GetSrcSize(Op);

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);

-  OrderedNode *Test1 = _VAnd(Dest, Src, Size, 1);
-  OrderedNode *Test2 = _VBic(Src, Dest, Size, 1);
+  OrderedNode *Test1 = _VAnd(Size, 1, Dest, Src);
+  OrderedNode *Test2 = _VBic(Size, 1, Src, Dest);

  Test1 = _VPopcount(Size, 1, Test1);
  Test2 = _VPopcount(Size, 1, Test2);
@@ -2231,8 +2402,14 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
  Test2 = _Select(FEXCore::IR::COND_EQ,
      Test2, ZeroConst, OneConst, ZeroConst);

+  // Careful, these flags are different between {V,}PTEST and VTESTP{S,D}
  SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(Test1);
  SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Test2);
+
+  SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(ZeroConst);
+  SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(ZeroConst);
 }

 void OpDispatchBuilder::PHMINPOSUWOp(OpcodeArgs) {
@@ -2265,17 +2442,17 @@ void OpDispatchBuilder::PHMINPOSUWOp(OpcodeArgs) {
  }

  // Insert the minimum in to bits [15:0]
-  OrderedNode *Result = _VMov(Min, 2);
+  OrderedNode *Result = _VMov(2, Min);

  // Insert position in to bits [18:16]
-  Result = _VInsGPR(16, 2, Result, Pos, 1);
+  Result = _VInsGPR(16, 2, 1, Result, Pos);

  StoreResult(FPRClass, Op, Result, -1);
 }

 template<size_t ElementSize>
 void OpDispatchBuilder::DPPOp(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint8_t Mask = Op->Src[1].Data.Literal.Value;
  uint8_t SrcMask = Mask >> 4;
  uint8_t DstMask = Mask & 0xF;
@@ -2323,7 +2500,7 @@ template
 void OpDispatchBuilder::DPPOp<8>(OpcodeArgs);

 void OpDispatchBuilder::MPSADBWOp(OpcodeArgs) {
-  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
  uint8_t Select = Op->Src[1].Data.Literal.Value;

  // Src1 needs to be in byte offset
@@ -10,6 +10,7 @@ $end_info$
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/IR/IREmitter.h>

@@ -24,26 +25,26 @@ class OrderedNode;
 OrderedNode *OpDispatchBuilder::GetX87Top() {
  // Yes, we are storing 3 bits in a single flag register.
  // Deal with it
-  return _LoadContext(1, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC, GPRClass);
+  return _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC);
 }

-void OpDispatchBuilder::SetX87TopTag(OrderedNode *Value, uint32_t Tag) {
+void OpDispatchBuilder::SetX87TopTag(OrderedNode *Value, X87Tag Tag) {
  // if we are popping then we must first mark this location as empty
-  auto FTW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FTW), GPRClass);
+  auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
  OrderedNode *Mask = _Constant(0b11);
  auto TopOffset = _Lshl(Value, _Constant(1));
  Mask = _Lshl(Mask, TopOffset);
  OrderedNode *NewFTW = _Andn(FTW, Mask);
-  if (Tag != 0) {
-    auto TagVal = _Lshl(_Constant(Tag), TopOffset);
+  if (Tag != X87Tag::Valid) {
+    auto TagVal = _Lshl(_Constant(ToUnderlying(Tag)), TopOffset);
    NewFTW = _Or(NewFTW, TagVal);
  }

-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), NewFTW);
+  _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
 }

 OrderedNode *OpDispatchBuilder::GetX87FTW(OrderedNode *Value) {
-  auto FTW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FTW), GPRClass);
+  auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
  OrderedNode *Mask = _Constant(0b11);
  auto TopOffset = _Lshl(Value, _Constant(1));
  auto NewFTW = _Lshr(FTW, TopOffset);
@@ -51,7 +52,7 @@ OrderedNode *OpDispatchBuilder::GetX87FTW(OrderedNode *Value) {
 }

 void OpDispatchBuilder::SetX87Top(OrderedNode *Value) {
-  _StoreContext(GPRClass, 1, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC, Value);
+  _StoreContext(1, GPRClass, Value, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC);
 }

 template<size_t width>
@@ -72,7 +73,7 @@ void OpDispatchBuilder::FLD(OpcodeArgs) {
    // Implicit arg
    auto offset = _Constant(Op->OP & 7);
    data = _And(_Add(orig_top, offset), mask);
-    data = _LoadContextIndexed(data, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    data = _LoadContextIndexed(data, 16, MMBaseOffset(), 16, FPRClass);
  }
  OrderedNode *converted = data;

@@ -82,10 +83,10 @@ void OpDispatchBuilder::FLD(OpcodeArgs) {
  }

  auto top = _And(_Sub(orig_top, _Constant(1)), mask);
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);
  // Write to ST[TOP]
-  _StoreContextIndexed(converted, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass);
  //_StoreContext(converted, 16, offsetof(FEXCore::Core::CPUState, mm[7][0]));
 }

@@ -101,25 +102,25 @@ void OpDispatchBuilder::FBLD(OpcodeArgs) {
  auto orig_top = GetX87Top();
  auto mask = _Constant(7);
  auto top = _And(_Sub(orig_top, _Constant(1)), mask);
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

  // Read from memory
  OrderedNode *data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], 16, Op->Flags, -1);
  OrderedNode *converted = _F80BCDLoad(data);
-  _StoreContextIndexed(converted, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FBSTP(OpcodeArgs) {
  auto orig_top = GetX87Top();
-  auto data = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);

  OrderedNode *converted = _F80BCDStore(data);

  StoreResult_WithOpSize(FPRClass, Op, Op->Dest, converted, 10, 1);

  // if we are popping then we must first mark this location as empty
-  SetX87TopTag(orig_top, TAG_EMPTY);
+  SetX87TopTag(orig_top, X87Tag::Empty);
  auto top = _And(_Add(orig_top, _Constant(1)), _Constant(7));
  SetX87Top(top);
 }
@@ -129,15 +130,15 @@ void OpDispatchBuilder::FLD_Const(OpcodeArgs) {
  // Update TOP
  auto orig_top = GetX87Top();
  auto top = _And(_Sub(orig_top, _Constant(1)), _Constant(7));
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

  auto low = _Constant(Lower);
  auto high = _Constant(Upper);
  OrderedNode *data = _VCastFromGPR(16, 8, low);
-  data = _VInsGPR(16, 8, data, high, 1);
+  data = _VInsGPR(16, 8, 1, data, high);
  // Write to ST[TOP]
-  _StoreContextIndexed(data, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(data, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -159,7 +160,7 @@ void OpDispatchBuilder::FILD(OpcodeArgs) {
  // Update TOP
  auto orig_top = GetX87Top();
  auto top = _And(_Sub(orig_top, _Constant(1)), _Constant(7));
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

  size_t read_width = GetSrcSize(Op);
@@ -190,24 +191,24 @@ void OpDispatchBuilder::FILD(OpcodeArgs) {
  converted = _VInsElement(16, 8, 1, 0, converted, _VCastFromGPR(16, 8, upper));

  // Write to ST[TOP]
-  _StoreContextIndexed(converted, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 template<size_t width>
 void OpDispatchBuilder::FST(OpcodeArgs) {
  auto orig_top = GetX87Top();
-  auto data = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
  if constexpr (width == 80) {
    StoreResult_WithOpSize(FPRClass, Op, Op->Dest, data, 10, 1);
  }
  else if constexpr (width == 32 || width == 64) {
-    auto result = _F80CVT(data, width / 8);
+    auto result = _F80CVT(width / 8, data);
    StoreResult_WithOpSize(FPRClass, Op, Op->Dest, result, width / 8, 1);
  }

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(orig_top, TAG_EMPTY);
+    SetX87TopTag(orig_top, X87Tag::Empty);
    // Set the new top now
    auto top = _And(_Add(orig_top, _Constant(1)), _Constant(7));
    SetX87Top(top);
@@ -226,14 +227,14 @@ void OpDispatchBuilder::FIST(OpcodeArgs) {
  auto Size = GetSrcSize(Op);

  auto orig_top = GetX87Top();
-  OrderedNode *data = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  data = _F80CVTInt(data, Truncate, Size);
+  OrderedNode *data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  data = _F80CVTInt(Size, data, Truncate);

  StoreResult_WithOpSize(GPRClass, Op, Op->Dest, data, Size, 1);

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(orig_top, TAG_EMPTY);
+    SetX87TopTag(orig_top, X87Tag::Empty);
    // Set the new top now
    auto top = _And(_Add(orig_top, _Constant(1)), _Constant(7));
    SetX87Top(top);
@@ -274,22 +275,22 @@ void OpDispatchBuilder::FADD(OpcodeArgs) {
    if constexpr (ResInST0 == OpResult::RES_STI) {
      StackLocation = arg;
    }
-    b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  }

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
  auto result = _F80Add(a, b);

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now
    top = _And(_Add(top, _Constant(1)), mask);
    SetX87Top(top);
  }

  // Write to ST[TOP]
-  _StoreContextIndexed(result, StackLocation, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -336,23 +337,23 @@ void OpDispatchBuilder::FMUL(OpcodeArgs) {
      StackLocation = arg;
    }

-    b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  }

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80Mul(a, b);

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now
    top = _And(_Add(top, _Constant(1)), mask);
    SetX87Top(top);
  }

  // Write to ST[TOP]
-  _StoreContextIndexed(result, StackLocation, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -399,10 +400,10 @@ void OpDispatchBuilder::FDIV(OpcodeArgs) {
      StackLocation = arg;
    }

-    b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  }

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  OrderedNode *result{};
  if constexpr (reverse) {
@@ -414,14 +415,14 @@ void OpDispatchBuilder::FDIV(OpcodeArgs) {

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now
    top = _And(_Add(top, _Constant(1)), mask);
    SetX87Top(top);
  }

  // Write to ST[TOP]
-  _StoreContextIndexed(result, StackLocation, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -483,10 +484,10 @@ void OpDispatchBuilder::FSUB(OpcodeArgs) {
    if constexpr (ResInST0 == OpResult::RES_STI) {
      StackLocation = arg;
    }
-    b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  }

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  OrderedNode *result{};
  if constexpr (reverse) {
@@ -498,7 +499,7 @@ void OpDispatchBuilder::FSUB(OpcodeArgs) {

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now

    top = _And(_Add(top, _Constant(1)), mask);
@@ -506,7 +507,7 @@ void OpDispatchBuilder::FSUB(OpcodeArgs) {
  }

  // Write to ST[TOP]
-  _StoreContextIndexed(result, StackLocation, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -541,37 +542,37 @@ void OpDispatchBuilder::FSUB<32, true, true, OpDispatchBuilder::OpResult::RES_ST

 void OpDispatchBuilder::FCHS(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto low = _Constant(0);
  auto high = _Constant(0b1'000'0000'0000'0000ULL);
  OrderedNode *data = _VCastFromGPR(16, 8, low);
-  data = _VInsGPR(16, 8, data, high, 1);
+  data = _VInsGPR(16, 8, 1, data, high);

-  auto result = _VXor(a, data, 16, 1);
+  auto result = _VXor(16, 1, a, data);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FABS(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto low = _Constant(~0ULL);
  auto high = _Constant(0b0'111'1111'1111'1111ULL);
  OrderedNode *data = _VCastFromGPR(16, 8, low);
-  data = _VInsGPR(16, 8, data, high, 1);
+  data = _VInsGPR(16, 8, 1, data, high);

-  auto result = _VAnd(a, data, 16, 1);
+  auto result = _VAnd(16, 1, a, data);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FTST(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto low = _Constant(0);
  OrderedNode *data = _VCastFromGPR(16, 8, low);
@@ -595,35 +596,35 @@ void OpDispatchBuilder::FTST(OpcodeArgs) {

 void OpDispatchBuilder::FRNDINT(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80Round(a);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FXTRACT(OpcodeArgs) {
  auto orig_top = GetX87Top();
  auto top = _And(_Sub(orig_top, _Constant(1)), _Constant(7));
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

-  auto a = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);

  auto exp = _F80XTRACT_EXP(a);
  auto sig = _F80XTRACT_SIG(a);

  // Write to ST[TOP]
-  _StoreContextIndexed(exp, orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  _StoreContextIndexed(sig, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(exp, orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  _StoreContextIndexed(sig, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FNINIT(OpcodeArgs) {
-  // Init FCW to 0x037
-  auto NewFCW = _Constant(16, 0x037);
+  // Init FCW to 0x037F
+  auto NewFCW = _Constant(16, 0x037F);
  _F80LoadFCW(NewFCW);
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FCW), NewFCW);
+  _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));

  // Init FSW to 0
  SetX87Top(_Constant(0));
@@ -634,7 +635,7 @@ void OpDispatchBuilder::FNINIT(OpcodeArgs) {
  SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(_Constant(0));

  // Tags all get set to 0b11
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), _Constant(0xFFFF));
+  _StoreContext(2, GPRClass, _Constant(0xFFFF), offsetof(FEXCore::Core::CPUState, FTW));
 }

 template<size_t width, bool Integer, OpDispatchBuilder::FCOMIFlags whichflags, bool poptwice>
@@ -661,10 +662,10 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) {
    // Implicit arg
    auto offset = _Constant(Op->OP & 7);
    arg = _And(_Add(top, offset), mask);
-    b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  }

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  OrderedNode *Res = _F80Cmp(a, b,
    (1 << FCMP_FLAG_EQ) |
@@ -684,24 +685,27 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) {
    SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(HostFlag_ZF);
  }
  else {
+    // Invalidate deferred flags early
+    // OF, SF, AF, PF all undefined
+    InvalidateDeferredFlags();
+
    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
  }

-
  if constexpr (poptwice) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    top = _And(_Add(top, _Constant(1)), mask);
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now
    top = _And(_Add(top, _Constant(1)), mask);
    SetX87Top(top);
  }
  else if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    // Set the new top now
    top = _And(_Add(top, _Constant(1)), mask);
    SetX87Top(top);
@@ -738,12 +742,12 @@ void OpDispatchBuilder::FXCH(OpcodeArgs) {
  auto offset = _Constant(Op->OP & 7);
  arg = _And(_Add(top, offset), mask);

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  auto b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
+  auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);

  // Write to ST[TOP]
-  _StoreContextIndexed(b, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  _StoreContextIndexed(a, arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(b, top, 16, MMBaseOffset(), 16, FPRClass);
+  _StoreContextIndexed(a, arg, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::FST(OpcodeArgs) {
@@ -756,14 +760,14 @@ void OpDispatchBuilder::FST(OpcodeArgs) {
  auto offset = _Constant(Op->OP & 7);
  arg = _And(_Add(top, offset), mask);

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  // Write to ST[TOP]
-  _StoreContextIndexed(a, arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(a, arg, 16, MMBaseOffset(), 16, FPRClass);

  if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
    // if we are popping then we must first mark this location as empty
-    SetX87TopTag(top, TAG_EMPTY);
+    SetX87TopTag(top, X87Tag::Empty);
    top = _And(_Add(top, _Constant(1)), _Constant(7));
    SetX87Top(top);
  }
@@ -772,14 +776,14 @@ void OpDispatchBuilder::FST(OpcodeArgs) {
 template<FEXCore::IR::IROps IROp>
 void OpDispatchBuilder::X87UnaryOp(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80Round(a);
  // Overwrite the op
  result.first->Header.Op = IROp;

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -798,8 +802,8 @@ void OpDispatchBuilder::X87BinaryOp(OpcodeArgs) {
  auto mask = _Constant(7);
  OrderedNode *st1 = _And(_Add(top, _Constant(1)), mask);

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  st1 = _LoadContextIndexed(st1, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
+  st1 = _LoadContextIndexed(st1, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80Add(a, st1);
  // Overwrite the op
@@ -811,7 +815,7 @@ void OpDispatchBuilder::X87BinaryOp(OpcodeArgs) {
  }

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 template
@@ -842,17 +846,17 @@ void OpDispatchBuilder::X87ModifySTP<true>(OpcodeArgs);
 void OpDispatchBuilder::X87SinCos(OpcodeArgs) {
  auto orig_top = GetX87Top();
  auto top = _And(_Sub(orig_top, _Constant(1)), _Constant(7));
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

-  auto a = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);

  auto sin = _F80SIN(a);
  auto cos = _F80COS(a);

  // Write to ST[TOP]
-  _StoreContextIndexed(sin, orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  _StoreContextIndexed(cos, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(sin, orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  _StoreContextIndexed(cos, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87FYL2X(OpcodeArgs) {
@@ -860,61 +864,61 @@ void OpDispatchBuilder::X87FYL2X(OpcodeArgs) {

  auto orig_top = GetX87Top();
  // if we are popping then we must first mark this location as empty
-  SetX87TopTag(orig_top, TAG_EMPTY);
+  SetX87TopTag(orig_top, X87Tag::Empty);
  auto top = _And(_Add(orig_top, _Constant(1)), _Constant(7));
  SetX87Top(top);

-  OrderedNode *st0 = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  OrderedNode *st1 = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  OrderedNode *st0 = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  OrderedNode *st1 = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  if (Plus1) {
    auto low = _Constant(0x8000'0000'0000'0000ULL);
    auto high = _Constant(0b0'011'1111'1111'1111);
    OrderedNode *data = _VCastFromGPR(16, 8, low);
-    data = _VInsGPR(16, 8, data, high, 1);
+    data = _VInsGPR(16, 8, 1, data, high);
    st0 = _F80Add(st0, data);
  }

  auto result = _F80FYL2X(st0, st1);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87TAN(OpcodeArgs) {
  auto orig_top = GetX87Top();
  auto top = _And(_Sub(orig_top, _Constant(1)), _Constant(7));
-  SetX87TopTag(top, TAG_VALID);
+  SetX87TopTag(top, X87Tag::Valid);
  SetX87Top(top);

-  auto a = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80TAN(a);

  auto low = _Constant(0x8000'0000'0000'0000ULL);
  auto high = _Constant(0b0'011'1111'1111'1111ULL);
  OrderedNode *data = _VCastFromGPR(16, 8, low);
-  data = _VInsGPR(16, 8, data, high, 1);
+  data = _VInsGPR(16, 8, 1, data, high);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  _StoreContextIndexed(data, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  _StoreContextIndexed(data, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87ATAN(OpcodeArgs) {
  auto orig_top = GetX87Top();
  // if we are popping then we must first mark this location as empty
-  SetX87TopTag(orig_top, TAG_EMPTY);
+  SetX87TopTag(orig_top, X87Tag::Empty);
  auto top = _And(_Add(orig_top, _Constant(1)), _Constant(7));
  SetX87Top(top);

-  auto a = _LoadContextIndexed(orig_top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  OrderedNode *st1 = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
+  OrderedNode *st1 = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);

  auto result = _F80ATAN(st1, a);

  // Write to ST[TOP]
-  _StoreContextIndexed(result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87LDENV(OpcodeArgs) {
@@ -924,7 +928,7 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) {

  auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2);
  _F80LoadFCW(NewFCW);
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FCW), NewFCW);
+  _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));

  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
  auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
@@ -947,7 +951,7 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
    auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
-    _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), NewFTW);
+    _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
  }
 }

@@ -976,7 +980,7 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) {
  Mem = AppendSegmentOffset(Mem, Op->Flags);

  {
-    auto FCW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FCW), GPRClass);
+    auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW));
    _StoreMem(GPRClass, Size, Mem, FCW, Size);
  }

@@ -1004,7 +1008,7 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) {
  {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
-    auto FTW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FTW), GPRClass);
+    auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
    _StoreMem(GPRClass, Size, MemLocation, FTW, Size);
  }

@@ -1036,11 +1040,11 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) {
 void OpDispatchBuilder::X87FLDCW(OpcodeArgs) {
  OrderedNode *NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
  _F80LoadFCW(NewFCW);
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FCW), NewFCW);
+  _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 }

 void OpDispatchBuilder::X87FSTCW(OpcodeArgs) {
-  auto FCW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FCW), GPRClass);
+  auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW));

  StoreResult(GPRClass, Op, FCW, -1);
 }
@@ -1107,7 +1111,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {

  OrderedNode *Top = GetX87Top();
  {
-    auto FCW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FCW), GPRClass);
+    auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW));
    _StoreMem(GPRClass, Size, Mem, FCW, Size);
  }

@@ -1134,7 +1138,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
  {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
-    auto FTW = _LoadContext(2, offsetof(FEXCore::Core::CPUState, FTW), GPRClass);
+    auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
    _StoreMem(GPRClass, Size, MemLocation, FTW, Size);
  }

@@ -1168,14 +1172,14 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
  auto SevenConst = _Constant(7);
  auto TenConst = _Constant(10);
  for (int i = 0; i < 7; ++i) {
-    auto data = _LoadContextIndexed(Top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass);
    _StoreMem(FPRClass, 16, ST0Location, data, 1);
    ST0Location = _Add(ST0Location, TenConst);
    Top = _And(_Add(Top, OneConst), SevenConst);
  }

  // The final st(7) needs a bit of special handling here
-  auto data = _LoadContextIndexed(Top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass);
  // ST7 broken in to two parts
  // Lower 64bits [63:0]
  // upper 16 bits [79:64]
@@ -1195,7 +1199,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {

  auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2);
  _F80LoadFCW(NewFCW);
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FCW), NewFCW);
+  _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));

  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
  auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
@@ -1218,7 +1222,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
    // FTW
    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
    auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
-    _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), NewFTW);
+    _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
  }

  OrderedNode *ST0Location = _Add(Mem, _Constant(Size * 7));
@@ -1230,14 +1234,14 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
  auto low = _Constant(~0ULL);
  auto high = _Constant(0xFFFF);
  OrderedNode *Mask = _VCastFromGPR(16, 8, low);
-  Mask = _VInsGPR(16, 8, Mask, high, 1);
+  Mask = _VInsGPR(16, 8, 1, Mask, high);

  for (int i = 0; i < 7; ++i) {
    OrderedNode *Reg = _LoadMem(FPRClass, 16, ST0Location, 1);
    // Mask off the top bits
    Reg = _VAnd(16, 16, Reg, Mask);

-    _StoreContextIndexed(Reg, Top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+    _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass);

    ST0Location = _Add(ST0Location, TenConst);
    Top = _And(_Add(Top, OneConst), SevenConst);
@@ -1252,12 +1256,12 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
  ST0Location = _Add(ST0Location, _Constant(8));
  OrderedNode *RegHigh = _LoadMem(FPRClass, 2, ST0Location, 1);
  Reg = _VInsElement(16, 2, 4, 0, Reg, RegHigh);
-  _StoreContextIndexed(Reg, Top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87FXAM(OpcodeArgs) {
  auto top = GetX87Top();
-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
  OrderedNode *Result = _VExtractToGPR(16, 8, a, 1);

  // Extract the sign bit
@@ -1333,7 +1337,7 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
    Type = COMPARE_ZERO;
  break;
  default:
-    LOGMAN_MSG_A("Unhandled FCMOV op: 0x%x", Opcode);
+    LOGMAN_MSG_A_FMT("Unhandled FCMOV op: 0x{:x}", Opcode);
  break;
  }

@@ -1358,7 +1362,7 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
  SrcCond = _Sbfe(1, 0, SrcCond);

  OrderedNode *VecCond = _VCastFromGPR(16, 8, SrcCond);
-  VecCond = _VInsGPR(16, 8, VecCond, SrcCond, 1);
+  VecCond = _VInsGPR(16, 8, 1, VecCond, SrcCond);

  auto top = GetX87Top();
  OrderedNode* arg;
@@ -1369,17 +1373,17 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
  auto offset = _Constant(Op->OP & 7);
  arg = _And(_Add(top, offset), mask);

-  auto a = _LoadContextIndexed(top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
-  auto b = _LoadContextIndexed(arg, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
+  auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
  auto Result = _VBSL(VecCond, b, a);

  // Write to ST[TOP]
-  _StoreContextIndexed(Result, top, 16, offsetof(FEXCore::Core::CPUState, mm[0][0]), 16, FPRClass);
+  _StoreContextIndexed(Result, top, 16, MMBaseOffset(), 16, FPRClass);
 }

 void OpDispatchBuilder::X87EMMS(OpcodeArgs) {
  // Tags all get set to 0b11
-  _StoreContext(GPRClass, 2, offsetof(FEXCore::Core::CPUState, FTW), _Constant(0xFFFF));
+  _StoreContext(2, GPRClass, _Constant(0xFFFF), offsetof(FEXCore::Core::CPUState, FTW));
 }

 void OpDispatchBuilder::X87FFREE(OpcodeArgs) {
@@ -1391,7 +1395,7 @@ void OpDispatchBuilder::X87FFREE(OpcodeArgs) {
  top = _And(_Add(top, offset), _Constant(7));

  // Set this argument's tag as empty now
-  SetX87TopTag(top, TAG_EMPTY);
+  SetX87TopTag(top, X87Tag::Empty);
 }

 }