steam-frame/FEX-Emu--FEX
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Code Issues Packages Projects Releases 67 Wiki Activity
1,443 Commits 11 Branches 71 Tags
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Commit Graph
551 Commits
Author SHA1 Message Date
Ryan Houdek 31be022348 Fixes bad implementation in fallback x86 LZCNT 
This was just wrong and the unit tests hadn't caught it
 2020-10-04 16:13:03 -07:00
Ryan Houdek 4ff7046ddb Fixes bugs in PSHUFB 
If bits were set in the reserved bits then the shuffle was incorrect
 2020-10-04 16:10:03 -07:00
Ryan Houdek d9414ee8ad Implements SSE2 MOVNTPD 
We apparently missed this one
 2020-10-04 16:09:15 -07:00
Ryan Houdek 6287e769be Splits x86 JIT's IR handling over to a jump table 
This is changes the behaviour to be exactly like the ARM64 side.
No behaviour change beyond that.
 2020-09-30 13:35:00 -07:00
Stefanos Kornilios Mitsis Poiitidis c7615bf560 Merge pull request #447 from Sonicadvance1/aes_ext 
Implements support for the AES instructions
 2020-09-30 20:02:17 +03:00
Stefanos Kornilios Mitsis Poiitidis 56f47395db Merge pull request #446 from Sonicadvance1/umul_fix 
Fixes unsigned multiply zext mechanics
 2020-09-30 19:49:49 +03:00
Ryan Houdek 99a344ac62 Allows CPUID to only report AES support if the host supports it 2020-09-30 00:05:55 -07:00
Ryan Houdek 7e264533cf Implements the AES instructions in the Opcode dispatcher 2020-09-30 00:05:55 -07:00
Ryan Houdek aa8da5d70d Adds AES IR ops to the x86_64 JIT 2020-09-30 00:05:55 -07:00
Ryan Houdek 3e7407fa09 Adds AES IR ops to the Arm64 JIT 2020-09-30 00:05:55 -07:00
Ryan Houdek a26f5c0cc5 Adds AES IR ops to the interpreter 2020-09-30 00:05:55 -07:00
Ryan Houdek 30b4a645af Adds the AES extensions to the tables 2020-09-29 23:47:53 -07:00
Ryan Houdek 10df2db7c9 Fixes a bug in the frontend decoder 
This table doesn't listen to REX itself but just REX widening
Necessary to decode AESKeyGenAssist correctly
 2020-09-29 23:46:09 -07:00
Ryan Houdek cf72f998f8 Add common location to see host features 
Only necessary to pick up AES at the moment
 2020-09-29 23:45:13 -07:00
Ryan Houdek 77511c5f92 Fixes unsigned multiply zext mechanics 
32bit wasn't zexting correctly
 2020-09-29 16:37:46 -07:00
Ryan Houdek 05d43945a6 Fixes a bug in 32bit signed multiply on x86_64 jit 
We were storing the zexted result instead of the sexted result
 2020-09-29 12:33:33 -07:00
Ryan Houdek 5c518dd96e Fixes flags calculation for signed multiply 
Resulting high bits needed to be sexted to do the proper flags check
 2020-09-29 12:33:33 -07:00
Stefanos Kornilios Mitsis Poiitidis 5248991a14 Merge pull request #440 from Sonicadvance1/fix_insextr_index 
Ensures PEXTR and PINSR mask the element selection correctly
 2020-09-29 11:22:09 +03:00
Stefanos Kornilios Mitsis Poiitidis b9d004b639 Merge pull request #439 from Sonicadvance1/cmpxchg_edgecase 
Fixes edge case that wasn't covered in FEX's cmpxchg
 2020-09-29 11:20:45 +03:00
Stefanos Kornilios Mitsis Poiitidis ea99f661bf Merge pull request #444 from Sonicadvance1/shlrd_fixes 
Fixes 32bit SHLD and SHRD by zero
 2020-09-29 11:09:30 +03:00
Stefanos Kornilios Mitsis Poiitidis 227c2dc308 Merge pull request #441 from Sonicadvance1/vfcmp 
Fixes float compare with negated results
 2020-09-29 11:06:33 +03:00
Ryan Houdek fc093531c3 Fixes SHRD and SHRD by zero with 32bit source register 
This will still zext the GPR with zero shift, just won't update the
flags
 2020-09-28 16:58:26 -07:00
Ryan Houdek 912b6fb0f3 Merge pull request #442 from Sonicadvance1/ashr_fix 
Fixes smaller than 32bit ASHR
 2020-09-28 13:44:07 -07:00
Ryan Houdek f6c207b5c5 Fixes smaller than 32bit ASHR 
Need to operate on it as a 32bit value
 2020-09-27 23:11:58 -07:00
Ryan Houdek 5b8046e612 Fixes float compare with negated results 
We can't just flip the comparison because NaN changes behaviour here
 2020-09-27 19:11:34 -07:00
Ryan Houdek cef2f693a5 Ensures PEXTR and PINSR mask the element selection correctly 
Only uses the bitfield necessary for the size ofd the instruction
 2020-09-27 18:48:58 -07:00
Ryan Houdek 88f880650b Fixes edge case that wasn't covered in FEX's cmpxchg 
When the destination is a 32bit GPR, when the resulting compare failed
we were zexting the destination registeron accident.
Thus clearing the upper 32bits when it shouldn't have changed.
 2020-09-27 17:47:54 -07:00
Ryan Houdek d404da1bf1 Fixes PSADBW in the opdispatcher 
Documentation in the x86 manuals implied operating at 8bit
 2020-09-27 16:53:50 -07:00
Ryan Houdek b0b3335178 Fixes VADDV in the x86_64 JIT 2020-09-27 16:53:25 -07:00
Ryan Houdek a919e532fc Merge pull request #437 from Sonicadvance1/ssse3 
Enables SSSE3 in CPUID
 2020-09-27 11:15:15 -07:00
Ryan Houdek 603580f291 Implements PHADDSW and PHSUBSW in the opdispatcher 
Both the MMX and XMM variants
 2020-09-27 11:08:21 -07:00
Ryan Houdek b409855605 Implements PMADDUBSW in the Opdispatcher 
This is some weirdly specific instruction
 2020-09-27 10:50:35 -07:00
Ryan Houdek 1c2f8dece5 Fixes typo in x86 VUXTL2 
This was supposed to shift right, not shift left
This IR op wasn't being used so it went unnoticed
 2020-09-27 10:38:46 -07:00
Ryan Houdek badc7f6562 Merge pull request #434 from Sonicadvance1/pmulhrsw 
Implements SSSE3 PMULHRSW
 2020-09-27 10:38:14 -07:00
Ryan Houdek 6b3e1bd75b Implements PHADD and PHSUB in the OpDispatcher 2020-09-27 10:32:10 -07:00
Ryan Houdek 72d0dd30a6 Fixes 8byte register VAddP in the x86 JIT 2020-09-27 10:31:35 -07:00
Ryan Houdek 4f73897a7f Fixes 8byte register VaddP on AArch64 JIT 2020-09-27 10:31:35 -07:00
Ryan Houdek afa4f0df38 Enables SSSE3 in CPUID 2020-09-26 20:40:22 -07:00
Ryan Houdek da16b40e12 Implements PMULHRSW in the opdispatcher 
Both the MMX and XMM versions
 2020-09-26 15:32:21 -07:00
Ryan Houdek 315e909ed0 Implements new VectorImm in the x86 JIT 2020-09-26 15:31:18 -07:00
Ryan Houdek b30e517a0b Implements new VectorImm op in the AArch64 JIT 2020-09-26 15:31:05 -07:00
Ryan Houdek 820c10b439 Implements new VectorImm op in the interpreter 2020-09-26 15:30:43 -07:00
Ryan Houdek 58425637e2 Implements pshufb in the opdispatcher 
This hits both the MMX and XMM variants
 2020-09-26 13:08:31 -07:00
Ryan Houdek 91229c8ea2 Implements new VTBL1 IR op in x86 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek 59bffc7431 Implements new VTBL1 instruction in AArch64 JIT 2020-09-26 12:59:34 -07:00
Ryan Houdek a5f6a5b26e Implements new VTBL1 op in the interpreter 2020-09-26 12:59:34 -07:00
Ryan Houdek 55077cfa55 Implements MMX register based palignr 
We had already implemented the XMM variant
 2020-09-26 12:53:51 -07:00
Ryan Houdek 9cdd0c4776 Fixes an edge case in our palignr implementation 
When the shift amount is greater than the size of both the registers
then it'll set the resulting register to zero
 2020-09-26 12:53:51 -07:00
Ryan Houdek 12a4dd6d2d Fixes VExtr in the ARM64 JIT for 8byte registers 
We only expected 16byte registers before
 2020-09-26 12:52:26 -07:00
Ryan Houdek bd37d007c9 Fixes 64bit register usage in VExtr on x86_64 
We would need to fall back to MMX if we wanted to handle that cleanly
there.
Just emulate instead of using MMX
 2020-09-26 12:52:26 -07:00