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6,348 Commits 11 Branches 71 Tags
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Commit Graph
2547 Commits
Author SHA1 Message Date
Ryan Houdek aac4e25ca4 Merge pull request #2549 from Sonicadvance1/glibc_remaining_allocations 
Move FEX away from the remaining glibc allocations that we can
 2023-04-01 09:46:29 -07:00
Ryan Houdek 53bbbd5a4f Review code 2023-03-30 16:28:34 -07:00
Ryan Houdek 3eae668cec X86Jit: Fix xbyak allocating through glibc 2023-03-30 16:28:34 -07:00
Ryan Houdek b2ec28503d LookupCache: Move over to fextl::pmr 2023-03-30 16:28:33 -07:00
Ryan Houdek 170c9ee9e4 LookupCache: Switch to fextl 2023-03-30 16:28:33 -07:00
Ryan Houdek 1eb36b8b31 Convert a ton of things over to fextl 2023-03-30 16:28:33 -07:00
Mai df354e37dd Merge pull request #2578 from Sonicadvance1/support_salc 
OpcodeDispatcher: Implement support for 32-bit SALC instruction
 2023-03-30 18:12:15 -04:00
Ryan Houdek 43e6d398b6 X86Dispatcher: Move xbyak to custom types 2023-03-30 08:49:26 -07:00
Mai 88dba60bee Merge pull request #2579 from Sonicadvance1/invalid_instruction_log 
Core: Add a new log message for unsupported instruction
 2023-03-29 22:52:08 -04:00
Ryan Houdek d615ae9c6a Core: Add a new log message for unsupported instruction 
The previous log in the frontend is super useful when an instruction
decoding wasn't supported.
Now that most of AVX is covered, a game will crash on SIGILL (and
usually catch it) and close without any indication.

Now if the instruction is decoded but it is invalid for the
configuration, still output a message as a good indicator that the game
is using instructions that the host doesn't support.

Will let us still pick up on games crashing due to lack of SVE very
easily.
 2023-03-29 14:38:16 -07:00
Ryan Houdek 7629edcf61 OpcodeDispatcher: Implement support for 32-bit SALC instruction 
This is an undocumented but supported instruction. It behaves just like
an `sbb al, al` but doesn't set flags and is one byte shorter.

The end result is that al is set to 0xFF or 0 depending on if CF is set
or not.
 2023-03-29 14:34:51 -07:00
Lioncache 73d250c555 ARMEmitter: Handle SVE2 integer add/subtract wide category 2023-03-29 17:02:18 -04:00
Lioncache 337f8b06a3 ARMEmitter: Convert SVE2 integer multiply long to wide helper 
Unifies the emitted ops under the same underlying emitter function.
 2023-03-29 16:52:37 -04:00
Lioncache 87fa545bd0 ARMEmitter: Convert SVE2 integer add/subtract long to wide helper 
The generic helper will be used to implement the remaining unimplemented
category from this group
 2023-03-29 16:52:34 -04:00
Ryan Houdek 7747ac8de8 Merge pull request #2576 from lioncash/mul 
ARMEmitter: Handle SVE Integer Multiply-Add - Unpredicated group
 2023-03-29 13:14:29 -07:00
Lioncache deb1c9e933 ARMEmitter: Handle SVE mixed sign dot product category 2023-03-29 15:43:07 -04:00
Lioncache 672a88395d ARMEmitter: Handle SVE2 saturating multiply-add high category 2023-03-29 15:38:38 -04:00
Lioncache 88524ce718 ARMEmitter: Handle SVE2 saturating multiply-add long category 2023-03-29 15:33:49 -04:00
Lioncache bb153054f9 ARMEmitter: Handle SVE2 integer multiply-add long category 2023-03-29 15:28:32 -04:00
Lioncache 22a7a49042 ARMEmitter: Handle SVE2 complex integer multiply-add 2023-03-29 15:19:09 -04:00
Lioncache 9876f3eb5c ARMEmitter: Handle SVE2 saturating multiply-add interleaved long category 2023-03-29 15:08:30 -04:00
Lioncache b9e4ce4029 ARMEmitter: Handle SVE integer dot product (unpredicated) category 2023-03-29 14:55:06 -04:00
Lioncache 0c048772e0 ARMEmitter: Handle CDOT (vectors) 2023-03-29 14:54:35 -04:00
Lioncache 830c1884d1 OpcodeDispatcher: Handle store variants of VMASKMOVPD/VMASKMOVPS 
And with that, we support all of the AVX1-only instructions.

The remaining instructions for full AVX1 support is now just the SSE4.2
string instructions.
 2023-03-29 14:03:23 -04:00
Lioncache 5abf9de8a5 IR: Add VStoreVectorMasked IR op 
Will be used to implement the store variants of VPMASKMOV and
VMASKMOVP{D, S}
 2023-03-29 14:03:20 -04:00
Lioncache 25960fe6b1 OpcodeDispatcher: Handle load variants of VMASKMOVP{D, S} 2023-03-28 10:35:23 -04:00
Lioncache eb8626c1f7 IR: Add VLoadVectorMasked IR op 
Will be used to implement the load variants of VMASKMOVP{D, S} and
VPMASKMOV{D, Q}

Particularly useful, since with SVE this behavior can be collapsed into
two instructions (CMPGT followed by the relevant LD1 load instruction)
 2023-03-28 01:57:25 -04:00
Lioncache ef7853ca4a ARMEmitter: Fix treating 32-bit elements as 64-bit with ld1w 
These conditionals were accidentally inverted and were treating 32-bit
elements as 64-bit ones, when this is unintended.

Also add missing tests to ensure this doesn't slip through in the
future.
 2023-03-28 00:55:04 -04:00
Ryan Houdek 55d65f3aea Merge pull request #2570 from lioncash/mov 
Arm64/VectorOps: Remove a few unnecessary EORs from comparisons in SVE path
 2023-03-27 13:35:48 -07:00
Ryan Houdek 2c2abc550b Merge pull request #2569 from lioncash/psadbw 
OpcodeDispatcher: Handle VMPSADBW
 2023-03-27 13:31:52 -07:00
Lioncache a1dc132f03 Arm64/VectorOps: Eliminate unnecessary EOR and MOV in FP compares 
We can use the zeroing variant of MOVPRFX to perform the same behavior.
 2023-03-27 16:16:28 -04:00
Lioncache ef31e0c7c7 OpcodeDispatcher: Handle VMPSADBW 2023-03-27 16:00:24 -04:00
Lioncache eecd016ba8 Arm64/VectorOps: Eliminate unnecessary EOR and MOV in VCMP{EQ,GT} 
We can use the zeroing version of MOVPRFX to perform the same behavior.
 2023-03-27 15:38:03 -04:00
Lioncache b2ec6d5208 OpcodeDispatcher: Move MPSADBW implementation into helper 
This will be used for implementing the AVX variant of this instruction.
 2023-03-27 12:40:28 -04:00
Lioncache 416a7b825d ARMEmitter: Move SVE2IntegerSaturatingAddSub over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:42 -04:00
Lioncache c3511ffa48 ARMEmitter: Move SVEIntegerPairwiseArithmetic over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:42 -04:00
Lioncache b9c3277b09 ARMEmitter: Move SVE2IntegerHalvingPredicated over to using SVE2IntegerPredicated helper 
Deduplicates some code.
 2023-03-27 12:21:38 -04:00
Lioncache 09f259c458 ARMEmitter: Handle SVE2 saturating/rounding bitwise shift left (predicated) category 2023-03-27 11:58:02 -04:00
Lioncache 7a2d23e189 ARMEmitter: Handle SVE2 integer unary operations (predicated) category 2023-03-27 11:36:06 -04:00
Lioncache 1e10561892 ARMEmitter: Handle SVE2 integer pairwise add accumulate long category 2023-03-27 11:22:39 -04:00
Ryan Houdek 9183cf144f Merge pull request #2547 from Sonicadvance1/standard_string_theory_versus_fex 
Convert most std::string over to fextl
 2023-03-24 04:37:40 -07:00
Ryan Houdek 043a03547f Resolve review comments 2023-03-24 04:09:03 -07:00
Ryan Houdek 7022b3b825 Review c_str() changes 2023-03-23 12:45:14 -07:00
Lioncache dfeee6a1ed Arm64/VectorOps: Fix comment typo in VUShr 
Meant to write USHL here, rather than SSHL
 2023-03-21 22:25:34 -04:00
Lioncache 91d6dc0528 Arm64/VectorOps: Handle 64-bit elements in VSShr 
Makes it consistent with all of the other variable shift IR ops.

Now this won't explode if we ever implement VPSRAVQ from AVX-512
 2023-03-21 22:23:12 -04:00
Ryan Houdek 54e784742c Merge pull request #2558 from lioncash/shift 
OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ
 2023-03-21 15:15:40 -07:00
Ryan Houdek 22936144ce Merge pull request #2557 from lioncash/pred 
ARMEmitter: Handle SVE Inc/Dec by Predicate Count category
 2023-03-21 15:12:39 -07:00
Lioncache fea0162096 OpcodeDispatcher: Handle VPSLLVD/VPSLLVQ 2023-03-21 17:08:03 -04:00
Lioncache 8287375117 x86_64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:57:48 -04:00
Lioncache 0106f03b44 Arm64/VectorOps: Implement VUShl IR op 
This will be used to implement VPSLLVD/VPSLLVQ
 2023-03-21 16:55:33 -04:00