Ryan Houdek
8c1f2eb0b3
Merge pull request #870 from FEX-Emu/skmp/lock-validation
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OpDisp: Validate LOCK handling, add missing segment offsets
2021-03-20 15:53:06 -07:00
Stefanos Kornilios Mitsis Poiitidis
d120f12c93
X87: Init on X87FNSAVE, fix FNINIT
2021-03-19 17:04:51 +02:00
Stefanos Kornilios Mitsis Poiitidis
695322d446
OpDisp: Validate LOCK handling, add missing segment offsets
2021-03-19 16:32:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
a7dc9d00d2
Merge pull request #864 from Sonicadvance1/cpuid_15h
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Implements CPUID 15h
2021-03-19 10:02:02 +02:00
Ryan Houdek
c7f265158f
Implements CPUID 15h
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ARMv8 allows you query the cycle counter register very from userspace which allows us to emulate this easily.
My IceLake device returns 1.5Ghz through this interface
My AMD Zen+ device doesn't support this but with measurements has 3Ghz TSC
My Snapdragon 865 device has a TSC frequency of 19.20Mhz
2021-03-18 01:42:44 -07:00
Ryan Houdek
fbf5325bdd
Enables Invariant TSC CPUID bit
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I keep forgetting to enable this bit. Fixes #855
2021-03-18 00:15:48 -07:00
Ryan Houdek
0c5e5dbdf2
Removes warnings from OpcodeDispatcher
2021-03-14 13:27:39 -07:00
Ryan Houdek
d8591a8f14
Removes warnings from x86 JITCore
2021-03-14 13:27:39 -07:00
Ryan Houdek
941107120c
Removes warnings from x86 BranchOps
2021-03-14 13:27:39 -07:00
Ryan Houdek
ffc17c90c5
Removes warnings from InterpreterOps
2021-03-14 13:27:39 -07:00
Scott Mansell
5e1e09a43d
Fix review issues
2021-03-15 04:41:14 +13:00
Scott Mansell
42b186a76c
Don't generate a default vixl::codebuffer
2021-03-12 12:47:29 +13:00
Scott Mansell
bdca7109a4
Force XBYAK64
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Because XBYAK's autoconfig doesn't quite do the right thing
2021-03-11 23:46:07 +13:00
Scott Mansell
074bedf25c
Automatically use correct ContextBackup type
2021-03-11 23:46:07 +13:00
Scott Mansell
bdb199b6d6
Unify all four dispatchers
2021-03-11 23:46:07 +13:00
Ryan Houdek
c73d2b2bca
Merge pull request #843 from Sonicadvance1/locked_not
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Adds support for locked NOT
2021-03-11 00:47:01 -08:00
Ryan Houdek
8a7caa82b2
Adds support for locked NOT
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This was trivial
2021-03-11 00:38:12 -08:00
Ryan Houdek
96f2a461f8
Adds support for locked ADC and SBB
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These were fairly straightforward
2021-03-11 00:22:35 -08:00
Ryan Houdek
6b4ccc46a8
Merge pull request #838 from Sonicadvance1/fix_cmpxchg_32bit_reg
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Fixes an edge case of 32bit cmpxchg <reg>, <reg>
2021-03-10 21:34:24 -08:00
Ryan Houdek
e264194453
Fixes an edge case of 32bit cmpxchg <reg>, <reg>
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The comparison was using the wrong values which means this cmpxchg would fail
2021-03-10 17:47:54 -08:00
Ryan Houdek
10fbf60259
Converts the printf usages in FEXCore to LogManager
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Now that we can safely handle long strings these will now work
2021-03-10 16:38:46 -08:00
Ryan Houdek
a9d3851684
Disables RCPC on ARM64 JIT
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This is currently bugged on Snapdragon 865.
Seems to only affect its prime core. Smells like errata.
2021-03-10 02:13:16 -08:00
Ryan Houdek
e3d6db2eb5
Merge pull request #823 from FEX-Emu/skmp/fix-secondaryalu-atomics
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OpDisp: Add atomic logic for SecondaryALUOp
2021-03-09 18:15:18 -08:00
Stefanos Kornilios Mitsis Poiitidis
d930de30ef
OpDisp: Add atomic logic for SecondaryALUOp
2021-03-09 18:32:13 +02:00
Scott Mansell
afda855caf
disptacher fixes/cleanups
2021-03-09 20:28:53 +13:00
Scott Mansell
6ed36e3304
Refactor syscalls to take Frame
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The vast majoirty of syscalls don't need anything in thread or frame.
So lets save an indirection for all those syscalls.
Most of the syscalls which do need Thread (or CTX via
Thread are in Thread.cpp or Memory.cpp
These have all been modifiy to fetch Thread from Frame
2021-03-09 20:28:50 +13:00
Scott Mansell
35c01038ba
Seperate per-thread and per-frame state
2021-03-09 20:27:44 +13:00
Scott Mansell
43a087d554
Allow both interpeter dispatchers to be built
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This commit doesn't include cmakefile changes to actually do this.
2021-03-09 20:25:14 +13:00
Ryan Houdek
a1fed323df
Merge pull request #820 from Sonicadvance1/remove_config_duplication
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Deduplicates some configuration data
2021-03-08 23:20:04 -08:00
Ryan Houdek
0bcd1c7df5
Merge pull request #816 from Sonicadvance1/cpuid_80000005
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Implements CPUID 0x8000'0005 for L1 cacheline information
2021-03-08 23:15:03 -08:00
Ryan Houdek
a3ba1ae199
Deduplicates some configuration data
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Configuration mapping was duplicated between three different tables.
Additionally default configuration values were strewn about. Making it confusing as to what the default value would end up being
Adds a new ConfigValues.inl header that defines a few things right next to each other.
Defines the enum name as usual.
Defines the JSON config option name.
Defines the Environment config option name
Defines the default value that the configuration should be
2021-03-08 22:53:41 -08:00
Scott Mansell
98cb54e3e4
Merge pull request #812 from phire/both_sides
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Allow both ARM64 and X86_64 jits to be compiled at the same time
2021-03-09 14:59:11 +13:00
Scott Mansell
cb17127ccb
Remove last traces of vixl simulator mode
2021-03-08 16:30:25 +13:00
Scott Mansell
93b6dbdc2b
Fix Arm64JitCore instantiation on x86
2021-03-08 16:30:25 +13:00
Scott Mansell
bea0adc3d1
Allow both jitcores to be enabled simultaneously
2021-03-08 16:30:25 +13:00
Scott Mansell
9cf7545f8d
Abstract mcontext out of JITs
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This will help with unification of common code later
2021-03-08 16:30:25 +13:00
Ryan Houdek
c657165e56
Implements CPUID 0x8000'0005 for L1 cacheline information
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@skmp commented about this in the L2 cacheline information PR.
Quickly implement it since it also has cacheline information.
Fairly trivial since every piece of information is just some 8bit variables.
2021-03-06 08:32:47 -08:00
Ryan Houdek
05ae7d3c5e
Merge pull request #814 from Sonicadvance1/cacheline_cpuid
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Implements CPUID 0x8000'0006 for cacheline information
2021-03-06 08:23:03 -08:00
Ryan Houdek
f94529ebb2
Implements CPUID 0x8000'0006 for cacheline information
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This exposes some cache information including cacheline information.
Fills out this data structure as well just incase we hit another cacheline size bug
2021-03-06 07:30:25 -08:00
Ryan Houdek
1adbf66fee
Implements MOVNTDQA
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Found this when running Steamlink under FEX on my laptop.
Turns out the Iris video driver now uses this unconditionally in a couple of locations.
Makes sense there since all the Iris targets are expected to support SSE4.1 atm.
2021-03-06 06:23:18 -08:00
Stefanos Kornilios Mitsis Poiitidis
3978097f15
Merge pull request #705 from FEX-Emu/skmp/mmap-cache-flushing
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Flush IR/Code cache on mmap, mmunmap & mprot
2021-03-03 12:59:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
613e5b66ba
SMC: Expand --smc-checks options to 'none', 'mman', 'full'
2021-03-03 12:49:23 +02:00
Scott Mansell
ec95610587
X64_64 JIt: Remove -fno-operator-names
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Some IDEs didn't recognize this flag and threw
phantom errors when these files were open.
Lets lean towards a smoother developer experience
2021-03-03 15:47:58 +13:00
Stefanos Kornilios Mitsis Poiitidis
e92578817d
SMC: Flush IR/Code cache on mmap, mmunmap & mprot
2021-02-26 13:22:05 +02:00
Stefanos Kornilios Mitsis Poiitidis
aecea294d5
Merge pull request #792 from Sonicadvance1/implemented_unaligned_memory_ops
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Implements unaligned atomic memory ops for ARMv8.1+
2021-02-26 12:50:06 +02:00
Ryan Houdek
6c469c21db
Fixes Zext and flags behaviour of CMPXCHG to register
2021-02-23 23:21:28 -08:00
Ryan Houdek
9798522bc5
Fixes Zext behaviour of CMPXCHG to memory
2021-02-23 23:21:05 -08:00
Ryan Houdek
373f4275f6
Fixes CMPXCHG flags being incorrect aside from ZF
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Almost everything only checks ZF but we had the arguments reversed for
the rest of the comparison flag results.
2021-02-23 22:01:52 -08:00
Scott Mansell
6fee5b9ca2
Merge pull request #789 from FEX-Emu/skmp/add-cacheinfo-cpuid
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CPUID: Add cache information, function 0x2
2021-02-24 03:06:20 +13:00
Stefanos Kornilios Mitsis Poiitidis
075cd423ed
AOTIR: Review feedback
2021-02-23 12:08:57 +02:00
Ryan Houdek