Ryan Houdek
edd1dfdfe8
Merge pull request #1040 from Sonicadvance1/more_syscalls_5_12
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Implements more syscalls for supporting a higher guest kernel version
2021-06-01 00:27:50 -07:00
Ryan Houdek
2d342d4662
Handle user provided siginfo_t with user signal
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If the guest has sent a signal and the si_code is SI_USER then
we need to pass that siginfo_t through without touching it.
User could be sticking whatever they want in to that struct
2021-05-27 22:59:27 -07:00
Ryan Houdek
211e7bf0f0
Implements SSE4.1 insertps
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Cheap Golf is using this instruction unconditionally.
With this implemented the game now runs
2021-05-26 21:40:39 -07:00
Stefanos Kornilios Mitsis Poiitidis
d70c91ddc6
AOTIR: Multi-threaded AOTGen
2021-05-19 14:19:55 +03:00
Stefanos Kornilios Mitsis Poiitidis
b8dc63754b
AOTIR: Don't keep IR,RA,Code data around when aotirgenerating
2021-05-11 15:15:39 +03:00
Stefanos Kornilios Mitsis Poiitidis
df8f1850ae
AOTIR: .aotir files are now stream-written
2021-05-11 14:37:12 +03:00
Ryan Houdek
82b04d9886
Fixes JITSymbols for x86-64 JIT
2021-05-06 01:12:51 -07:00
Stefanos Kornilios Mitsis Poiitidis
c8bb02f3a6
JIT: Add reason 1 (0xCD) to OP_BREAK implementations
2021-05-04 13:22:00 +03:00
Ryan Houdek
fd6d33d197
Merge pull request #996 from FEX-Emu/skmp/aotirgen
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AOTIR: Offline Generation
2021-05-03 15:58:57 -07:00
Stefanos Kornilios Mitsis Poiitidis
1d82e9e59e
JIT: Stub Break reasons 2, 3
2021-05-03 05:42:46 +03:00
Ryan Houdek
4961604807
Implements support for CLFLUSH
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JRE requires this to run
2021-05-02 12:18:35 -07:00
Ryan Houdek
417e8836a4
Arm64: Fixes some wrong sign extensions
2021-05-01 07:39:14 -07:00
Ryan Houdek
5143100a73
Switches more usages of memory allocation routines over to FEX internal
2021-05-01 07:39:14 -07:00
Stefanos Kornilios Mitsis Poiitidis
8b6e767742
Frontend: Slightly more resilient max instruction size handling
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
be0b29bbc6
OpDisp: Convert more asserts to soft-errors
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
ee8f8ed176
Improve error handling
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
5b8cbae1e1
Core/Frontend: Improve error handling
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
b98ef9e48b
Core/Frontend: Improve error handling
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
fd724448ab
Front End: Fix an error check
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
f4083883ca
Frontend: Fix ExternalBranches initialization
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
ab44f800f7
AOTgen: Cleaner interfaces, use LogMan
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
1a5bc39d09
Rebase fixes
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
244ef94e9b
AOTIR: Generate list of files with code, add Scripts/FEXUpdateAOTIRCache.sh to generate all files
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
a85ef061d1
AOITR: Add AOTIRGenerate fo FEXLoader option that does generation
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
4e847d03b7
Remove more assertions for invalid code
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
ce9324f50f
Kinda-parse unwind table
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
0897fc4a0a
pretrans wip
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
8a73783a07
AOTIR: Use FEXCore::Allocator
2021-04-29 08:16:21 +03:00
Stefanos Kornilios Mitsis Poiitidis
32b4b02302
AOTIR: mmap based loading
2021-04-28 13:08:43 +03:00
Ryan Houdek
6255eba524
Memory layout optimizations
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Some of these memory layouts weren't optimal for ARM loading.
This is now significantly improved
2021-04-26 23:48:22 -07:00
Ryan Houdek
04e0baadc6
Changes LogMan assert to defines
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C++ no-op functions can't optimize out the predicate arguments in all cases.
This was causing a problem where zero cost assertions weren't actually zero cost.
The only way to resolve this is to actually use macros sadly enough.
This will give a fairly hefty performance uplift with anything operating on IR.
2021-04-26 13:49:35 -07:00
Ryan Houdek
7d4380fe6d
Merge pull request #984 from FEX-Emu/skmp/relocation-fixes
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IR: Fix RIP relocation edge-cases
2021-04-26 10:11:24 -07:00
Ryan Houdek
7d5157b602
Merge pull request #983 from FEX-Emu/skmp/faster-l1
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LookupCache: Add new entries to L1C
2021-04-26 10:10:51 -07:00
Stefanos Kornilios Mitsis Poiitidis
b3564a4a48
IR: Fix RIP relocation edge-cases
2021-04-26 19:20:01 +03:00
Stefanos Kornilios Mitsis Poiitidis
df8b78b327
Dispatcher: Use Also lookup L1C when dispatching interpreter
2021-04-26 19:06:11 +03:00
Stefanos Kornilios Mitsis Poiitidis
2ea6a2a141
LookupCache: Fix L1C to actually cache entries
2021-04-26 18:38:03 +03:00
Stefanos Kornilios Mitsis Poiitidis
b45b7c3441
IR: Remove Entry from OP_HEADER, pass as parameter to CompileCode
2021-04-25 13:15:23 +03:00
Stefanos Kornilios Mitsis Poiitidis
7805552edb
LookupCache: Add new entries to L1C
2021-04-25 13:03:43 +03:00
Stefanos Kornilios Mitsis Poiitidis
60671ee6cb
Merge pull request #975 from Sonicadvance1/use_xxhash
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Switch from fasthash64 to xxhash's XXH3
2021-04-23 09:49:06 +03:00
Ryan Houdek
0b0db08ebf
Switch from fasthash64 to xxhash's XXH3
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Fixes #797
2021-04-18 18:13:27 -07:00
Ryan Houdek
967ac863be
Replaces naked mman usage in X86Dispatcher
2021-04-16 20:50:14 -07:00
Ryan Houdek
99ab9864aa
Replaces naked mman usage in X86HelperGen
2021-04-16 20:50:03 -07:00
Ryan Houdek
11246355e2
Replaces naked mman usage in LookupCache
2021-04-16 20:49:58 -07:00
Ryan Houdek
0d236940e0
Replaces naked mman usage in x86-64 JIT
2021-04-16 20:49:52 -07:00
Ryan Houdek
a0afb4be5a
Replaces naked mman usage in Arm64 JIT
2021-04-16 20:49:47 -07:00
Stefanos Kornilios Mitsis Poiitidis
22f1cf0e2a
More wip
2021-04-15 10:05:59 +03:00
Stefanos Kornilios Mitsis Poiitidis
80493487db
ELF Loading: Cleanups all around
2021-04-14 10:59:23 +03:00
Stefanos Kornilios Mitsis Poiitidis
59ce750af6
Elf: Add ELFCodeLoader2, with simplified loading logic
2021-04-13 15:59:36 +03:00
Ryan Houdek
66c8dd2013
First step in paranoid TSO mode
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This moves vector ops down the GPR atomic backpatch path.
Next step after this is to add SIGBUS based handlers for these rather than backpatching.
Needs more work to treat aligned versus unaligned vector loadstores differently
2021-04-06 18:48:36 -07:00
Ryan Houdek
91ac4ccdd8
Adds LDAXP and STLXP backpatch handlers
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This will be used in the next commit
2021-04-06 18:47:50 -07:00