lioncash
ecba1b6838
IR: Handle 256-bit VBSL
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Extends VBSL to handle 256-bit vectors.
2022-10-03 18:06:27 +00:00
Ryan Houdek
8d8b029285
Merge pull request #2044 from lioncash/vumax
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IR: Handle 256-bit VSMax/VUMax
2022-09-29 13:52:40 -07:00
lioncash
bf6f855868
IR: Handle 256-bit VSMax
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Extends VSMax to handle 256-bit vectors.
2022-09-29 20:31:19 +00:00
Ryan Houdek
aa6a499329
Merge pull request #2043 from lioncash/vumin
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IR: Handle 256-bit VSMin/VUMin
2022-09-29 13:19:07 -07:00
lioncash
0971650ef9
IR: Handle 256-bit VUMax
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Extends VUMax to handle 256-bit vectors.
2022-09-29 20:18:42 +00:00
Ryan Houdek
64c4fdccf7
Merge pull request #2042 from lioncash/vnot
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IR: Handle 256-bit VNot
2022-09-29 13:13:23 -07:00
lioncash
aef801b5b5
IR: Handle 256-bit VSMin
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Extends VSMin to handle 256-bit vectors.
2022-09-29 20:01:04 +00:00
lioncash
6c9e29796b
IR: Handle 256-bit VUMin
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Extends VUMin to handle 256-bit vectors.
2022-09-29 19:47:47 +00:00
lioncash
364bb3ac1e
IR: Handle 256-bit VNot
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Extends VNot to handle 256-bit vectors.
2022-09-29 14:40:46 +00:00
lioncash
428ea68507
IR: Handle 256-bit VFNeg
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Extends VFNeg to handle 256-bit vectors.
2022-09-29 14:00:52 +00:00
Ryan Houdek
1799d4c675
Merge pull request #2038 from lioncash/vneg
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IR: Handle 256-bit VNeg
2022-09-28 13:16:55 -07:00
Ryan Houdek
808e1c0330
Merge pull request #2029 from lioncash/interp
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Interpreter: Use constant for AVX register size where applicable
2022-09-28 13:16:14 -07:00
Ryan Houdek
dacd96cab5
Merge pull request #2037 from lioncash/vfrsqrt
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IR: Handle 256-bit VFRSqrt
2022-09-28 13:15:50 -07:00
Ryan Houdek
ca4d3bf64d
Merge pull request #2036 from lioncash/vfsqrt
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IR: Handle 256-bit VFSqrt
2022-09-28 13:14:25 -07:00
Ryan Houdek
ea38b043c1
Merge pull request #2035 from lioncash/vfrecp
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IR: Handle 256-bit VFRecp
2022-09-28 13:12:57 -07:00
Ryan Houdek
a39746df2e
Merge pull request #2034 from lioncash/vfmax
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IR: Handle 256-bit VFMax
2022-09-28 13:11:04 -07:00
Ryan Houdek
2367a8e50b
Merge pull request #2033 from lioncash/vfmin
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IR: Handle 256-bit VFMin
2022-09-28 13:10:17 -07:00
Ryan Houdek
cb121d7f17
Merge pull request #2032 from lioncash/vaddp
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IR: Handle 256-bit VAddP
2022-09-28 13:08:40 -07:00
lioncash
ce2286c48b
IR: Handle 256-bit VNeg
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Extends VNeg to handle 256-bit vectors.
2022-09-28 19:25:33 +00:00
lioncash
d5694d6de0
IR: Handle 256-bit VFRSqrt
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Extends VFRSqrt to handle 256-bit vectors.
2022-09-28 19:11:01 +00:00
lioncash
121218aa8a
IR: Handle 256-bit VFSqrt
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Extends VFSqrt to handle 256-bit vectors.
2022-09-28 18:46:43 +00:00
lioncash
6bb53fa758
IR: Handle 256-bit VFRecp
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Extends VFRecp to handle 256-bit vectors.
2022-09-28 18:27:34 +00:00
lioncash
89aa0c5471
IR: Handle 256-bit VFMax
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Extends VFMax to handle 256-bit vectors.
2022-09-28 17:40:16 +00:00
lioncash
53fcbf6afa
IR: Handle 256-bit VFMin
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Extends VFMin to handle 256-bit vectors.
2022-09-28 16:56:22 +00:00
lioncash
2f5643ae6b
Arm64/VectorOps: Amend half-precision case in VFAddP
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Noticed that I forgot to change the Zn register over to VTMP1.
This would have been caught by a vixl internal assert anyway.
Also make the behavior equal with VAddP, where we clear and only copy
over the exact amount of bytes instead of the whole register.
2022-09-28 15:10:49 +00:00
lioncash
d162ac8b3d
IR: Handle 256-bit VAddP
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Extends VAddP to handle 256-bit vectors.
2022-09-28 15:01:31 +00:00
lioncash
c9a704fbde
Interpreter: Handle 256-bit VMov
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Now we'll properly handle the move.
Also put an assert in place to catch any over-sized values.
2022-09-28 13:47:23 +00:00
lioncash
9d5a822a3a
Interpreter: Use constant for AVX register size where applicable
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Makes the previously implemented ops a little more self-documenting,
and, if we ever actually need to change this, there's a nice constant
that can be looked up instead of magic 32 values.
2022-09-28 13:38:03 +00:00
Ryan Houdek
50eba4066a
Merge pull request #2028 from lioncash/vfdiv
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IR: Handle 256-bit VFDiv
2022-09-27 13:39:02 -07:00
lioncash
6116ae5330
IR: Handle 256-bit VFDiv
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Extends VFDiv to handle 256-bit vectors.
2022-09-27 20:20:31 +00:00
Ryan Houdek
447226576f
Merge pull request #2027 from lioncash/vfmul
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IR: Handle 256-bit VFMul
2022-09-27 13:18:38 -07:00
Ryan Houdek
3f8b872f17
Merge pull request #2026 from lioncash/vfsub
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IR: Handle 256-bit VFSub
2022-09-27 13:17:00 -07:00
Ryan Houdek
e573ddc2db
Merge pull request #2025 from lioncash/vfaddp
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IR: Handle 256-bit VFAddP
2022-09-27 12:56:58 -07:00
lioncash
fe9aa681f0
IR: Handle 256-bit VFMul
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Extends VFMul to handle 256-bit vectors.
2022-09-27 19:54:57 +00:00
lioncash
1b2f2c1559
IR: Handle 256-bit VFSub
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Extends VFSub to be able to handle 256-bit vectors.
2022-09-27 19:33:46 +00:00
lioncash
84c75a86c3
IR: Handle 256-bit VFAddP
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Extends VFAddP to be able to handle 256-bit vectors.
2022-09-27 19:03:44 +00:00
Ryan Houdek
eedbde6f15
Merge pull request #2024 from lioncash/vfadd
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IR: Handle 256-bit VFAdd
2022-09-27 09:53:25 -07:00
Ryan Houdek
4e441e5a08
Merge pull request #2023 from lioncash/vpopcnt
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IR: Handle 256-bit VPopcount
2022-09-27 09:51:27 -07:00
Ryan Houdek
3e287a36c2
Merge pull request #2022 from lioncash/vabs
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IR: Handle 256-bit VAbs
2022-09-27 09:48:26 -07:00
lioncash
eadc477695
IR: Handle 256-bit VFAdd
2022-09-27 16:07:42 +00:00
lioncash
59aa324678
IR: Handle 256-bit VPopcount
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Extends VPopcount to be able to handle 256-bit width vectors
2022-09-27 15:19:24 +00:00
lioncash
219bce1467
IR: Handle 256-bit VAbs
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Extends VAbs to be able to handle 256-bit width vectors.
2022-09-27 13:56:38 +00:00
Ryan Houdek
46bde401bd
Merge pull request #2019 from Sonicadvance1/remove_mov
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IR: Removes Mov IR op
2022-09-26 19:49:52 -07:00
Ryan Houdek
01beac4956
Merge pull request #2018 from Sonicadvance1/remove_vextractelement
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IR: Removes VExtractElement
2022-09-26 19:49:46 -07:00
Ryan Houdek
825833cfcc
IR: Removes Mov IR op
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This is unused and shouldn't ever be used.
2022-09-26 16:04:27 -07:00
Ryan Houdek
4a4c49bf68
IR: Removes VExtractElement
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This is a duplicate of VDupElement since AArch64 doesn't support an
element extract plus zero of the rest of the register.
Removes and replaces its uses with VDupElement.
2022-09-26 15:55:41 -07:00
Ryan Houdek
763cea423a
IR: Removes unnecessary VBitcast IR op
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This instruction was purely a move that did format reinterpretation.
This was necessary with LLVM when we had implicit IR op sizes.
Now that all vector ops are explicitly sized, this is not only
redundant, but also completely unnecessary sicne we don't support LLVM
anymore.
Remove the op, which technically is a very minor optimization for the
two instructions that still used it.
2022-09-26 15:42:24 -07:00
Ryan Houdek
0fee355ff5
Merge pull request #2016 from lioncash/pred
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Arm64/VectorOps: Make use of static predicate registers
2022-09-26 14:48:26 -07:00
Ryan Houdek
8c7cfc4d11
Config: Adds support for unique 32-bit GuestThunk path
2022-09-26 14:01:48 -07:00
lioncash
496ee730c8
Arm64/VectorOps: Make use of static predicate registers
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Since PR #2003 , we now set up some predicate registers within
FillStaticRegs. We can now make use of those instead of manually setting
up predicate registers inside the IR opcodes.
2022-09-26 13:20:01 +00:00
lioncash