lioncash
ecb1cc4ed4
Interpreter: Handle 256-bit VBic
2022-09-15 16:18:14 +00:00
lioncash
5622bcae16
Interpreter: Handle 256-bit VOr
2022-09-15 16:18:14 +00:00
lioncash
f4539ee289
Interpreter: Handle 256-bit VXor
2022-09-15 16:18:10 +00:00
Ryan Houdek
f34f1309a7
Merge pull request #1983 from lioncash/vsqadd
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VectorOps: Extend VSQAdd/VSQSub/VUQAdd/VUQSub
2022-09-13 11:26:11 -07:00
lioncash
809f60df06
VectorOps: Handle 256-bit VSQSub
2022-09-13 16:43:42 +00:00
lioncash
cbdcd8253c
VectorOps: Handle 256-bit VSQAdd
2022-09-13 16:20:37 +00:00
lioncash
7ac2cd7cc8
VectorOps: Handle 256-bit VUQSub
2022-09-13 16:03:30 +00:00
lioncash
cf1bb1348c
VectorOps: Handle 256-bit VUQAdd
2022-09-13 16:03:27 +00:00
lioncash
b60a26ff9e
VectorOps: Handle 256-bit VSub
2022-09-13 15:40:45 +00:00
lioncash
b805c07342
VectorOps: Handle 256-bit VAdd
2022-09-13 15:40:06 +00:00
Ryan Houdek
0f59c1d5e3
Add support for the vixl simulator
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This will allow CI to test ARM features before we have any hardware that
supports it.
2022-09-07 19:54:07 -07:00
Ryan Houdek
c5a7fc1e2a
Resolve most VDSO comments
2022-09-02 15:13:18 -07:00
Ryan Houdek
98dbfbe654
Merge pull request #1949 from lioncash/interp-op
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InterpreterOps: Extend SSAData size to accomodate 256-bit operations
2022-09-02 09:54:58 -07:00
lioncash
6444726614
InterpreterOps: Use designated initializer for IR op data
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Same behavior, but keeps everything all initialized at the point of
declaration, rather than after the fact.
2022-09-02 12:40:25 -04:00
lioncash
0a562fbb10
InterpreterOps: Extend SSAData to handle 256-bit vectors
2022-09-02 12:40:14 -04:00
lioncash
3fdde0c90b
Arm64/JIT: Rename CanUseSVE to HostSupportsSVE
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This is a much more descriptive name.
Spawned off of discussion in #1944
2022-09-01 13:22:41 -04:00
Ryan Houdek
e776f4cd4e
Merge pull request #1948 from lioncash/svebit
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VectorOps: Extend VAnd/VBic/VOr/VXor
2022-08-30 17:57:51 -07:00
Ryan Houdek
e7d7dd13d7
Merge pull request #1945 from lioncash/vectormov
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VectorOps: Extend VMov
2022-08-30 17:57:00 -07:00
Ryan Houdek
37ccb13917
Merge pull request #1946 from lioncash/x86dep
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x86_64/JIT: Resolve lingering fmt deprecation warning
2022-08-30 17:54:57 -07:00
lioncash
70efdbba5d
VectorOps: Handle 256-bit VectorImm
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Extends VectorImm to be capable of using SVE to handle 256-bit length
vectors.
2022-08-24 13:28:48 -04:00
lioncash
bcb7e20619
VectorOps: Handle 256-bit VXor
2022-08-24 12:52:05 -04:00
lioncash
afc5e8a140
VectorOps: Handle 256-bit VOr
2022-08-24 12:52:05 -04:00
lioncash
4be6626c89
VectorOps: Handle 256-bit VBic
2022-08-24 12:52:02 -04:00
lioncash
5f2b6d629b
VectorOps: Handle 256-bit VAnd
2022-08-24 12:43:51 -04:00
lioncash
79674c697a
x86_64/JIT: Resolve lingering fmt deprecation warning
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Just a log that was missed during the previous fmt deprecation cleanup.
2022-08-24 11:49:02 -04:00
lioncash
416d8c1df6
VectorOps: Handle 256-bit VMov
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Kind of sucky that SVE doesn't have a convenient way to manipulate
predicate registers with immediates or anything to make this nicer (that
I know of).
Having to use a temp to clear the upper part of the vector reliably is
bleh.
2022-08-24 11:35:34 -04:00
lioncash
df22e0c796
x86_64/JITClass: Add ToYMM helper
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Will be used in subsequent changes to handle 256-bit operations in the
x86-64 backend
2022-08-23 12:58:25 -04:00
lioncash
79a3bd75cc
VectorOps: Handle 256-bit VectorZero
2022-08-23 12:57:59 -04:00
Ryan Houdek
bba58732e0
HostFeatures: Add new supported features flag
2022-08-14 19:56:14 -07:00
Stefanos Kornilios Mitsis Poiitidis
dc810c7a1e
Fix arm64 build
2022-08-08 05:19:09 +03:00
Stefanos Kornilios Misis Poiitidis
e0ee4e71f8
Fixes
2022-08-08 05:01:38 +03:00
Stefanos Kornilios Misis Poiitidis
ab7dac90a2
Mask signals around Block Linking
2022-08-08 04:19:01 +03:00
Stefanos Kornilios Misis Poiitidis
3a423fbc41
Synchronized Block Linking
2022-08-08 03:33:23 +03:00
lioncash
9e524a30d6
General: Resolve fmt deprecation warnings
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fmt 9.0.0 deprecates implicit conversions of unscoped enum values to
integers to be consistent with scoped enum behavior.
Fairly trivial to resolve
2022-08-04 11:39:51 -04:00
lioncash
0da6b07770
Arm64Dispatcher: Fix signed/unsigned comparisons
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Trivial change. We just need to use size_t instead of int here.
2022-08-03 11:23:40 -04:00
lioncash
05805356fb
Arm64Dispatcher: Amend register memcpy in SpillSRA
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Ensures that we spill to the correct register offset depending on the
execution mode.
2022-08-03 11:21:55 -04:00
lioncash
3960e0f2a3
Arm64/JIT: Remove unnecessary [[maybe_unused]] attributes
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These are always used inside the function via assignments.
2022-07-28 10:29:32 -04:00
Ryan Houdek
a984674dae
Merge pull request #1862 from Sonicadvance1/fix_tmp_pollution
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JitSymbols: Only initialize perf map file if using
2022-07-26 22:47:00 -07:00
Ryan Houdek
8589119725
Merge pull request #1856 from lioncash/avx-ldp
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Arm64Emitter: Re-add use of stp/ldp with hosts that don't support SVE2
2022-07-26 14:21:58 -07:00
lioncash
bff2f2e5f9
Context: Expose ability to retrieve host features
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Allows the test runner to determine whether or not to use AVX or SSE
state.
2022-07-26 16:56:57 -04:00
lioncash
5f9052a675
CoreState: Use a union for representing xmm data
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In the event that the host doesn't support the requirements for running
AVX-enabled applications (SVE2 with at least 256-bit wide vectors) but
still wanted to run regular SSE-enabled applications, they would be
taking a performance hit due to a load/store pessimization (necessary in
order for 256-bit loads/stores to work)
However, we can add an alternate view into the xmm data that would allow
those hosts to use the previous optimization, while still supporting
AVX-capable hosts.
2022-07-26 16:56:54 -04:00
Ryan Houdek
8691b3964f
JitSymbols: Only initialize perf map file if using
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In most cases we aren't using JIT symbols but still creating the perf
map file.
Early check if we should generate the file or not, this way we stop
polluting the /tmp folder.
2022-07-25 14:21:14 -07:00
Ryan Houdek
601b0f96b1
CPUID: Detect Cortex-X1C
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Missed this in the list before since we didn't know the part ID.
2022-07-20 23:20:56 -07:00
Stefanos Kornilios Mitsis Poiitidis
98d935d972
Merge pull request #1852 from lioncash/json
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json_ir_generator: Remove Args() functions from IR structs
2022-07-20 14:03:58 +00:00
Ryan Houdek
b07660c4fa
Merge pull request #1851 from Sonicadvance1/fix_soma_and_sa_mask
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Fix SOMA and sigaction definition
2022-07-19 13:06:45 -07:00
Ryan Houdek
8037231376
Merge pull request #1850 from Sonicadvance1/fix_faulting_instructions
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FEXCore: Fix-up edge case behaviour on faulting instructions
2022-07-19 10:23:12 -07:00
Ryan Houdek
6e422a8691
Signals: Steal back the XID signal from glibc
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glibc lazily initializes the SETXID signal handler until first thread
creation.
Once we create our first pthread, steal it back from GLIBC after the
fact.
Fixes SOMA again.
2022-07-19 10:18:47 -07:00
lioncash
08c34bf573
json_ir_generator: Remove Args() functions from IR structs
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Since the IR argument can be accessed directly by name, this is no
longer needed as a shorthand.
2022-07-19 11:23:13 -04:00
Ryan Houdek
ff1d51c7bd
FEXCore: Fix-up edge case behaviour on faulting instructions
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x86 has six instructions that will fault on us that we mostly handled. A
few of these weren't being handled correctly.
One problem is that RIP needs to synchronize differently depending on
which fault instruction it is. Some instructions fault at the
instruction RIP, some at the instruction afterwards.
Additionally some of the metadata generated around the signal delegation
wasn't correct.
With behaviour of all of these instructions changed, it will now be
easier to switch over to non-faulting guest synchronous signals off of
these instructions. This doesn't go far enough to change that behaviour
yet.
I noticed this when looking at Elden Ring's weird faulting behaviour
with ud2 and `int 0x2d`. This made me investigate since I had a
suspicion that we weren't handling both cases correctly.
With this change, Elden Ring is now stabilized and works under FEX.
2022-07-17 20:56:31 -07:00
Ryan Houdek
ba0887defa
Misc: Convert assert logs to assume+assert that can be
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Most of these won't make a performance difference. But we should be
using the assume version everywhere we can.
2022-07-17 12:51:43 -07:00
lioncash