These are interesting rotate instructions that treats CF as an
additional rotation bit for the source.
So you end up with a 9bit, 17bit, 33bit, or 65bit rotate.
The rotate value is still masked by 0x1F or 0x3F depending on
instruction size.
This ends up with the quirk that this instruction doesn't directly map
to AArch64 rotations for the smaller register sizes;
So we have to do some manual mirroring in a larger register to pull the
correct view out of the op
This interface is for native host code to be able to call back in to JIT
to execute guest code.
This is mainly for thunks but could be used for other purposes.
This can cross a couple ABI boundaries so one must be careful when
calling in to this
This helps out Mono's garbage collector specifically. There is a minor
race that can currently occur with signal 63 but that technically should
only occur on a pause or stop condition.
Might need to change this behaviour if it becomes a problem
glibc raise() actually disables all signals, raises the signal that the
user wants, then reenables the previous signal mask.
On the reenabling of the previous signal mask, that is when the pending
signal fires.
This needs to be accurately handled, so check for pending signals
getting unmasked in sigprocmask
This also then needs to be further fixed to handle default signal
handling, where if a signal was sent that is default ignored (NOT set to
ignore!) then it would just exit the application before.
Now something likg SIGCHLD with the default handler (aka ignore) won't
kill the process
Previously we never checked for SS_DISABLE.
We were also only ever checking for ss_sp being a valid memory range
when we should have been checking for the absense of SS_DISABLE.
Fixes#326
Instead of saying we support the world, actually go through each
individual flag and say that we support the correct things.
Puts FEX plus the git hash in to the model name for now.
Once we have a tagged release in the future we can change this to have
its version tag inside of it.
If the host CPU supports RCPC instructions then it'll use those
instruction of atomics for LoadMemTSO ops.
This pushed my worst case FTL test from 16FPS to 17FPS .
There is another extension to RCPC to add short immediate offset support
which the c630 doesn't support any way. For future optimization on
hardware we can use that.
