Lioncache
db8317caf8
ARMEmitter: Handle SVE ANDV (predicated)
2023-02-03 21:31:41 -05:00
Lioncache
3508f7a667
ARMEmitter: Handle SVE EORV (predicated)
2023-02-03 21:30:48 -05:00
Lioncache
02861f41eb
ARMEmitter: Handle SVE ORV (predicated)
2023-02-03 21:26:06 -05:00
Lioncache
51c9f70904
ARMEmitter: Handle SVE UADDV (predicated)
2023-02-03 21:05:00 -05:00
Lioncache
4f9530cec3
ARMEmitter: Handle SVE SADDV (predicated)
2023-02-03 21:02:45 -05:00
Lioncache
ecd711e691
ARMEmitter: Handle SVE UDIVR (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
870115dd5d
ARMEmitter: Handle SVE SDIVR (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
848e5561ce
ARMEmitter: Handle SVE UDIV (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
db8a9bb5cf
ARMEmitter: Handle SVE SDIV (predicated)
2023-02-03 20:49:54 -05:00
Lioncache
f8a1c43c06
ARMEmitter: Handle SVE UMULH (predicated)
2023-02-03 20:27:48 -05:00
Lioncache
3a98190119
ARMEmitter: Handle SVE SMULH (predicated)
2023-02-03 20:25:44 -05:00
Lioncache
19ad19193e
ARMEmitter: Handle SVE MUL (predicated)
2023-02-03 20:16:24 -05:00
Ryan Houdek
9d33bba1c8
Merge pull request #2366 from lioncash/addsub
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ARMEmitter: Handle integer add/subtract vectors (predicated) instruction class
2023-02-03 10:31:56 -08:00
Lioncache
8c09356bd7
ARMEmitter: Handle SETF16
2023-02-02 23:27:40 -05:00
Lioncache
50bcc1b96f
ARMEmitter: Handle SETF8
2023-02-02 23:26:07 -05:00
Lioncache
36831ebc37
ARMEmitter: Handle RMIF
2023-02-02 23:18:22 -05:00
Lioncache
44f5d788c8
ARMEmitter: Handle SUBR (vector, predicated)
2023-02-02 21:44:44 -05:00
Lioncache
a42ae7d385
ARMEmitter: Handle SUB (vector, predicated)
2023-02-02 21:42:57 -05:00
Lioncache
5cf9bb2613
ARMEmitter: Handle ADD (vector, predicated)
2023-02-02 21:41:12 -05:00
Lioncache
4001dc1219
ARMEmitter: Handle SVE FMINV
2023-02-02 20:42:54 -05:00
Lioncache
f77de7f283
ARMEmitter: Handle SVE FMAXV
2023-02-02 20:41:10 -05:00
Lioncache
ac9f9d291b
ARMEmitter: Handle SVE FMINNMV
2023-02-02 20:35:43 -05:00
Lioncache
25f97065df
ARMEmitter: Handle SVE FMAXNMV
2023-02-02 20:33:37 -05:00
Lioncache
6fcbce0c52
ARMEmitter: Handle SVE FADDV
2023-02-02 20:28:11 -05:00
Lioncache
4c647a2e02
ARMEmitter: Handle NMATCH
2023-02-02 15:40:34 -05:00
Lioncache
d0f00d53d3
ARMEmitter: Handle MATCH
2023-02-02 15:40:34 -05:00
Lioncache
6174437667
ARMEmitter: Handle SVE FCMLA
2023-02-02 15:40:34 -05:00
Lioncache
9c762861f6
ARMEmitter: Handle SVE FCADD
2023-02-02 15:40:34 -05:00
Lioncache
448785e693
ARMEmitter: Handle HISTSEG
2023-02-02 15:40:26 -05:00
Lioncache
f8c68acc09
ARMEmitter: Handle HISTCNT
2023-02-02 15:40:18 -05:00
Lioncache
2e232ac3dd
OpcodeDispatcher: Handle VBLENDPS
2023-02-01 20:36:23 -05:00
Lioncache
88ff0db12a
OpcodeDispatcher: Handle VPBLENDD
2023-02-01 20:36:15 -05:00
Ryan Houdek
fa1193f14c
Merge pull request #2344 from Sonicadvance1/siginfo_32
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FEXCore: Fixup 32-bit signal handling
2023-01-31 20:26:36 -08:00
Lioncache
4177d5c185
Arm64/VectorOps: Clamp shift amount to esize-1 for VSShr
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Makes the behavior consistent with the x86 JIT.
We need to treat values larger than 31 as if they were 31 bit shifts in
order to handle sign-extending behavior properly.
2023-01-31 22:53:51 -05:00
Lioncache
d5316c8c7e
OpcodeDispatcher: Handle VPSRAVD
2023-01-31 17:31:24 -05:00
Lioncache
cc65f3e788
Arm64/VectorOps: Implement VSShr
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This will be used for implementing VPSRAVD
2023-01-31 17:31:20 -05:00
Mai
787b6895e8
Merge pull request #2337 from Sonicadvance1/optimize_frontend
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Frontend: Various optimizations
2023-01-31 14:46:11 +00:00
Mai
7be2e1ad34
Merge pull request #2330 from Sonicadvance1/implement_flushes
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OpDispatcher: Adds support for CLWB and CLFLUSHOPT
2023-01-31 04:01:26 +00:00
Ryan Houdek
d75e1f996f
FEXCore: Fixup 32-bit signal handling
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Follow-up to #2327 .
Split off from #2176 and improved.
32-bit signals are a bit more complex than 64-bit due to behaviour
changing depending on if `rt_sigaction` and `sigaction` syscall is used
and if `SA_SIGINFO` is passed in to the flags.
With `SA_SIGINFO` used, both turn in to an `RT` frame, which is encoded
differently than without `SA_SIGINFO`.
Additionally 32-bit signals support both regular Linux stack ABI and
`regparm(3)` ABI.
Without `SA_SIGINFO` then `siginfo_t` is removed from the signal handler
arguments, but most of the rest still remains.
Also two of the arguments to the signal handler are forced to be nullptr
with `regparm(3)`.
2023-01-30 13:30:15 -08:00
Ryan Houdek
14fe95bd14
IR: Removes NumArgs member from IR ops
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Split off from #2243 to remove each member individually.
Shaves 8-bits off of each IR op.
No need to cart around this data when it is constant for each operation.
Especially since most optimization passes don't need the data anyway.
Needed to add a new `GetRAArgs` to get the number of SSA arguments that
get RA versus `GetArgs` which returns all SSA arguments the IR operation
owns. This is what was causing #2243 to fail CI since it needs to know
the difference in some places.
2023-01-30 11:53:05 -08:00
Ryan Houdek
65b6b6d5dd
Merge pull request #2355 from Sonicadvance1/siginfo_64
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Dispatcher: Extract 64-bit signal frame save and restore
2023-01-30 11:50:03 -08:00
Mai
f8e762fcfb
Merge pull request #2319 from Sonicadvance1/remove_has_dest
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IR: Remove HasDest member
2023-01-30 16:25:09 +00:00
Ryan Houdek
9cfd169fb8
Dispatcher: Extract 64-bit signal frame save and restore
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Stripped from #2344 at request to ensure 64-bit code hasn't changed in a
meaningful way. So that PR can focus on 32-bit.
2023-01-27 01:17:32 -08:00
Mai
da88c68e12
Merge pull request #2332 from Sonicadvance1/emitter_test_ci
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Github: Add ARM emitter tests to CI
2023-01-25 23:47:39 +00:00
Mai
7f6a620c9e
Merge pull request #2349 from Sonicadvance1/virtual_mem_size_32bit
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Core: Adjust virtual memory size for 32-bit
2023-01-24 21:12:36 +00:00
Mai
1e90ebb400
Merge pull request #2323 from Sonicadvance1/pool_inline_constants
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ConstProp: Pool inline constants
2023-01-24 21:11:56 +00:00
Ryan Houdek
c6d46801ad
ConstProp: Pool inline constants
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In large blocks we can be generating a ton of inline constants. But in
most cases these end up being 0, 1, or (1 << N).
Add these to a map and reuse if possible. Makes some IR blocks
significantly smaller for later optimization passes.
2023-01-24 12:58:29 -08:00
Mai
afaff9293b
Merge pull request #2316 from Sonicadvance1/fix_negative_ficomi_f64
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X87_F64: Fixes FICOM
2023-01-24 17:31:05 +00:00
Mai
a28039f7cd
Merge pull request #2350 from Sonicadvance1/optimize_dispatcher_slightly
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Arm64: Merge two loads in to an LDP
2023-01-23 08:35:13 +00:00
Ryan Houdek
db4cb497e0
unittests: New emitter tests for LongAddressGen
2023-01-22 16:03:17 -08:00
Lioncache