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Code Issues Packages Projects Releases 67 Wiki Activity
4,735 Commits 11 Branches 71 Tags
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Commit Graph
1519 Commits
Author SHA1 Message Date
Ryan Houdek 6742e0c376 Merge pull request #2003 from lioncash/svespill 
JITs: Handle spilling/filling 256-bit vectors
 2022-09-23 17:27:53 -07:00
lioncash 707db51b1b Arm64Emitter: Amend comment for GPR temporaries 
Only x3 can be used across spill boundaries.
 2022-09-24 00:12:01 +00:00
lioncash 5b5fa1aa29 x86_64/JIT: Handle pushing and popping 256-bit values 2022-09-24 00:11:56 +00:00
Ryan Houdek 2b9cc9666a Merge pull request #2006 from Sonicadvance1/remove_splat 
IR: Removes SplatVector{2,4}
 2022-09-23 14:42:44 -07:00
Ryan Houdek 5c84e8f23c IR: Removes VInsScalarElement 
This IR op duplicates what VInsElement does.
 2022-09-22 17:57:20 -07:00
Ryan Houdek 081b61677a IR: Removes SplatVector{2,4} 
These IR ops are redundant and mostly unused.
VDupElement does exactly what these operations were already doing and
more closely matches what the hardware wants.
 2022-09-22 17:49:28 -07:00
lioncash 9c54814b98 Arm64Emitter: Handle spilling 256-bit dynamic regs 2022-09-22 12:40:54 +00:00
lioncash 35d7b855ed Arm64Dispatcher: Increment code buffer size 
vixl hits an assertion in CodeBuffer's Emit() function since there's no
space for any more instructions with the changes made to handle SVE.
 2022-09-22 12:40:54 +00:00
lioncash 0b8799274c Arm64Emitter: Handle filling/spilling 256-bit static FPRs 
Drops in handling for spilling/filling FPRs using SVE for supporting
AVX.

Also alters the dispatcher and JIT a little to avoid accidentally clobbering
TMP4 (x3 as of this commit)
 2022-09-22 12:40:54 +00:00
lioncash ace2b737d8 Arm64Emitter: Initialize fixed predicate register values in FillStaticRegs 
Allows us to have values set up in a way that we don't need to
constantly set up predicates in IR ops.
 2022-09-22 12:40:54 +00:00
Ryan Houdek 83763df6fd Arm64: Fixes SVE VectorImm 
SVE DUP instruction does sign extension on the incoming immediate, while
ASIMD MOVI does zero extension.

If the immediate doesn't fit then move in to a GPR first and then DUP
from GPR.
 2022-09-22 01:16:58 -07:00
lioncash 341bdb5a54 JITs: Handle 32 byte spills and fills 
Puts in the plumbing necessary to handle spilling and filling 256-bit
data.
 2022-09-19 22:00:20 +00:00
lioncash 2f3dbfb289 JITs: Expand max spill slot size to 32 bytes 
This will be necessary to handle spilling 256-bit vectors.
 2022-09-19 19:51:32 +00:00
lioncash 868e4a6d81 Arm64: Centralize location for register defines 
Gets rid of a few repeated definitions and allows the emitter itself to
make use of these defines without causing a circular dependency on the
JIT.
 2022-09-19 17:44:21 +00:00
lioncash 2bb27fffb7 VectorOps: Handle 256-bit VURAvg 2022-09-15 19:38:31 +00:00
Ryan Houdek 0261ed353d Merge pull request #1992 from lioncash/uminv 
VectorOps: Handle 256-bit VUMinV
 2022-09-15 12:05:27 -07:00
lioncash 95fbcd7b9a VectorOps: Handle 256-bit VUMinV 2022-09-15 18:36:46 +00:00
lioncash f999d30bc5 Interpreter: Handle 256-bit VAnd 2022-09-15 16:18:14 +00:00
lioncash ecb1cc4ed4 Interpreter: Handle 256-bit VBic 2022-09-15 16:18:14 +00:00
lioncash 5622bcae16 Interpreter: Handle 256-bit VOr 2022-09-15 16:18:14 +00:00
lioncash f4539ee289 Interpreter: Handle 256-bit VXor 2022-09-15 16:18:10 +00:00
Ryan Houdek f34f1309a7 Merge pull request #1983 from lioncash/vsqadd 
VectorOps: Extend VSQAdd/VSQSub/VUQAdd/VUQSub
 2022-09-13 11:26:11 -07:00
lioncash 809f60df06 VectorOps: Handle 256-bit VSQSub 2022-09-13 16:43:42 +00:00
lioncash cbdcd8253c VectorOps: Handle 256-bit VSQAdd 2022-09-13 16:20:37 +00:00
lioncash 7ac2cd7cc8 VectorOps: Handle 256-bit VUQSub 2022-09-13 16:03:30 +00:00
lioncash cf1bb1348c VectorOps: Handle 256-bit VUQAdd 2022-09-13 16:03:27 +00:00
lioncash b60a26ff9e VectorOps: Handle 256-bit VSub 2022-09-13 15:40:45 +00:00
lioncash b805c07342 VectorOps: Handle 256-bit VAdd 2022-09-13 15:40:06 +00:00
Ryan Houdek 0f59c1d5e3 Add support for the vixl simulator 
This will allow CI to test ARM features before we have any hardware that
supports it.
 2022-09-07 19:54:07 -07:00
Ryan Houdek c5a7fc1e2a Resolve most VDSO comments 2022-09-02 15:13:18 -07:00
Ryan Houdek 98dbfbe654 Merge pull request #1949 from lioncash/interp-op 
InterpreterOps: Extend SSAData size to accomodate 256-bit operations
 2022-09-02 09:54:58 -07:00
lioncash 6444726614 InterpreterOps: Use designated initializer for IR op data 
Same behavior, but keeps everything all initialized at the point of
declaration, rather than after the fact.
 2022-09-02 12:40:25 -04:00
lioncash 0a562fbb10 InterpreterOps: Extend SSAData to handle 256-bit vectors 2022-09-02 12:40:14 -04:00
lioncash 3fdde0c90b Arm64/JIT: Rename CanUseSVE to HostSupportsSVE 
This is a much more descriptive name.

Spawned off of discussion in #1944
 2022-09-01 13:22:41 -04:00
Ryan Houdek e776f4cd4e Merge pull request #1948 from lioncash/svebit 
VectorOps: Extend VAnd/VBic/VOr/VXor
 2022-08-30 17:57:51 -07:00
Ryan Houdek e7d7dd13d7 Merge pull request #1945 from lioncash/vectormov 
VectorOps: Extend VMov
 2022-08-30 17:57:00 -07:00
Ryan Houdek 37ccb13917 Merge pull request #1946 from lioncash/x86dep 
x86_64/JIT: Resolve lingering fmt deprecation warning
 2022-08-30 17:54:57 -07:00
lioncash 70efdbba5d VectorOps: Handle 256-bit VectorImm 
Extends VectorImm to be capable of using SVE to handle 256-bit length
vectors.
 2022-08-24 13:28:48 -04:00
lioncash bcb7e20619 VectorOps: Handle 256-bit VXor 2022-08-24 12:52:05 -04:00
lioncash afc5e8a140 VectorOps: Handle 256-bit VOr 2022-08-24 12:52:05 -04:00
lioncash 4be6626c89 VectorOps: Handle 256-bit VBic 2022-08-24 12:52:02 -04:00
lioncash 5f2b6d629b VectorOps: Handle 256-bit VAnd 2022-08-24 12:43:51 -04:00
lioncash 79674c697a x86_64/JIT: Resolve lingering fmt deprecation warning 
Just a log that was missed during the previous fmt deprecation cleanup.
 2022-08-24 11:49:02 -04:00
lioncash 416d8c1df6 VectorOps: Handle 256-bit VMov 
Kind of sucky that SVE doesn't have a convenient way to manipulate
predicate registers with immediates or anything to make this nicer (that
I know of).

Having to use a temp to clear the upper part of the vector reliably is
bleh.
 2022-08-24 11:35:34 -04:00
lioncash df22e0c796 x86_64/JITClass: Add ToYMM helper 
Will be used in subsequent changes to handle 256-bit operations in the
x86-64 backend
 2022-08-23 12:58:25 -04:00
lioncash 79a3bd75cc VectorOps: Handle 256-bit VectorZero 2022-08-23 12:57:59 -04:00
Ryan Houdek bba58732e0 HostFeatures: Add new supported features flag 2022-08-14 19:56:14 -07:00
Stefanos Kornilios Mitsis Poiitidis dc810c7a1e Fix arm64 build 2022-08-08 05:19:09 +03:00
Stefanos Kornilios Misis Poiitidis e0ee4e71f8 Fixes 2022-08-08 05:01:38 +03:00
Stefanos Kornilios Misis Poiitidis ab7dac90a2 Mask signals around Block Linking 2022-08-08 04:19:01 +03:00