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Code Issues Packages Projects Releases 67 Wiki Activity
2,427 Commits 11 Branches 71 Tags
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Commit Graph
894 Commits
Author SHA1 Message Date
Stefanos Kornilios Mitsis Poiitidis 22f1cf0e2a More wip 2021-04-15 10:05:59 +03:00
Stefanos Kornilios Mitsis Poiitidis 80493487db ELF Loading: Cleanups all around 2021-04-14 10:59:23 +03:00
Stefanos Kornilios Mitsis Poiitidis 59ce750af6 Elf: Add ELFCodeLoader2, with simplified loading logic 2021-04-13 15:59:36 +03:00
Ryan Houdek 66c8dd2013 First step in paranoid TSO mode 
This moves vector ops down the GPR atomic backpatch path.
Next step after this is to add SIGBUS based handlers for these rather than backpatching.
Needs more work to treat aligned versus unaligned vector loadstores differently
 2021-04-06 18:48:36 -07:00
Ryan Houdek 91ac4ccdd8 Adds LDAXP and STLXP backpatch handlers 
This will be used in the next commit
 2021-04-06 18:47:50 -07:00
Stefanos Kornilios Mitsis Poiitidis 50c3ee047c Merge pull request #961 from Sonicadvance1/fix_segment_override 
Fixes segment register override on string instructions.
 2021-04-06 09:24:23 +03:00
Stefanos Kornilios Mitsis Poiitidis c0ef6da6a8 Merge pull request #960 from Sonicadvance1/more_cpuid 
Adds some more CPUID functions
 2021-04-06 09:23:13 +03:00
Stefanos Kornilios Mitsis Poiitidis 4a5eefec25 Merge pull request #958 from Sonicadvance1/fix_atomic_zext 
Fixes Zext semantics on atomic ops with x64 JIT
 2021-04-06 09:21:44 +03:00
Stefanos Kornilios Mitsis Poiitidis c26f19ed4d Merge pull request #950 from Sonicadvance1/fix_gcc_tests 
Fixes GCC tests
 2021-04-06 09:05:45 +03:00
Stefanos Kornilios Mitsis Poiitidis 9619cea097 Merge pull request #949 from Sonicadvance1/arm64_print 
Adds support for Arm64 JIT to Print
 2021-04-06 08:58:13 +03:00
Stefanos Kornilios Mitsis Poiitidis 44dbecc2ac Merge pull request #948 from Sonicadvance1/fix_leak 
Fixes memory leak in CPU backends
 2021-04-06 08:56:00 +03:00
Ryan Houdek b7e81e867d Fixes segment register override on string instructions. 
The segment prefix only overrides one side of the string instruction.
Passing in the flags was causing the instruction to have the segment override on both sides of the copy.
So something like `movsb es:[rdi], fs:[rsi]` was being interpreted as `movsb fs:[rdi], fs:[rsi]`
Same for all the string ops which is now fixed.

We can't unit test these currently since we can't set host segment register for confirmed host behaviour.
 2021-04-05 21:28:31 -07:00
Ryan Houdek 4f276aae82 Adds comment for LEA and segment registers 
LEA doesn't give you the result with segment register applied to it.
Adds a comment to OpDispatcher to make it more clear
 2021-04-05 21:28:25 -07:00
Ryan Houdek c80254f6f4 Adds some more CPUID functions 
Noticed a game poking at these
 2021-04-05 18:37:05 -07:00
Ryan Houdek 0dd1959d65 Fixes Zext semantics on atomic ops with x64 JIT 
Fixes Factorio 1.1.30 on x86-64 hosts

Fixes #957
 2021-04-05 18:19:15 -07:00
Ryan Houdek f8eabb4f33 Implements 64bit scalar VUMin on x86 JIT 2021-04-04 22:05:55 -07:00
Ryan Houdek 4da492d361 Fixes vector integer min and max on AArch64 
These instructions don't have a 64bit element variant.
Switch the 64bit element variant over to a coded variant similar to float min/max
 2021-04-04 22:05:55 -07:00
Ryan Houdek a200d2c91c Fixes packed shift ops 
In the case of a shift value larger than the element size then the shift will zero the element.
Incoming shift amount is always a 64bit value which means that the value can become quite large on shifts.
Checks the incoming source and sets the maximum to be the element size, which works for AArch64's vector shifts
Which only operate on 8bit incoming shift amounts
 2021-04-04 22:05:55 -07:00
Ryan Houdek af205e9f5f Fixes PEXTRW 
In the case of 16bit PEXTRW it will zext to 32bits which wasn't being done
 2021-04-04 21:32:12 -07:00
Ryan Houdek 032d1fbba2 Fixes VFMIN/VFMax NaN behaviour 
In a world with NaNs we were hitting some undefined behaviour with fmin/fmax
Needed to change these over to something more complex to handle the NaN case.

ARMv8.7 alternative FP mode would solve this for the scalar case, but it still doesn't work for the vecto case sadly.
 2021-04-04 21:29:46 -07:00
Ryan Houdek 313c4bb784 Fixes bug in VectorImm 
If passing in a 64bit immediate then movi doesn't behaviour how you would expect.

Instead to a tmp move + dup to implement it the way we want
 2021-04-04 20:24:23 -07:00
Ryan Houdek ceb484fd3a Adds support for Arm64 JIT to Print 
Useful for debugging, supports both vector and GPR
 2021-04-04 20:22:44 -07:00
Ryan Houdek b98c7bd853 Moves AArch64's GetPhys to be a class function 
No need for it to be static
 2021-04-04 20:21:06 -07:00
Ryan Houdek 4c045148b6 Fixes memory leak in CPU backends 
Dispatcher wasn't ever getting cleaned up.
Also ensures sharing it with the CompileService otherwise it crashes on use.
 2021-04-04 20:19:35 -07:00
Ryan Houdek 9f29bba4aa Fixes missing virtual destructor on Dispatcher class 2021-04-04 20:10:58 -07:00
Ryan Houdek 2c592bd8a8 Implements a minimal siginfo_t in the dispatcher's signal handler 
This lets Carrion get farther in game.
Seems like one of its threads hits sigsegv and it just...lets it die after checking siginfo?
 2021-04-03 17:03:19 -07:00
Ryan Houdek 21a364c2ad Switches FEXCore over to pthreads implementation 
This defaults to a pthread implementation but it can be switched over to a custom thread
handler if the frontend desires.
 2021-04-01 00:31:45 -07:00
Stefanos Kornilios Mitsis Poiitidis 315b8e9c1e Merge pull request #917 from FEX-Emu/skmp/lightweight-docs-3 
Docs: Add tags, unittest Readme.md, generated SourceOutline.md
 2021-03-30 12:52:18 +03:00
Stefanos Kornilios Mitsis Poiitidis 942b8549c6 Docs: Add tags to the source code 2021-03-30 12:21:18 +03:00
Lioncache 434a74a88a CMakeLists: Flag unannotated implicit fallthrough as an error 
Prevents a class of sneaky logic bugs from slipping through into the
codebase.

This also resolves a case of such a bug within the Decorder's ReadData()
where all 3 byte reads would be performed as if they were a 4 byte read.
 2021-03-30 04:56:12 -04:00
Ryan Houdek c92df21627 Merge pull request #915 from lioncash/fallthrough 
OpcodeDispatcher: Add missing break for UD2 in INTOp()
 2021-03-29 22:56:19 -07:00
Lioncache 539de0492e OpcodeDispatcher: Add missing break for UD2 in INTOp() 
Fixes a case where the reason gets overwritten.
 2021-03-29 23:42:26 -04:00
Lioncache 99ae862875 Context: Eliminate undefined behavior in LoadEntryList() 
This breaks the strict-aliasing rule. We can use std::memcpy here to
make this code well-defined.
 2021-03-29 12:17:36 -04:00
Lioncache b81ea43601 Context: Make use of std::optional with GetFilenameHash() 
Same behavior, minus the need for an out parameter. While we're at it,
we can tidy up some of the file handling code.
 2021-03-29 12:17:32 -04:00
Ryan Houdek 8fad0c8fdb Adds a 32-bit mask for multiblock RIP calculation 
In the case of overflow then it'll just mask this result.
The rest of the logic already matches what 32-bit expects.

Fixes #703
 2021-03-28 23:39:53 -07:00
Ryan Houdek 650877adca Replaces FEX's usage of classic C array element count with std::size 
Just learned that this is a c++17 feature and it's a nice little
cleanup.

Only one remains in our codebase which can't easily be replaced
 2021-03-28 05:39:35 -07:00
Ryan Houdek 9eee879be0 Removes remaining warnings from AArch64 JIT. 
There are a couple of warnings remaining but need restructuring to solve.
I believe @phire is going to fix the one warning about a virtual destructor in a upcoming PR.
Fixes #679
 2021-03-26 18:49:40 -07:00
Ryan Houdek a50689aa8b Merge pull request #885 from Sonicadvance1/cpuid_leaf 
Adds support for CPUID leafs
 2021-03-23 20:55:33 -07:00
Scott Mansell 6a8f68022f Join threads after fork. 
Also, add some comments to document things and
rename function to be clear about it's purpose.
 2021-03-24 15:41:09 +13:00
Ryan Houdek 43ddba4e82 Adds support for CPUID leafs 
Leafs come from ECX but only some CPUID functions support this.
This adds the initial infrastructure but doesn't yet add support for the CPUID functions to consume the leaf.
 2021-03-23 18:13:14 -07:00
Scott Mansell 41a1a9d400 Cleanup threads when they exit 2021-03-24 03:14:23 +13:00
Ryan Houdek e5a9bd4d3e Fixes incorrect result on cmpxchg reg, reg failure when regsize = 32bit 2021-03-22 09:03:48 -07:00
Ryan Houdek ca24ea1d36 Fixes missing HandledLock on XCHG 2021-03-22 09:03:48 -07:00
Ryan Houdek 8c1f2eb0b3 Merge pull request #870 from FEX-Emu/skmp/lock-validation 
OpDisp: Validate LOCK handling, add missing segment offsets
 2021-03-20 15:53:06 -07:00
Stefanos Kornilios Mitsis Poiitidis d120f12c93 X87: Init on X87FNSAVE, fix FNINIT 2021-03-19 17:04:51 +02:00
Stefanos Kornilios Mitsis Poiitidis 695322d446 OpDisp: Validate LOCK handling, add missing segment offsets 2021-03-19 16:32:29 +02:00
Stefanos Kornilios Mitsis Poiitidis a7dc9d00d2 Merge pull request #864 from Sonicadvance1/cpuid_15h 
Implements CPUID 15h
 2021-03-19 10:02:02 +02:00
Ryan Houdek c7f265158f Implements CPUID 15h 
ARMv8 allows you query the cycle counter register very from userspace which allows us to emulate this easily.

My IceLake device returns 1.5Ghz through this interface
My AMD Zen+ device doesn't support this but with measurements has 3Ghz TSC
My Snapdragon 865 device has a TSC frequency of 19.20Mhz
 2021-03-18 01:42:44 -07:00
Ryan Houdek fbf5325bdd Enables Invariant TSC CPUID bit 
I keep forgetting to enable this bit. Fixes #855
 2021-03-18 00:15:48 -07:00
Ryan Houdek 0c5e5dbdf2 Removes warnings from OpcodeDispatcher 2021-03-14 13:27:39 -07:00