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Code Issues Packages Projects Releases 67 Wiki Activity
9,533 Commits 11 Branches 71 Tags
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Commit Graph
1283 Commits
Author SHA1 Message Date
Ryan Houdek 44767901fe FEXCore/Interface/Core/Dispatcher: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 1220c86573 FEXCore/Interface/Core/ArchHelpers: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 6ace406a2f FEXCore/Interface/Core/ObjectCache: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 38f1536255 FEXCore/Interface/Core/OpcodeDispatcher: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 324473651e FEXCore/Interface/Core/X86Tables: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 573148b27a FEXCore/Interface/Core/VSyscall: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek 12e1c2eaa0 FEXCore/Interface/Context: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek c678ea3060 FEXCore/Interface/GDBJIT: Adds SPDX identifier 2023-09-19 17:33:15 -07:00
Ryan Houdek e570b07ba0 FEXCore/Interface/Thunks: Adds SPDX identifier 2023-09-19 17:33:14 -07:00
Ryan Houdek afda4d6b7a FEXCore/Interface/IR: Adds SPDX identifier 2023-09-19 17:33:14 -07:00
Ryan Houdek 22daa506f6 FEXCore/Interface/Config: Adds SPDX identifier 2023-09-19 17:33:14 -07:00
Alyssa Rosenzweig 25943d1d17 OpcodeDispatcher: Sigh. 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:50:40 -04:00
Alyssa Rosenzweig bf03dab295 Arm64: Use csetm 
Saves some moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:50:40 -04:00
Alyssa Rosenzweig 8adfaa9aa6 OpcodeDispatcher: Use SelectCC for x87 
Better code gen and will benefit from future work.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-19 08:37:54 -04:00
Ryan Houdek 2ea2300408 Merge pull request #3110 from Sonicadvance1/buffered_jit_symbols 
FEXCore/JitSymbols: Buffer writes to reduce overhead
 2023-09-18 11:38:06 -07:00
Alyssa Rosenzweig df3833edbe OpcodeDispatcher: Use plain Lshl for flags 
If we have PF but no CF this simplifies the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-18 11:01:46 -04:00
Alyssa Rosenzweig 8edcd31404 OpcodeDispatcher: Avoid inverting PF 
..if we can fold the invert into the reader.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-18 10:35:39 -04:00
Ryan Houdek fd1b639ad9 Merge pull request #3115 from lioncash/sqxtun 
Arm64/VectorOps: Elide moves where applicable in 128-bit VSQXTUN2
 2023-09-17 14:51:27 -07:00
Lioncache 26e4d8ad59 Arm64/VectorOps: Elide moves where applicable in 128-bit VSQXTUN2 
If the destination and lower data alias, we can
avoid needing to move into a temporary.
 2023-09-17 17:37:36 -04:00
Lioncache d54f590b14 Arm64/VectorOps: Improve handling of 128-bit vector VInsElement 
If none of the vectors alias the destination, then we can eliminate
an extra move and usage of a temporary.
 2023-09-17 16:56:23 -04:00
Lioncache 047646be6d Arm64/VectorOps: Elide moves in ASIMD VUShrNI2 if possible 
In the event the destination and lower source are the same, then
we don't need to perform any moves.
 2023-09-17 15:49:54 -04:00
Ryan Houdek 8168a49d10 Merge pull request #3112 from lioncash/assert 
Arm64/VectorOps: Assert VTMP1 and VTMP2 are sequential in VTBL2
 2023-09-17 12:40:47 -07:00
Lioncache 7f2fd4e9a0 Arm64/VectorOps: Assert VTMP1 and VTMP2 are sequential in VTBL2 
Ensures that if our temp vectors change in the future that this is
caught at compile-time rather than runtime.
 2023-09-17 15:22:39 -04:00
Lioncache 4ea9f08425 ARMEmitter: Mark index and conversion ops as constexpr 
Will be used for assertions. Also makes registers more flexible
for compile-time stuff in general.
 2023-09-17 15:19:44 -04:00
Lioncache 8ecdb341e2 Arm64/VectorOps: Fix SVE aliasing-path move in VSShr 
Seems like this was a typo from 8d11073, since we'd be moving
into a temporary and then never use it.
 2023-09-17 14:43:05 -04:00
Ryan Houdek 0c5c146fcf FEXCore/JitSymbols: Buffer writes to reduce overhead 
While this interface is usually pretty fast because it is a write and
forget operation, this has issues when there are multiple threads
hitting the perf map file at the same time. In particular this interface
becomes a bottleneck due to a locking mutex on writes in the kernel.

The situations when this bottleneck occurs is when a bunch of threads
get spawned and they are all jitting code as quickly as possible. In
particular Geekbench's clang benchmark hits this hard where each CPU
thread spends ~40% CPU time on all eight CPU threads because they are
stalled waiting for this mutex to unlock.

To work around this issue, buffer the writes a small amount. Either up
to a page-ish of data or 100ms of time. This completely eliminates
threads waiting on the kernel mutex.
- Around a page of buffer space was chosen by profiling Geekbench's
  clang benchmark and seeing how frequently it was still writing.
   - 1024 bytes was still fairly aggressive, 4096 seemed fine.
- 100ms was chosen to ensure we don't wait /too/ long to write JIT
  symbols.
   - In most cases 100ms is enough that you won't notice the blip in
     perf.

One thing of note is that with profiling enabled and checking the time
on every JIT block still ends up with 2-3% CPUtime in vdso
clock_gettime. We can improve this by using the cyclecounter directly
since that is still guaranteed to be monotonic. Maybe we'll come back to
that if it is actually an issue here.
 2023-09-16 17:52:46 -07:00
Ryan Houdek ad8b0c673f Merge pull request #3109 from lioncash/shlx 
OpcodeDispatcher: Improve output of SHLX/SHRX/SARX
 2023-09-15 18:49:36 -07:00
Ryan Houdek e574cfe681 Merge pull request #3108 from lioncash/mulx 
OpcodeDispatcher: Improve output of MULX
 2023-09-15 18:09:02 -07:00
Lioncache e9be291cec OpcodeDispatcher: Improve output of SHLX/SHRX/SARX 
We can remove some unnecessary moves for the 32-bit cases and
collapse the operations down to a single instruction.
 2023-09-15 21:05:50 -04:00
Lioncache d4f87c7db1 OpcodeDispatcher: Improve output of MULX 
We can cut down on a few of the generated moves. For
the case where both destinations alias one another,
we can just calculate the high part instead of both of them.
 2023-09-15 20:52:02 -04:00
Lioncache b0c8ff0ea6 Arm64/ALUOps: Remove spills in PEXT 
Reduces the number of emitted instructions for a
corresponding PEXT instruction.

We no longer spill for this IR op.
 2023-09-15 19:39:51 -04:00
Lioncache be90e76422 Arm64/ALUOps: mov in the case of full 32-bit/64-bit BFE 
Allows register-renaming mechanisms to be invoked more frequently
 2023-09-15 17:38:01 -04:00
Lioncache 4a37ea4819 OpcodeDispatcher: Handle RORX corner cases better 
There are a few cases where we were emitting code when we
didn't really need to, or could emit less.
 2023-09-15 17:36:36 -04:00
Ryan Houdek 6e08ac65b9 Merge pull request #3106 from lioncash/clwb 
HostFeatures: Fix x86 CLWB support check
 2023-09-15 14:06:54 -07:00
Lioncache 8705de1893 HostFeatures: Fix x86 CLWB support check 
This was clobbering the BMI2 boolean unintentionally.
 2023-09-15 16:38:45 -04:00
Alyssa Rosenzweig c8e7c347c3 Merge pull request #3100 from Sonicadvance1/optimize_cmov 
OpcodeDispatcher: Optimize cmov
 2023-09-15 15:17:51 -04:00
Lioncache e1ed7f43fd DeadContextStoreElimination: Turn LastAccessType into an enum class 
Makes the type stricter in terms of implicit conversions.
 2023-09-15 13:23:00 -04:00
Ryan Houdek d5b58eebaf OpcodeDispatcher: Optimize cmov 
cmov was quite terrible in its implementation. Some things of note:
- NZCV cache would cause store for no reason
- {16,32}-bit would zero extend sources for no reason
- 16-bit would zero extend result for no reason

A bunch of flag testing is still doing a ubfx plus compare against zero
when it could end up being a tst instead, but this is a step in the
right direction and switches over to explicit sized selects.
 2023-09-15 10:09:37 -07:00
Ryan Houdek 6dbbd9ecfc OpcodeDispatcher: Duplicate SelectCC but with Explicit result size 
This is a temporary measure as we are moving Select operations over to
explicit sizes. Once we remove all uses of SelectCC then it will get
removed.
 2023-09-15 10:09:37 -07:00
Ryan Houdek 759cc0025a OpcodeDispatcher: Add a dirty flag for tracking NZCV status 
Cached NZCV reads don't need to be written back at the end of the block.
This will remove one instruction from the end of some blocks.
 2023-09-15 10:09:37 -07:00
Lioncache d05f890147 DeadContextStoreElimination: Silence unused function warning 2023-09-15 13:08:32 -04:00
Alyssa Rosenzweig d29b8bab36 OpcodeDispatcher: Inline constant in PF calculation 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-15 12:33:53 -04:00
Alyssa Rosenzweig fc02f38435 IR: Only invert CF for NZCV if needed 
If we are going to throw away the updated value of CF anyway there is no point
wasting an instruction to invert CF. Add an IR toggle for that so the arm64 JIT
can make better choices.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-15 12:08:22 -04:00
Ryan Houdek d5782567e8 Merge pull request #3077 from Sonicadvance1/x86_shifted 
FEXCore: Implements support for shifted bitwise ops
 2023-09-15 08:09:35 -07:00
Ryan Houdek 060433621a Merge pull request #3097 from Sonicadvance1/disable_enhanced_tso 
FEXCore: Disable Enhanced REP MOVSB if Atomic TSO is enabled
 2023-09-15 08:08:36 -07:00
Ryan Houdek 9866e238d5 Merge pull request #3080 from Sonicadvance1/defer_softfloat 
FEXCore: Defer setting x87 softflow rounding mode until use
 2023-09-15 08:08:04 -07:00
Mai f5c4e28696 Merge pull request #3098 from Sonicadvance1/optimize_vectors_sve 
Arm64: Optimize wide shifts slightly for 64-bit OpSize
 2023-09-15 05:21:20 -04:00
Mai 96bbd01ad6 Merge pull request #3096 from Sonicadvance1/optimal_crc 
OpcodeDispatcher: Optimize CRC32
 2023-09-15 05:19:05 -04:00
Mai f84a264b0e Merge pull request #3095 from Sonicadvance1/bswap 
OpcodeDispatcher: Optimize 16-bit MOVBE
 2023-09-15 05:18:26 -04:00
Ryan Houdek d81d89c4fb IR: Changes Select operation to not have implicit sizes 
Changes the helper which all the source uses to still calculate the size
implicitly. This is going to take a while to convert all implicit uses
over to the explicit operation.

Get us started by at least having the IR operation itself be explicit.
 2023-09-14 20:48:16 -07:00