Ryan Houdek
b42b4e03a4
Merge pull request #2218 from Sonicadvance1/GOT_optimization
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OpCodeDispatcher: Optimize a case of GOT calculation
2022-12-12 09:02:18 -08:00
Ryan Houdek
ab14375a03
Merge pull request #2222 from lioncash/rsqrt
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OpcodeDispatcher: Handle VRSQRTSS/VRSQRTPS
2022-12-12 09:02:04 -08:00
lioncash
c4c93f5bfe
OpcodeDispatcher: Handle VRSQRTSS
2022-12-12 16:30:34 +00:00
lioncash
3504ba068e
OpcodeDispatcher: Handle VRSQRTPS
2022-12-12 16:11:16 +00:00
lioncash
88b88c9cd3
OpcodeDispatcher: Handle VBROADCASTI128
2022-12-12 15:51:12 +00:00
lioncash
e99928990e
OpcodeDispatcher: Handle VPBROADCASTQ
2022-12-12 15:41:41 +00:00
lioncash
6733f83471
OpcodeDispatcher: Handle VPBROADCASTD
2022-12-12 15:37:59 +00:00
lioncash
a14cce27a4
OpcodeDispatcher: Handle VPBROADCASTW
2022-12-12 15:34:17 +00:00
lioncash
04d5b53389
OpcodeDispatcher: Handle VPBROADCASTB
2022-12-12 15:31:17 +00:00
Ryan Houdek
a6b0181cd4
OpCodeDispatcher: Optimize a case of GOT calculation
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32-bit GOT calculation needs to do a call+pop to do get the EIP on
32-bit. LEA doesn't work because it there is no EIP relative ops like on
x86-64.
This causes a terrible block split on every GOT calculation without the
optimization in place.
Now the block can continue through this weird GOT calculation.
This will be worthwhile for our 32-bit thunks where for some reason the
GOT calculation can't be removed. The GOT is calculated even though it
isn't used.
2022-12-10 02:50:48 -08:00
lioncash
b891999a7f
OpcodeDispatcher: Handle VBROADCASTF128
2022-12-08 03:18:58 +00:00
lioncash
a53fd07bda
OpcodeDispatcher: Handle VBROADCASTSD
2022-12-08 02:58:12 +00:00
lioncash
8f213b75be
OpcodeDispatcher: Handle VBROADCASTSS
2022-12-08 02:40:36 +00:00
Ryan Houdek
b73aeb8902
Merge pull request #2214 from lioncash/stmxcsr
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OpcodeDispatcher: Handle VLDMXCSR/VSTMXCSR
2022-12-07 17:07:07 -08:00
lioncash
d642c1a646
OpcodeDispatcher: Handle VLDMXCSR/VSTMXCSR
2022-12-08 00:42:13 +00:00
lioncash
e42de0b645
OpcodeDispatcher: Handle VSQRTSD
2022-12-07 22:42:16 +00:00
lioncash
9ef5247dd7
OpcodeDispatcher: Handle VSQRTSS
2022-12-07 22:42:16 +00:00
lioncash
25428cb28c
OpcodeDispatcher: Handle VSQRTPD
2022-12-07 22:42:16 +00:00
lioncash
2125949d6d
OpcodeDispatcher: Handle VSQRTPS
2022-12-07 22:42:16 +00:00
Ryan Houdek
7ac21e794d
Merge pull request #2212 from lioncash/comiss
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OpcodeDispatcher: Handle VCOMISD/VCOMISS/VUCOMISD/VUCOMISS
2022-12-07 14:38:49 -08:00
lioncash
4aa0f3d0a4
OpcodeDispatcher: Handle VCOMISD
2022-12-07 22:06:25 +00:00
lioncash
740c983f65
OpcodeDispatcher: Handle VCOMISS
2022-12-07 22:06:25 +00:00
lioncash
83bccc0032
OpcodeDispatcher: Handle VUCOMISD
2022-12-07 22:06:22 +00:00
lioncash
d1ab636df1
OpcodeDispatcher: Handle VUCOMISS
2022-12-07 21:22:19 +00:00
lioncash
26b629833e
OpcodeDispatcher: Handle VPAVGW
2022-12-07 21:07:43 +00:00
lioncash
95964f8dd8
OpcodeDispatcher: Handle VPAVGB
2022-12-07 21:07:40 +00:00
Ryan Houdek
94ae2e3a9c
Merge pull request #2209 from lioncash/ins
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IR: Handle 128-bit VInsElement with SVE
2022-12-07 11:08:47 -08:00
lioncash
eae33b0c50
IR: Handle 128-bit VInsElement with SVE
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Currently VDupElement allows duplicating 128-bit elements in 256-bit
vectors with SVE, so we can extend VInsElement to have similar behavior.
2022-12-07 18:41:45 +00:00
Ryan Houdek
e9aa368a62
Merge pull request #2208 from lioncash/zero
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OpcodeDispatcher: Explicitly zero upper lanes
2022-12-07 10:13:53 -08:00
lioncash
5a37786da7
OpcodeDispatcher: Explicitly zero upper lanes
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Makes our intent to zero-extend the upper lanes explicit and lets us
remove a special case in the LoadSource implementation.
This also makes things a little nicer since we're not hardcoding 32 byte
stores.
2022-12-07 17:22:20 +00:00
lioncash
4cf3805950
OpcodeDispatcher: Handle VADDSD
2022-12-07 16:43:47 +00:00
lioncash
1f5a1826a6
OpcodeDispatcher: Handle VADDSS
2022-12-07 16:43:44 +00:00
lioncash
6a63ae2d9c
OpcodeDispatcher: Merge PHADD into VectorALUOp
2022-12-07 15:18:19 +00:00
lioncash
a7a1e2abd3
OpcodeDispatcher: Merge HADDP into VectorALUOp
2022-12-07 15:14:10 +00:00
lioncash
047ae13c98
OpcodeDispatcher: Merge PAVGOp with VectorALUOp
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This can be merged into it, considering it only has one IR op.
2022-12-07 14:51:08 +00:00
lioncash
3d5e0c5832
OpcodeDispatcher: Merge PSUBSOp with VectorALUOp
2022-12-06 01:31:26 +00:00
lioncash
71a36763df
OpcodeDispatcher: Merge PADDSOp with VectorALUOp
2022-12-06 01:27:31 +00:00
lioncash
07bd3137ef
OpcodeDispatcher: Merge PSUBQOp with VectorALUOp
2022-12-06 01:21:33 +00:00
lioncash
c2b40b4dd3
OpcodeDispather: Merge PADDQOp with VectorALUOp
2022-12-06 01:13:12 +00:00
lioncash
db74e46fc3
OpcodeDispatcher: Merge ANDNOp with VectorALUROp
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Now that ANDNOp is reduced to one IR op, we can merge it with
VectorALUROp
2022-12-05 22:28:39 +00:00
lioncash
13bba59ba6
OpcodeDispatcher: Simplify ANDNOp and VANDNOp
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We can just use VBic here to simplify everything.
2022-12-05 22:15:15 +00:00
lioncash
6b259e2731
OpcodeDispatcher: Handle VPADDQ
2022-12-05 17:53:33 +00:00
lioncash
200660aba5
OpcodeDispatcher: Handle VPADDD
2022-12-05 17:44:12 +00:00
lioncash
065c12cfbb
OpcodeDispatcher: Handle VPADDW
2022-12-05 17:33:52 +00:00
lioncash
318972620f
OpcodeDispatcher: Handle VPADDB
2022-12-05 17:23:39 +00:00
lioncash
e7f54d1592
OpcodeDispatcher: Handle VADDPD
2022-12-05 16:59:04 +00:00
lioncash
a8571282b2
OpcodeDispatcher: Handle VADDPS
2022-12-05 16:43:26 +00:00
Ryan Houdek
69f39a0bc3
Arm64: Const on unmodified argument
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Just noticed this when tinkering around the JIT.
These arguments can safely be const.
2022-12-05 03:54:17 -08:00
Ryan Houdek
5e46d63c42
Arm64: Minor optimization in AESKEYGENASSIST
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The less number of FPR<->GPR movement instructions the better.
This removes one instance of `ins` and replaces the other with a 64-bit
`dup` instead.
The LoadConstant still turns in to a single `movz` instruction with the
shift.
2022-12-03 03:59:27 -08:00
lioncash
02a2292115
OpcodeDispatcher: Handle VPANDN
2022-11-30 15:51:10 +00:00
Ryan Houdek