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OpcodeDispatcher: Merge ANDNOp with VectorALUROp

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Now that ANDNOp is reduced to one IR op, we can merge it with
VectorALUROp
This commit is contained in:
lioncash committed 2022-12-05 22:28:39 +00:00
1 parent 13bba59ba6
commit db74e46fc3
3 files changed
+6 -16
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+4 -4
View File
@@ -6081,7 +6081,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0x52, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRSQRT, 4, false>},
{0x53, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRECP, 4, false>},
{0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
{0x55, 1, &OpDispatchBuilder::ANDNOp},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
{0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
{0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 4>},
@@ -6127,7 +6127,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0xDC, 1, &OpDispatchBuilder::PADDSOp<1, false>},
{0xDD, 1, &OpDispatchBuilder::PADDSOp<2, false>},
{0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
{0xDF, 1, &OpDispatchBuilder::ANDNOp},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0xE0, 1, &OpDispatchBuilder::PAVGOp<1>},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
@@ -6371,7 +6371,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0x50, 1, &OpDispatchBuilder::MOVMSKOp<8>},
{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 8, false>},
{0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
{0x55, 1, &OpDispatchBuilder::ANDNOp},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
{0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
{0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 8>},
@@ -6428,7 +6428,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0xDC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 1>},
{0xDD, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 2>},
{0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
{0xDF, 1, &OpDispatchBuilder::ANDNOp},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0xE0, 1, &OpDispatchBuilder::PAVGOp<1>},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
Vendored
-1
View File
@@ -378,7 +378,6 @@ public:
void VFCMPOp(OpcodeArgs);
template<size_t ElementSize>
void SHUFOp(OpcodeArgs);
void ANDNOp(OpcodeArgs);
template<size_t ElementSize>
void PINSROp(OpcodeArgs);
void InsertPSOp(OpcodeArgs);
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
Vendored
+2 -11
View File
@@ -443,6 +443,8 @@ void OpDispatchBuilder::VectorALUROp(OpcodeArgs) {
StoreResult(FPRClass, Op, ALUOp, -1);
}
template
void OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>(OpcodeArgs);
template
void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 4>(OpcodeArgs);
template
@@ -772,17 +774,6 @@ void OpDispatchBuilder::SHUFOp<4>(OpcodeArgs);
template
void OpDispatchBuilder::SHUFOp<8>(OpcodeArgs);
void OpDispatchBuilder::ANDNOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
// Dest = ~Src1 & Src2
auto Dest = _VBic(Size, Size, Src2, Src1);
StoreResult(FPRClass, Op, Dest, -1);
}
void OpDispatchBuilder::VANDNOp(OpcodeArgs) {
const auto Size = GetSrcSize(Op);
const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE;