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a94aaca0ec3faeabe08fade9d4f9fadd47aabeef
Commit Graph
482 Commits
Author SHA1 Message Date
Ryan Houdek a94aaca0ec OpcodeDispatcher: Add default FEX_UNREACHABLE 
This can't happen but if it changes then make sure we capture it.
 2024-09-08 18:03:20 -07:00
Alyssa Rosenzweig e9ab514962 IR: push parity evaluation down 
so we can optimize it globally

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-09-07 08:26:04 -04:00
Billy Laws f7b911ca43 OpcodeDispatcher: Do not forbid INT 2E syscalls on 64-bit Windows 
This works fine on real Windows and is relied on by wine as SystemCall
is set to 1 in KUSER_SHARED_DATA, which causes the ntdll thunks to use
it over `syscall`
 2024-09-06 15:58:17 +00:00
Ryan Houdek fd4f6b8020 FEXCore: Dynamically scale TSC 
When I implemented TSC scaling originally, I chose a scale factor of 128
because it basically covered the range of devices we cared about without
going too high. I also only tested devices that had a TSC scale factor
from 19.2Mhz to 34Mhz. Turns out there is hardware that also has a 48Mhz
cycle counter, which cause them to effectively have a 6.1Ghz cycle
counter, which is kind of absurd.

Instead of a fixed scale, just calculate the amount of scaling we need
to get >= the minimum threshold of 1Ghz. This will change the shift from
7 to 5 or 6 for the faster cycle counter devices.

Of course if someone wants to know the scale factor they can still use
cpuid function 15h to know it.

Fixes #4026
 2024-09-03 13:41:31 -07:00
Alyssa Rosenzweig 335cd9180e OpcodeDispatcher: optimize mul rax 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-27 12:32:43 -04:00
Mai 2829ad56a1 Merge pull request #3996 from Sonicadvance1/more_bind 
OpcodeDispatcher: Convert more template handlers to Bind handlers
 2024-08-23 18:27:59 -04:00
Billy Laws ef823ce82b OpcodeDispatcher: Allow x86 code to read CNTVCT on ARM64EC 
Required by newer insider preview versions, I noticed many crashes with
this exception number and QueryPeformanceCounter in the backtrace,
testing with XTA found it to not be passed through and instead write
the host CNTVCT (unscaled) into RAX. No other registers seem to be
affected.
 2024-08-23 21:46:11 +00:00
Ryan Houdek 1d00ad6030 OpcodeDispatcher: Convert VectorVariableBlend to Bind handler 2024-08-22 15:09:44 -07:00
Ryan Houdek 23a076c313 OpcodeDispatcher: Convert packed vector shifts to Bind handler 2024-08-22 15:07:09 -07:00
Ryan Houdek 57eacab654 OpcodeDispatcher: Convert VBROADCASTOp to Bind handler 2024-08-22 14:59:25 -07:00
Ryan Houdek b4093a8888 OpcodeDispatcher: Convert packed HSub to Bind handler 2024-08-22 14:57:40 -07:00
Ryan Houdek 7c5a9b5d6a OpcodeDispatcher: Convert AVXVectorVariableBlend to Bind handler 2024-08-22 14:55:34 -07:00
Ryan Houdek 12b3c82d83 OpcodeDispatcher: Convert PExtr to Bind handler 2024-08-22 14:54:26 -07:00
Ryan Houdek 66520bce0a OpcodeDispatcher: Convert VPACK{U,S}S to Bind handler 2024-08-22 14:52:41 -07:00
Ryan Houdek 25cc2bdcb8 OpcodeDispatcher: Convert VPERMILImm to Bind handler 2024-08-22 14:51:02 -07:00
Ryan Houdek f98b18800c OpcodeDispatcher: Convert MOVMSK to Bind handler 2024-08-22 14:49:57 -07:00
Ryan Houdek 0dd687a7a1 OpcodeDispatcher: Convert SHUFOp to Bind handler 2024-08-22 14:47:30 -07:00
Ryan Houdek 1aff3acbb9 OpcodeDispatcher: Convert PSHUFW to Bind handler 2024-08-22 14:45:04 -07:00
Ryan Houdek a6ab2ca30d OpcodeDispatcher: Convert PUNPCKH to Bind handler 2024-08-22 14:42:24 -07:00
Ryan Houdek ca43e2a61c OpcodeDispatcher: Convert PUNPCKL to Bind handler 2024-08-22 14:39:45 -07:00
Alyssa Rosenzweig ce8e6e5c0c OpcodeDispatcher: optimize adc 0 
clang generates this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-22 10:51:06 -04:00
Alyssa Rosenzweig 6951284924 OpcodeDispatcher: optimize ADCX/ADOX 
rewrite to use native adcs with flag fixups.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig b03c613fbf OpcodeDispatcher: optimize JP/JNP 
fuse and+cbnz into tbz/tbnz.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig b893bdb8df OpcodeDispatcher: optimize fcmovu 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig db45f6eec8 OpcodeDispatcher: optimize test with small immediate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig 5d613e8716 OpcodeDispatcher: optimize test x, x 
fewer uops now that we invert carry

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 21:17:08 -04:00
Alyssa Rosenzweig 84e4960e52 OpcodeDispatcher: optimize btc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 09:24:02 -04:00
Alyssa Rosenzweig e5cb583cc0 OpcodeDispatcher: optimize 8-bit rol 
rotate right by less than 8:

  ror(________________7654321076543120, ...)

rotate left by less than 8:

  rol(76543210________________76543210, ...)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 10:40:53 -04:00
Alyssa Rosenzweig 3ef83a9e23 OpcodeDispatcher: optimize ror al, cl 
rely on the masking.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 10:40:53 -04:00
Alyssa Rosenzweig 7de6a5cb07 OpcodeDispatcher: optimize rotate flags 
introduce an IR op for it so we can reason about flags across rotate
instructions easily.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 10:40:53 -04:00
Alyssa Rosenzweig c495f82f4f OpcodeDispatcher: optimize 8/16-bit bitwise with constants 
avoid masking. apparently even modern compilers will do cute tricks with 8-bit
math in hot loops ...

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 08:54:47 -04:00
Ryan Houdek 2eb7a9ff28 OpcodeDispatcher: Remove old bad assumption in INC/DEC 
Somewhere there was an assumption made that INC and DEC supported the
repeat prefix. This isn't actually the case, while the prefix can be
encoded, it is a nop and should only expect to be used for padding.

Adds a unittest to ensure that behaviour is as expected.
 2024-08-15 10:22:31 -07:00
Alyssa Rosenzweig 0db17bd58a OpcodeDispatcher: optimize IRET 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Alyssa Rosenzweig aac16493f1 OpcodeDispatcher: optimize RET 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Alyssa Rosenzweig c70e44cf05 OpcodeDispatcher: extract Push helper 
Mirrors the Pop helper we added. This cleans up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig ede13e37d9 OpcodeDispatcher: optimize Thunk 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig a7dada457a OpcodeDispatcher: optimize POPF 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 6367554d30 OpcodeDispatcher: optimize LEAVE 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 81969a684e OpcodeDispatcher: optimize pop segment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig ee339b5960 OpcodeDispatcher: optimize POPA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 881c940693 OpcodeDispatcher: optimize POP 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 74f341bc0e IR: remove pair from cpuid 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig feaa1af1a8 IR: remove pair from XGetBV 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig a9c26cbf71 IR: add coalescing heuristics for pair replacements 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig f4b5c4e69a OpcodeDispatcher: allow upper garbage for cmpxchg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 13974df204 IR: drop CASPair pair result 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig fa6fe9bf06 IR: drop cmppairz pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 746be0824e IR: drop CASPair source pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 93120cabbb IR: drop pair from memcpy 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 40812efaae OpcodeDispatcher: better handle SIB indexing 
if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00