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7,401 Commits 11 Branches 71 Tags
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Commit Graph
61 Commits
Author SHA1 Message Date
Ryan Houdek 189b0da68f JIT/Int: Add support for scalar conversion as well 2023-08-25 03:19:11 -07:00
Ryan Houdek 62156f2152 ARM64JIT: Adds support for scalar cvt 2023-08-25 02:34:30 -07:00
Ryan Houdek 72ce7ddf2d Arm64: Optimize CVT operations for 64-bit variants 
Using 128-bit converts for 64-bit versions cuts their throughput in half
on Cortex. Ensure we use the 64-bit version when possible.
 2023-08-24 15:45:07 -07:00
Ryan Houdek ba01eac467 IR: Adds support for ARM's FCMA FCADD instruction 2023-08-24 15:00:41 -07:00
Lioncache 42ccc18606 x86_64/MemoryOps: Fix mislabeled IR op messages 2023-08-23 22:54:36 -04:00
Ryan Houdek 05b9651279 IR: Implements new vector multiply returning high bits 
SVE implemented a new instruction that does this explicitly, so we
should support it directly.
 2023-08-23 18:38:05 -07:00
Ryan Houdek 6e4765d48b Merge pull request #2989 from lioncash/ins 
Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR
 2023-08-23 18:09:15 -07:00
Ryan Houdek 172c8f3ba6 Merge pull request #2988 from lioncash/half 
Arm64/ConversionOps: Add missing half-precision conversions to scalar functions
 2023-08-23 17:56:23 -07:00
Lioncache 203a2b1105 Arm64/ConversionOps: Remove redundant moves in AdvSIMD VInsGPR 
If Dst and DestVector alias one another, then we don't need to
move the vector unnecessarily.
 2023-08-23 20:50:21 -04:00
Ryan Houdek 4297e13fcf Merge pull request #2986 from lioncash/ext 
Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible
 2023-08-23 17:40:50 -07:00
Lioncache 5ad56ad52e Arm64/ConversionOps: Add missing half-precision operations to Float_FromGPR_S 
Provides parity with vector operations.
 2023-08-23 20:36:34 -04:00
Lioncache 24e7baf28f Arm64/ConversionOps: Add missing half-precision conversions to Float_FToF 
Provides parity with the vector conversion operations.
 2023-08-23 20:31:49 -04:00
Lioncache b248ae4c04 Arm64/VectorOps: Remove redundant moves from SVE SQSHL 
We don't need to emit a move if the destination and source alias.
 2023-08-23 20:12:09 -04:00
Lioncache 95bea864cf Arm64/VectorOps: Remove redundant moves from SVE SRSHR 
We don't need to perform a move is the destination aliases
the source vector to be shifted.
 2023-08-23 20:10:51 -04:00
Lioncache 47c4507bb6 Arm64/VectorOps: Remove redundant moves from SVE VSQXTUN2 
We don't need to perform a move if the destination aliases the lower vector.
 2023-08-23 20:10:29 -04:00
Lioncache 5ea0b6db28 Arm64/VectorOps: Remove redundant moves from SVE VSQXTN2 
We don't need to perform a move if the destination aliases the
lower vector.
 2023-08-23 20:02:28 -04:00
Mai ee10153d14 Merge pull request #2984 from Sonicadvance1/optimize_pack 
OpcodeDispatcher: Use new IR ops for pack instructions
 2023-08-23 20:02:16 -04:00
Lioncache d0d94adabe Arm64/VectorOps: Remove redundant moves in SVE VExtr when possible 
We don't need to do any moves here is the destination aliases the
lower bits.
 2023-08-23 19:56:10 -04:00
Ryan Houdek 926b8c2c97 Merge pull request #2985 from lioncash/shift 
Arm64/VectorOps: Remove redundant moves from SVE variable/immediate/vector shifts when possible
 2023-08-23 16:41:39 -07:00
Lioncache 18ebcdc9de Arm64/VectorOps: Remove redundant moves in VUshrNI2 
If the destination and VectorLower alias, then we don't need
to emit a movprfx.
 2023-08-23 18:52:32 -04:00
Lioncache f31a9a52e6 Arm64/VectorOps: Remove redundant moves from SVE immediate vector shifts when possible 
If the destination and source vector alias one another, then the
operation can largely be done in place.
 2023-08-23 18:36:21 -04:00
Lioncache 03504a5f8c Arm64/VectorOps: Remove redundant moves from SVE vector shifts when possible 
If the destination and the vector to be shifted alias, then we can
avoid needing to move some data around.
 2023-08-23 18:24:58 -04:00
Lioncache d29b4de1ee Arm64/VectorOps: Remove redundant moves from SVE variable vector register shifts when possible 
In the event that the destination and the vector to be shifted
alias one another, then we can skip the movprfx, since it's not
necessary.
 2023-08-23 18:24:53 -04:00
Ryan Houdek c508570da0 IR: Implements VSQXT{U,}NPair operations 
This takes the two independent VSXT{U}N{2,} operations and merges them
in to a single IR operations.
In some cases this can result in a more optimal implementation since
there is no need for moves inbetween.
 2023-08-23 15:13:07 -07:00
Lioncache d5e145c4b0 Arm64/VectorOps: Remove redundant moves from SVE BSL when possible 
If the destination and true vector alias one another, then we can
perform the operation in place instead of moving data around.
 2023-08-23 17:54:10 -04:00
Ryan Houdek 350bca97c6 Merge pull request #2982 from lioncash/imin 
Arm64/VectorOps: Remove redundant moves from SVE V{S,U}Min/V{S,U}Max when possible
 2023-08-23 14:53:15 -07:00
Ryan Houdek 226405880f Merge pull request #2981 from lioncash/fmin 
Arm64/VectorOps: Remove redundant moves from SVE VFMin/VFMax when possible
 2023-08-23 14:46:03 -07:00
Lioncache 37a8cb6821 Arm64/VectorOps: Remove redundant moves from SVE VSMax when possible 
When the destination and first source alias one another, then we
can perform the operation in place instead of moving data around.
 2023-08-23 17:34:52 -04:00
Lioncache fe2c7dbf97 Arm64/VectorOps: Remove redundant moves from SVE VUMax when possible 
When the destination and source alias one another, then we
can perform the operation in place without needing to move
data around.
 2023-08-23 17:32:17 -04:00
Lioncache 787b4f37fb Arm64/VectorOps: Remove redundant moves from SVE VSMin when possible 
When the destination and first source alias one another, then we can
perform the operation in place without moving any data.
 2023-08-23 17:30:08 -04:00
Lioncache c3faa019f5 Arm64/VectorOps: Remove redundant moves from SVE VUMin when possible 
If the destination and first source alias, then we can perfom the operation
in place.
 2023-08-23 17:27:52 -04:00
Ryan Houdek da098d8204 Merge pull request #2979 from lioncash/div 
Arm64/VectorOps: Remove moves from SVE VFDiv if possible
 2023-08-23 14:22:46 -07:00
Lioncache 149852b122 Arm64/VectorOps: Remove redundant moves from SVE VFMax if possible 
If Dst and Vector1 alias one another, then the operation can be
performed in place instead of moving data around.
 2023-08-23 17:18:41 -04:00
Lioncache ecf02846e6 Arm64/VectorOps: Remove redundant moves from SVE VFMin is possible 
If Dst and Vector1 alias one another, then we can do the merging move
in place instead of shuffling data around.
 2023-08-23 17:16:25 -04:00
Lioncache a8f7529847 Arm64/VectorOps: Remove moves from SVE VFDiv if possible 
Given the operation is:

Dst = Vector1 / Vector2

If Dst and Vector1 alias one another, then we can just perform
the division as is without any moving of data around.
 2023-08-23 16:53:56 -04:00
Lioncache 8431ab43a0 Arm64/VectorOps: Remove redundant moves from SVE VURAvg if possible 
If Dst and Vector1 alias one another, then we can perform the operation
without needing to move any data around.
 2023-08-23 16:51:17 -04:00
Lioncache 393cea2e8b Arm64/ConversionOps: Correct AdvSIMD round-to-nearest Vector_FToI case 
This was previously using frinti, which uses the host rounding mode, rather
than round to nearest.
 2023-08-23 13:27:44 -04:00
Lioncache e89321dc60 Arm64/ConversionOps: Add scalar support to Vector_FToI 
This can be used for the scalar conversions instead of always using the
vector variants.
 2023-08-23 13:23:07 -04:00
Mai 0819338dbf Merge pull request #2970 from Sonicadvance1/optimize_pminmax 
Arm64: Optimize VFMin/VFMax
 2023-08-23 12:39:37 -04:00
Ryan Houdek f0b1030e54 Arm64: Optimize VFMin/VFMax 
We can be more optimal on the selects. This makes 3DNow! and SSE packed
min/max operations optimal.
 2023-08-22 20:59:11 -07:00
Ryan Houdek 6aa2cab41c IR: Implement support for vector store element 
Matches ARM64 ST1 semantics
 2023-08-22 20:42:24 -07:00
Ryan Houdek 5e57ec94cf IR: Implement support for vector load element 
Matches Arm64 LD1 semantics.
 2023-08-22 20:15:16 -07:00
Lioncache 398a70312e Arm64: Optimize SVE VInsElement 
This can be done without storing any data to memory and also
compressing the amount of instructions being used.

Thanks to @dougallj for the optimization suggestions.
 2023-08-22 20:36:29 -04:00
Ryan Houdek bbf9cb9d52 IR: Implements new VRev32 and LoadNamedVectorConstant ops 
VRev32 matches Arm64 semantics directly.
LoadNamedVectorConstant allows FEX to quickly load "named constants".
This will allow us to have specific hardcoded vector constant values
that we can load with a ldr(State)+ldr(Value) and will be more abused in
the future.
This also allows us to do a very simple optimization in the future where
we can optimize away redundant loads of these loads if they are used
multiple times in the same block. (Not implemented here).
 2023-08-22 16:29:06 -07:00
Mai 3c49b3238a Merge pull request #2949 from Sonicadvance1/optimize_phsub 
OpcodeDispatcher: Optimize phsub
 2023-08-21 21:39:02 -04:00
Ryan Houdek 2d7a3a578e Merge pull request #2931 from Sonicadvance1/optimize_psign 
Optimize PSIGN and VBSL
 2023-08-21 18:30:55 -07:00
Ryan Houdek 30e9beba51 JIT64: Fixes i32v2 unzips 
This has just been broken since it was implemented. Turns out we had
never used these with XMM operations before today.
 2023-08-21 17:38:24 -07:00
Ryan Houdek a3bf952f2b IR: Implements support for wide scalar shifts 
This matches x86 vector shift behaviour closely for ps{rl,ra,ll}{w,d,q}
where the vector is shifted by a scalar value that is 64-bits wide.
Anything larger than the element size will set that element to zero.

With SVE we have some new wide element shifts that match this behaviour
exactly (except supports wide shift sources rather than scalar).

This is a significant improvement even on platforms that only support
128-bit SVE.
 2023-08-20 19:16:40 -07:00
Ryan Houdek ac77986c44 IR: Implements support for saturating/rounding vector shifts 2023-08-20 13:38:23 -07:00
Ryan Houdek c5f5a03c68 OpcodeDispatcher: Optimize PSIGN 
This dramatically improves the performance of the PSIGN instructions.
 2023-08-20 13:38:23 -07:00