Lioncache
d7a08fc7d4
CodeEmitter/ASIMDOps: Support RADDHN{2}/RSUBHN{2}
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These are trivial enough to just drop right in.
2025-04-17 20:13:30 -04:00
LC
572d6e0395
Merge pull request #4509 from Sonicadvance1/in_the_twilight_of_the_pale_blue_moon
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A couple of barrier and timing fixes.
2025-04-17 17:30:03 -04:00
Lioncache
bafcc8762b
CodeEmitter/ScalarOps: Handle ASIMD scalar x indexed element group
2025-04-17 14:47:38 -04:00
Lioncache
ec6ff7899d
CodeEmitter/ScalarOps: Remove implemented TODO
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These scalar ops are already implemented and this was accidentally left in.
2025-04-17 08:14:10 -04:00
Lioncache
6330b398a5
CodeEmitter/ScalarOps: Handle ASIMD scalar three same extra group
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These are trivial enough to drop in.
2025-04-17 08:09:42 -04:00
Ryan Houdek
da1868288d
CodeEmitter: Fixes misaligned function
2025-04-15 15:47:31 -07:00
Ryan Houdek
753c5e72be
CodeEmitter: Implement support for CNTVCTSS_EL0
2025-04-15 15:37:02 -07:00
Lioncache
222fcfd70e
CodeEmitter/ASIMDOps: Add crypto two-register SHA512 category
2025-04-15 11:48:30 -04:00
Lioncache
95c8a70ce6
CodeEmitter/ASIMDOps: Add crypto four-reg category
2025-04-15 11:41:07 -04:00
Lioncache
0f6bec4d5e
CodeEmitter/ASIMDOps: Add crypto three-reg SHA512 category
2025-04-15 11:31:00 -04:00
Lioncache
5fb0522c78
CodeEmitter/ASIMDOps: Add crypto three-reg imm2 category
2025-04-15 11:15:21 -04:00
Ryan Houdek
aa0fc9071e
CodeEmitter: Fixes typo in sha256h2
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This was accidentally encoding as sha256h.
2025-04-02 12:38:47 -07:00
Lioncache
5708846a07
CodeEmitter/Registers: Replace use of deprecated std::is_trivial_v template
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std::is_trivial/std::is_trivial_v is deprecated in C++26, so we can just
use a more specific trait and be more explicit about what we want.
Also some of these static_asserts were testing the constraints of the wrong
class, so we can tidy those up as well.
2025-03-29 00:28:14 -04:00
Ryan Houdek
fd28783f85
Merge pull request #4457 from lioncash/crypto
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CodeEmitter/SVEOps: Add SVE2 crypto operations
2025-03-28 14:55:40 -07:00
Lioncache
63f72621fc
CodeEmitter/SVEOps: Add SVE2 crypto constructive binary operations
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Likewise, these are now also available to test against in vixl.
2025-03-28 16:21:21 -04:00
Lioncache
580a8c9c61
CodeEmitter/SVEOps: Add SVE2 crypto destructive binary operations
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These are also now available in vixl to run disassembly tests against.
2025-03-28 16:09:41 -04:00
Lioncache
249351cef4
CodeEmitter/SVEOps: Add SVE2 crypto unary operations
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Now that these are available in vixl, we finally have something to test against.
2025-03-28 15:59:16 -04:00
Lioncache
497ee32f59
CodeEmitter: Generify data writing
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Lets us tidy up the repeated generation code a little bit
(and also allow for generic data writing, should it ever be needed)
2025-03-28 09:55:35 -04:00
Ryan Houdek
b0b41d00ee
Various: More static analysis warnings cleanup
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NFC
2025-03-12 17:27:41 -07:00
Ryan Houdek
c8d234a767
CodeEmitter: Adds missing assert checks
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We weren't checking if the post-index variants of these instructions
were using the correct post-offset. These support /only/ the correctly
sized post-index. The no-offset version is an entirely different set of
functions.
2025-03-04 20:18:16 -08:00
Ryan Houdek
8d3918b4f0
CodeEmitter: Update tests and new assert for unallocated instruction encoding
2025-02-23 03:31:43 -08:00
Tony Wasserka
bb30a2eb1e
CodeEmitter: Remove unused member function
2025-02-16 16:30:05 +01:00
Ryan Houdek
cd5f42ec79
CodeEmitter: Minor fixes to SVE fcvtz{u,s}
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We had duplicated code paths in the ternary selection for 64-bit source
size, and on 32-bit source size 16-bit is an invalid target so the
second ternary was dead.
2025-02-12 23:09:41 -08:00
Ryan Houdek
bc6ae7feb4
CodeEmitter: Fixes clang_format
2025-01-26 19:05:50 -08:00
Tony Wasserka
264f3be8b4
CodeEmitter: Remove unused Bind validation logic
2025-01-22 18:25:35 +01:00
Tony Wasserka
4282f96d35
CodeEmitter: Use inline constexpr constants over constexpr functions
2025-01-22 18:25:35 +01:00
Tony Wasserka
9cdd759fc1
CodeEmitter: Convert template specialization into function overload
2025-01-22 18:25:35 +01:00
Tony Wasserka
403e8f8702
CodeEmitter: Unify SingleUseForwardLabel and ForwardLabel
2025-01-22 18:25:35 +01:00
Tony Wasserka
8760c593ec
CodeEmitter: Reformat inl files
2025-01-21 21:28:33 +01:00
Tony Wasserka
ad695bdd59
CodeEmitter: Allow inl headers to be processed by external tooling
2025-01-21 21:28:33 +01:00
Tony Wasserka
da58e6a597
Fix warnings about unused variables
2025-01-21 12:07:33 +01:00
Tony Wasserka
e54b9237c6
Drop use of assume-asserting logging macros
2025-01-21 12:01:33 +01:00
Ryan Houdek
bb630797b5
CodeEmitter: Add support for TPIDRRO_EL0
2024-10-25 15:07:15 -07:00
Ryan Houdek
2da700fe82
CodeEmitter: Removes some ternaries that are unnecessary
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NFC
2024-09-08 18:03:20 -07:00
Alyssa Rosenzweig
5fbf76ee9e
CodeEmitter: mask immediate shifts
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more convenient for constprop and not really any more expensive.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-09-08 10:26:58 -04:00
Ryan Houdek
a4d5302369
Arm64: Adds Int helpers
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One more vixl step removed.
2024-08-03 21:40:28 -07:00
Ryan Houdek
6ff3c90af3
CodeEmitter: Removes vestigial vixl usage
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- IsImmLogical already existed in our CodeEmitter. We just forgot to
allow nullptr arguments and to use it.
- Adds an equivalent IsImmAddSub helper and uses it
This gets us closer to removing vixl's global initializers from FEXCore.
2024-08-03 21:04:56 -07:00
Ryan Houdek
c9efb75714
CodeEmitter: Implement support for SVE NT loads
2024-07-10 23:06:19 -07:00
Ryan Houdek
472a373861
Merge pull request #3786 from Sonicadvance1/non_temporal_stores
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OpcodeDispatcher: Implement support for non-temporal vector stores
2024-07-01 18:57:38 -07:00
Ryan Houdek
fb7167c2d2
CodeEmitter: Fixes vector {ldr,str}{b,h} with reg-reg source
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We had failed to enable these implementations for the
`ExtendedMemOperand` helpers. We had already implemented the non-helper
forms, which are already tested in CI. These helpers just weren't
updated?
Noticed this when running libaom's SSE4.1 tests, where it managed to
execute a pmovzxbq instruction with reg+reg memory source and was
breaking the test results.
There are /very/ few vector register operations that access only 8-bit
or 16-bit in vectors so this flew under the radar for quite a while.
Fixes their unit tests.
Also adds a unittest using sse4.1 pmovzxbq to ensure we support the
reg+reg case, and also a few other instructions to test 8-bit and 16-bit
vector loads and stores.
2024-07-01 17:03:47 -07:00
Ryan Houdek
8ab4ab29f8
CodeEmitter: Add SVE contiguous non-temporal instructions
2024-06-29 21:51:58 -07:00
Ryan Houdek
c5359264a3
VixlUtils: Remove warnings
2024-05-24 18:41:19 -07:00
Ryan Houdek
d3ab9bdef6
Remove Float16
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We aren't using it. We won't be using it. We need unit tests in our
lives if we want this.
2024-05-16 12:06:54 -07:00
Ryan Houdek
9e1840e974
FEXCore: Moves CodeEmitter to FHU
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Now that the vixl dependency is gone, this gets moved to FHU since the
frontend is going to need it for a microjit.
2024-05-13 12:48:10 -07:00
Lioncache