Commit Graph
712 Commits
Author SHA1 Message Date
Ryan Houdek 93ec676ce8 Merge pull request #3340 from Sonicadvance1/exitfunctionlink_data
FEXCore: Describe exit function linking object with a structure
2023-12-19 16:17:21 -08:00
Mai 3d2cbc5d08 Merge pull request #3317 from Sonicadvance1/fix_imul_flags2
OpcodeDispatcher: Fixes flags generation in imul
2023-12-19 11:43:21 -05:00
Mai 81c85d73b2 Merge pull request #3330 from Sonicadvance1/optimize_sib_addr_calc
OpcodeDispatcher: Optimize SIB addr calculation
2023-12-19 11:41:42 -05:00
Mai 5b4e9c6907 Merge pull request #3323 from Sonicadvance1/remove_unused_check
Dispatcher: Removes unused asserting CompileBlock function
2023-12-19 11:38:57 -05:00
Ryan Houdek cf86ae6b65 FEXCore: Describe exit function linking object with a structure
Instead of just poking raw uint64_t data values, describe it with a
struct.

This will be a read-only in the future.
2023-12-18 13:31:53 -08:00
Ryan Houdek 86654907bf Merge pull request #3334 from Sonicadvance1/remove_old_x86jit_references
FEXCore: Removes stale references to x86 JIT
2023-12-18 04:15:29 -08:00
Ryan Houdek 12b72f908b Merge pull request #3335 from Sonicadvance1/remove_internalthreadstate_header
FEXCore: Removes old InternalThreadState header
2023-12-18 04:14:57 -08:00
Ryan Houdek 6c8a54ff84 FEXCore: Removes old InternalThreadState header
This was a temporary header to help with when this header was migrated
to our public API headers.

It's temporary nature is no longer necessary, just get rid of it.
2023-12-15 18:51:25 -08:00
Ryan Houdek bcc2901d7f FEXCore: Removes stale references to x86 JIT
It doesn't exist anymore.
2023-12-15 18:46:57 -08:00
Ryan Houdek 358bbb51ff CPUID: Removes Init and just uses constructor
No need to wait for initialization on for this anymore.
Ever since Init was refactored to do basically no work, this hasn't been
necessary.

CPUID does need to still be initialized after HostFeatures though, so
need to ensure correct member ordering there.
2023-12-15 18:43:23 -08:00
Ryan Houdek 1a2f41922c OpcodeDispatcher: Optimize SIB addr calculation
When the address calculation for SIB has both index and base then we can
optimize this to an add with a shifted register. This will convert a
three instruction sequence in to one instruction in most cases.
2023-12-15 13:08:46 -08:00
Ryan Houdek 0ede707e0b IR: Adds support for AddShift IR op
This matches x86 SIB's operation of `scale * index + base`
2023-12-15 13:08:06 -08:00
Ryan Houdek 12923ba1b7 Merge pull request #3322 from Sonicadvance1/remove_unused_exithandler
PassManager: Removes unused exit handler
2023-12-14 01:55:06 -08:00
Ryan Houdek e657a27607 Dispatcher: Removes unused asserting CompileBlock function
While we were calling this function, its asserting nature hasn't been
used for a long time.

This used to trigger more frequently when CompileBlock would fail to
compile code, either due to not being able to decode an instruction or
hitting an instruction that FEX doesn't understand.

When these cases are hit today we still generate code blocks which
generate SIGILL. This means that this code was actually never hit.

Completely remove this function and have the JIT's dispatcher call the
CompileBlock function directly. Signature is slightly different since we
need to set x3 to be 0.
2023-12-11 17:20:51 -08:00
Ryan Houdek 8bb5462554 PassManager: Removes unused exit handler
git blame shows that 718b3e6b4c added this
handler.

It doesn't explain why this was desired but it was never wired up to
anything. Just remove it.
2023-12-11 17:14:41 -08:00
Ryan Houdek 98f21a2a28 X86Tables: Converts tables to be mostly consteval
Reduces the ELF's VM size from 9.8MB down to 9.37MB and should reduce
initialization time a smidge.

Slammed this out while waiting for other PRs to get reviewed.
2023-12-11 10:03:52 -08:00
Ryan Houdek 5660065eea FEXCore: Moves OS thread creation to the frontend
Fairly lightweight since it is almost 1:1 transplanting the code from
FEXCore in to the SyscallHandler's thread creation code.

Minor changes:
- ExecutionThreadHandler gets freed before executing the thread
   - Saves 16-bytes of memory per thread
- Start all threads paused by default
   - Since I moved the code to the frontend, I noticed we needed to do
     some post thread-creation setup.
   - Without the pause we were racing code execution with TLS setup and
     a few other things.
2023-12-11 06:22:50 -08:00
Ryan Houdek 7524029a06 Merge pull request #3294 from Sonicadvance1/mov_xid_check
FEXCore: Moves XID check to the frontend
2023-12-07 01:17:45 -08:00
Ryan Houdek 5c6f229e76 OpcodeDispatcher: Fixes flags generation imul
On overflow with 32-bit we weren't setting the flags correctly.
2023-12-07 01:08:02 -08:00
Ryan Houdek acdb4c7061 IR: Adds support for {S,U}Mull
Lets us do a 32-bit multiply returning a 64-bit result, signed and
unsigned.
2023-12-07 01:06:58 -08:00
Alyssa Rosenzweig 0fe5e3d1e7 Merge pull request #3313 from alyssarosenzweig/opt/andn-mask
rm andn masking
2023-12-06 12:21:24 -04:00
Ryan Houdek 60b0852cde Merge pull request #3309 from neobrain/fix_thunks_32bit_addresses
Thunks: Add workarounds for pointers not readable by 32-bit guests
2023-12-05 23:52:59 -08:00
Alyssa Rosenzweig 2a2c389be6 OpcodeDispatcher: rm masking in 32-bit andn
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-12-05 09:04:32 -04:00
Tony Wasserka 9f721e96db Thunks: Work around argument data on the host stack not being accessible by 32-bit guests 2023-12-05 11:32:09 +01:00
Tony Wasserka 3729b02255 Arm64/BranchOps: Fix unused-variable warning 2023-12-04 11:32:09 +01:00
Ryan Houdek 3b0aff5fb9 IR: Moves remaining NZCV operations to use DestSize
Just like in #3305 but wasn't causing any known issues
2023-12-02 15:40:51 -08:00
Ryan Houdek c6497fe32b JIT: Fixes crash in TestNZ
In some situations TestNZ is generated with a constant that is using a
constant that can't fit inside of the tst instruction.

This was found in libGLX with virgl, crashing invalid instruction
generation and crashing steamwebhelper
2023-12-02 14:57:57 -08:00
Ryan Houdek c8ef77c15f Merge pull request #3297 from Sonicadvance1/remove_getprogramstatus
FEXCore: Removes GetProgramStatus
2023-11-30 16:29:37 -08:00
Ryan Houdek b35fadf7e3 Merge pull request #3298 from Sonicadvance1/remove_initializecontext
FEXCore: Removes InitializeContext API
2023-11-30 16:29:30 -08:00
Ryan Houdek 250ffb6d23 Merge pull request #3299 from alyssarosenzweig/opt/bt
Optimize BT/BTC/BTS/BTR
2023-11-30 10:50:29 -08:00
Alyssa Rosenzweig f6b1434d63 Merge pull request #3304 from Sonicadvance1/fix_corruption
Dispatcher: Fixes corruption when spilling SRA registers
2023-11-30 08:51:56 -04:00
Ryan Houdek 6bbae69c75 Dispatcher: Fixes corruption when spilling SRA registers
These functions only want the GPRs returned for SRA. This is because the
signal handler needs this map to relation between x86 GPRs and AArch64
GPRs.

When we added AF and PF to the SRA array we accidentally started
returning two more GPRs to the frontend. This caused the signal
delegator to start corrupting the members after GPRs in FEX's CoreState.

Corrupting 16-bytes after the gregs[] array.
This included corrupting:
   - es_idx, cs_idx, ss_idx, ds_idx, gs_idx, fs_idx, _pad[]
2023-11-29 16:17:17 -08:00
Alyssa Rosenzweig d0f54bcb23 Merge pull request #3278 from Sonicadvance1/fix_oversights
FEXCore: Fixes passing arguments to ABI helpers
2023-11-29 17:17:39 -04:00
Alyssa Rosenzweig e923e83efb OpcodeDispatcher: fix nzcvdirty
lets us use flagm in cmpxchg.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 14:35:25 -04:00
Alyssa Rosenzweig 9417c93110 OpcodeDispatcher: remove outdated comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 14:23:41 -04:00
Alyssa Rosenzweig 068599b1ec OpcodeDispatcher: use size-appropriate alu in bt*
saves zero-extending move for 32-bit ops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 14:22:21 -04:00
Alyssa Rosenzweig 7216415bfc OpcodeDispatcher: reorder flag calcs in bt*
saves big moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 14:22:21 -04:00
Alyssa Rosenzweig 3020626506 OpcodeDispatcher: unify bt/btc/bts/btr impls
they're all copypastes of each other, unify into one general "bit test & perform
action" template. this means most of the wins from the previous commits now
apply for bt* without more copypaste.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 14:22:21 -04:00
Alyssa Rosenzweig 0a79fa8d5d OpcodeDispatcher: remove masking for 32/64-bit bt
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 13:40:18 -04:00
Alyssa Rosenzweig f8380b9adb OpcodeDispatcher: use smaller shifts for BT
if the shift is < N, and we grab bit 0 after, we only need to consider <=N
bits of the source. this lets us use 32-bit lsr for 32-bit bt, which will
reduce masking in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 13:40:18 -04:00
Alyssa Rosenzweig d898028bc3 OpcodeDispatcher: optimize BT with constant
use the rmif properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 13:35:23 -04:00
Ryan Houdek f090700184 FEXCore: Removes InitializeContext API
This isn't necessary anymore, just initialize everything on context
creation immediately. All use cases just called this immediately
afterwards.
2023-11-29 09:33:32 -08:00
Ryan Houdek 01d29dffb9 FEXCore: Removes GetProgramStatus
Split from #3284 without changing ownership semantics while I reduce the
debugging surface here.

Removes one usage of ParentThread from FEXCore. Which can be done since
it is no longer an opaque structure, we can read the StatusCode
directly.

No functional change.
2023-11-29 09:23:47 -08:00
Alyssa Rosenzweig 14ba64a22d OpcodeDispatcher: use rmif masking for bt
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 13:20:22 -04:00
Alyssa Rosenzweig 6716077cb6 OpcodeDispatcher: don't mask bt source
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-29 13:16:55 -04:00
Ryan Houdek 1b41304fc1 IRDumper: Fixes missing conditional name
When COND_AL was added it wasn't added to this helper. Since there is a
gap between the last condition, just early check the value.

Fixes reading beyond the end of the array
2023-11-29 08:39:35 -08:00
Ryan Houdek afebf73e8f FEXCore: Moves XID check to the frontend
The XID signal handler is OS specific and needs to be delegated to being
handled in the frontend. This only happens when we create a thread with
pthread rather than clone/fork/vfork.

The first created pthread will reset the XID signal handler in glibc,
which we need to check the first time this occurs. A little bit disjoint
while the actual thread creation still happens in the backend but will
come together once the thread creation gets moved to the frontend.

The only game I am aware of that requires this to work is SOMA since its
one of its middleware libraries tries asking for root privileges.

Retested the game to make sure it still works as expected.
2023-11-28 19:19:06 -08:00
Ryan Houdek 7de66ac3a4 Merge pull request #3286 from Sonicadvance1/remove_getcpustate
FEXCore: Removes Get/SetCPUState
2023-11-28 18:54:29 -08:00
Alyssa Rosenzweig 85a1c1ff25 Merge pull request #3281 from Sonicadvance1/optimize_constantdirection_memsetcpy
FEXCore: Optimize memcpy and memset when direction is compile time constant
2023-11-28 19:11:27 -04:00
Ryan Houdek 3f02d7c665 Merge pull request #3289 from Sonicadvance1/move_debug_names
FEXCore: Moves debug strings to gdbserver
2023-11-28 11:04:15 -08:00