Previously we never checked for SS_DISABLE.
We were also only ever checking for ss_sp being a valid memory range
when we should have been checking for the absense of SS_DISABLE.
Fixes#326
Instead of saying we support the world, actually go through each
individual flag and say that we support the correct things.
Puts FEX plus the git hash in to the model name for now.
Once we have a tagged release in the future we can change this to have
its version tag inside of it.
If the host CPU supports RCPC instructions then it'll use those
instruction of atomics for LoadMemTSO ops.
This pushed my worst case FTL test from 16FPS to 17FPS .
There is another extension to RCPC to add short immediate offset support
which the c630 doesn't support any way. For future optimization on
hardware we can use that.
Ensures the top of the loop is 16byte aligned to give Cortex's
prefetcher the best chance of loading the code.
If the address size is a power of two (We always do 64GB or 32GB VM atm)
then do the address size masking in one instruction instead of loading a
64bit constant first
Move some accessed constants to a literal pool at the end of the ASM
dispatcher.
Was accidently setting the buffer size then unmapping at that new size.
Make sure to unmap then resize.
Also cleans up which buffer is actually being touched here, only the
initial buffer ever changes here.
This requires implementing custom ASM dispatchers for the interpreter
side of things so it works correctly.
Allows all of our CPU backends to safely support signaling.
This is a bit of a nightmare change and requires rethinking logic about
debugging in some instances.
There are a significant number of changes here that I don't really
expect much review on.
Adds a bunch of new features and allows us to support GDB, IDA, and
Binja through their remote GDB debugging facilities.
Ghidra may also work but I haven't tried.
This work isn't quite yet complete to do correct thread stepping yet. We
need to add support for stopping threads using signals since threads may
be stuck inside of a syscall.
I have a hack locally that tries pausing all threads and times out after
a few seconds which works well enough for local testing.
Add and substract were the main culprits here.
We are trying to more towards a state where:
* Every IR op can expect it isn't given extra bits
on it's input
* Every IR op never sets more bits than it's size
* All unnessicary BFEs are never emitted
* ARM doesn't have to implement special 8 and 16bit versions of IR ops
All masking required to implement 8/16bit math on
arm should be explictly generated from Opcode decoder
Any time a guest signal is blocked, add it to the guest signal mask.
This doesn't use a signal queue so repeat signals can end up being lost.
This is expected behaviour
This doesn't help with implementing the problem of unblocking signals
causing the masked signal to be resent
Bunch of templated instructions that didn't need to be templated.
Removes a bunch of duplicate entries.
Saves a couple hundred kilobytes on the final file
When RA made the source address register be the same register as the
destination register then we could have overwritten the address with the
move.
Use a temporary until we get RA constraints in place.
For loadstores to memory, this will use TSO ops to emulate x86
behaviour.
In the case that the source register is the stack pointer then it falls
back down to using regular loadstores. Since it is expected that stack
pointer usage will be thread specific.
With the AArch64 implementation this makes us be quite a bit closer to
being x86 TSO compliant
This patches unaligned LORegion loadstores with DMB wrapped loadstores.
This will ensure full cacheline consistency on loadstores, at the
expense of speed.
The performance can potentially be improved with "Half-barriers"
Described a bit here: https://github.com/dotnet/runtime/issues/8072
We can worry about that path after the initial implementation
This is the base implementation that uses LORegion loadstore
instructions to support the load/store release semantics, which these
instructions use.
Sadly these don't match the alignment requirements of x86 loadstores, so
if it was just used everywhere then it will cause alignment faults.
This means we need to catch the sigbus and backpatch the instruction to
do safe (aka expensive) TSO.
Currently this backpatch just falls back to regular loadstores
surrounded by DMB instructions.
Basically unaligned loadstores will fall back to nearly what we are
doing now, so significantly improved but not perfect.
A follow up PR will change this over to using a helper routine to be
100% safe
Ryan Houdek