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Code Issues Packages Projects Releases 67 Wiki Activity
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4c27dfd5eb0ee2fe58a57a21ddb6cbe128b3b46a
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2656 Commits
Author SHA1 Message Date
LC 4c27dfd5eb VectorOps: Avoid temporary if able in 256-bit VFRecp 
If we're non-aliasing, we can make use of the destination reg directly.
Makes the non-RPRES path a little nicer.
 2026-06-30 04:36:20 -04:00
LC 201216ba54 HostFeatures: Put SVE support querying into single function 
Lets us avoid open-coding long checks for the existence of either
SVE-128 or SVE-256.
 2026-06-30 03:34:17 -04:00
Ryan Houdek 16f90b33f3 Merge pull request #5641 from lioncash/minmax 
VectorOps: Reduce temporary usage in 64-bit AdvSIMD min max paths
 2026-07-01 14:17:18 -07:00
LC d3a85e14d9 VectorOps: Reduce temporary usage in 64-bit AdvSIMD min max paths 
We can reorganize these such that they only use one temporary in the
worst case instead of two.
 2026-06-30 01:30:40 -04:00
LC 3d289f4489 VectorOps: Avoid move in 256-bit VAddP/VFAddP if possible 
If the first source and destination alias, then it's fine to use the
register in destructive operations, since the source data doesn't need
to be preserved.

Tiny saving, but reduces overall register use in some cases.
 2026-06-30 00:23:30 -04:00
LC c6b0f360fe AVX: Make use of table swapping constant to trim down relevant ops 
Now we can get rid of excessive overhead, with the ability to improve
this further in the future.
 2026-06-29 12:51:30 -04:00
LC ef19242be3 IR: Add constant for swapping midsections of 256-bit vectors around 
This'll let us eliminate some pretty gnarly inserts while
ZIP1Q/UZP1Q/etc are still unavailable.
 2026-06-29 12:50:53 -04:00
Paulo Matos 37b010795e Re-optimize FYL2X for reduced precision x87 path 2026-06-30 15:00:16 -07:00
LC 2cb4f8b6f5 AVX: Remove unnecessary moves from VPSHUF{D, HW, LW} 
These aren't necessary anymore, since these use operations
that already zero extend.
 2026-06-29 08:43:11 -04:00
LC 600e2ddecf Vector: Only signify 128-bit vector loads in UCOMISxOp 
Mainly a correctness change more than anything. The COMISX and
UCOMISX group of operations only ever load 128 bits when given
a vector source.

No change in codegen, but ensures this doesn't change if any backing
handling changes.
 2026-06-28 15:40:14 -04:00
LC 2ec2c39cf1 AVX: Lessen codegen for VMOVMSKPD 
Performs the same thing as what we've done for VMOVMSKPS. Though,
the effect isn't as drastic, given we're only operating on a max
of four elements as opposed to 8.
 2026-06-28 14:06:32 -04:00
LC 41fc57f46c AVX: Lessen codegen for 256-bit VMOVMSKPS 
Currently we can trivially split this up and join the results, which
is much nicer than iterating all the elements individually and shifting
their sign bit over.
 2026-06-28 13:52:19 -04:00
Ryan Houdek 9f2e982944 Merge pull request #5617 from simon902/vcvtps2ph 
OpcodeDispatcher: Fix missing zeroing for vcvtps2ph
 2026-06-29 10:40:45 -07:00
LC 3e60aa5738 Merge pull request #5610 from Sonicadvance1/171 
FEXCore: Pass host type that changes codegen to FEXCore
 2026-06-29 02:04:31 -04:00
Simon Scherer 4564325bc7 OpcodeDispatcher: Fix upper 128 bit zeroing for vcvtps2ph 2026-06-28 13:17:06 +02:00
LC a5ecb71993 AVX: Handle two field insertions in VPERMQ 
Lets us trivially handle fields like 0baa'aa'bb'bb
as broadcasts and an insert.
 2026-06-27 19:35:53 -04:00
LC 6d86dca20b AVX: Slightly trim codegen for VPSADW 256-bit case 
We can massage this a little bit to be slightly better. At least
gets rid of the heavyweight inserts.
 2026-06-27 14:16:48 -04:00
Ryan Houdek c85e426cc5 Merge pull request #5622 from lioncash/perm 
AVX: Handle trivial UZP/ZIP operations in VPERMQ
 2026-06-28 11:01:49 -07:00
Ryan Houdek b23fa30099 Merge pull request #5618 from wsxarcher/fixsmcfullvector 
Core: Start a new block for the next op in full SMC check
 2026-06-28 09:25:23 -07:00
wsxarcher b21c49352e Core: Start a new block for the next op in full SMC check 2026-06-28 18:07:28 +02:00
LC e24f84504f AVX: Handle trivial UZP/ZIP operations in VPERMQ 
Handles cases where a permutation can be simplified into a single
zip/unzip operation.
 2026-06-27 12:04:13 -04:00
LC ee2fb57f4e AVX: Handle full broadcast in VDPPS 
Another trivial case that can be handled without crazy codegen.
 2026-06-27 10:11:27 -04:00
LC 11fe95d8ea AVX: Simplify trivial case of VDPPS 
Just a silly case where we only need to return the zero vector
 2026-06-27 09:55:35 -04:00
Ryan Houdek c0251dc8be FEXCore: Pass host type that changes codegen to FEXCore 
Because these compile options change codegen, we need to make sure these
are runtime selected rather than compile-time selected. Will reduce
code-cache variance.
 2026-06-26 12:06:30 -07:00
LC d555ee8bcc Vector: Fix typo in VPERMQOp 
Noticed this in my own writing and it bothered me.
 2026-06-26 14:16:54 -04:00
Ryan Houdek 64392b2d45 OpcodeDispatcher: Fixes CRC32 with high 8-bit register 
Assertion failure in `_Bfe` IR operation when encountering this
instruction. Ensure the GPR source is sized appropriately.
 2026-06-26 11:34:45 -07:00
LC 8102a0974a AVX: Handle easily broadcastable permutations in VPERMQ 
When we have a 3 element identical permutation followed by a single
unique outlier, we can simplify the whole operation into a single
broadcast followed by an insert.

e.g.

0b00'00'00'01
0b00'01'01'01
0b11'11'00'11

are all examples of cases where we can broadcast and then insert.
 2026-06-25 21:48:56 -04:00
Ryan Houdek d5be15c90e Merge pull request #5605 from lioncash/permq 
AVX: Skip identity insertions in VPERMQ
 2026-06-25 11:51:25 -07:00
LC e91efc6694 AVX: Skip identity insertions in VPERMQ 
In the slower case, if our iteration index and the selector index match,
then all that means is that we'd be inserting the same data that already exists
at that location, so we can skip the insertion in that case.
 2026-06-25 14:33:49 -04:00
LC a2889a09e3 Vector: Move zero constant closer to use in PCMPXSTRXOpImpl 
Same behavior, but constrains the only scope it's used in.
 2026-06-23 09:35:41 -04:00
LC cf098a0de6 AVX: Handle transpose cases in VPERMQ 
These can be single instruction operations.
 2026-06-23 00:39:42 -04:00
Ryan Houdek d93997c1cb Merge pull request #5602 from lioncash/same 
AVX: Remove unnecessary dup if sources are the same in SHUFOpImpl
 2026-06-24 23:38:29 -07:00
Ryan Houdek e19aa975c8 Merge pull request #5597 from simon902/BTOpTypo 
OpcodeDispatcher: Fix incorrect comment for BTOp. ZF must be preserved.
 2026-06-24 23:31:09 -07:00
Simon Scherer 3f02dd0a36 OpcodeDispatcher: Update BTOp comment to clarify AMD vs Intel flag behavior 2026-06-25 07:36:32 +02:00
Ryan Houdek ab4e0f653a Merge pull request #5600 from lioncash/palign 
AVX: Shave some moves off 256-bit VPALIGNR
 2026-06-24 11:18:51 -07:00
Ryan Houdek fda023e7dc Merge pull request #5601 from lioncash/pshufb 
AVX: Reduce moves in 256-bit VPSHUFB
 2026-06-24 10:44:07 -07:00
Simon Scherer e03187852b OpcodeDispatcher: Fix incorrect comment for BTOp. ZF must be preserved. 2026-06-24 16:11:13 +02:00
LC 20647f2287 AVX: Remove unnecessary dup if sources are the same in SHUFOpImpl 
Eliminates a trivial move.
 2026-06-22 22:15:34 -04:00
LC a2e4209f4f AVX: Reduce moves in 256-bit VPSHUFB 
Just a minor reduction by avoiding insertion overhead.
 2026-06-22 10:47:49 -04:00
LC 73d6716828 AVX: Shave some moves off 256-bit VPALIGNR 
Arbitrary insertion of an element requires the use of a predicate
register. Since we only care about a particular element in the vector,
being replicated, we can broadcast that element instead of doing an
insert, which is effectively the same thing without excessive busywork.
 2026-06-22 10:09:13 -04:00
LC 1fb2419be2 Vector: Remove unused OpcodeArgs parameter from SHUFOpImpl 
No behavior change, just a reduction in noise.
 2026-06-22 09:47:46 -04:00
LC 3394808c06 AVX: Wire up helper to VPERMILPD 
We can just leverage the shuffle handler for this, since VPSHUFD
essentially functions like VPERMILPD
 2026-06-22 09:03:22 -04:00
LC c252b58a15 AVX: Wire up lane helper for VPERMILPS imm variant 
Makes for some more trivial savings. Will need handling for VPERMILPD
added separately, since selector behavior is different.
 2026-06-22 05:21:10 -04:00
LC 39ae8c3ea0 AVX: Wire up lane helper for VSHUFPD/VSHUFPS 
Also allows collapsing quite a bit of emitted code, like with
the shuffles in #5594
 2026-06-22 04:46:22 -04:00
LC eb8c2d964c Vector: Factor out 128-bit path in SHUFOpImpl 
We can leverage this for the 256-bit path
 2026-06-22 03:47:20 -04:00
LC bd9cf9ca11 AVX: Wire up lane helper for VPSHUFD/VPSHUFLW/VPSHUFHW 
Lets the AVX implementation get all the optimizations that the SSE
variant has, reducing the overhead a little.

Even with the individual lane handling, this is still leagues better
than all of the individual inserts that are pretty beefy with SVE.

For example:

vpshufd ymm0, ymm1, 0b00000011

drops from 50 instructions to 9
 2026-06-22 00:16:39 -04:00
Ryan Houdek 27a5f09185 Merge pull request #5592 from ShadowCurse/fixes 
JIT: Arm64: fix the loop in CacheLineClear/Clean
 2026-06-23 17:15:07 -07:00
Ryan Houdek 01b0b4e653 Merge pull request #5593 from lioncash/dup 
VectorOps: Avoid dup if able in VInsElement 128-bit element path
 2026-06-23 17:10:35 -07:00
Egor Lazarchuk e3e9777ee6 JIT: Arm64: fix the loop in CacheLineClear/Clean 
These functions need to clean at least 64 bytes of cache since this is
the default on x86_64, but previously they could clean less if
DCacheLineSize was smaller than 64 bytes.
 2026-06-24 00:38:48 +01:00
LC d78963c021 VectorOps: Avoid dup if able in VInsElement 128-bit element path 
We don't need to broadcast if we're inserting across registers into the
equivalent position, since we already have a predicate around that can
satisfy that.
 2026-06-21 20:32:37 -04:00