Stefanos Kornilios Mitsis Poiitidis
ab44f800f7
AOTgen: Cleaner interfaces, use LogMan
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
1a5bc39d09
Rebase fixes
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
244ef94e9b
AOTIR: Generate list of files with code, add Scripts/FEXUpdateAOTIRCache.sh to generate all files
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
a85ef061d1
AOITR: Add AOTIRGenerate fo FEXLoader option that does generation
2021-05-01 09:40:50 +03:00
Stefanos Kornilios Mitsis Poiitidis
4e847d03b7
Remove more assertions for invalid code
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
ce9324f50f
Kinda-parse unwind table
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
0897fc4a0a
pretrans wip
2021-05-01 09:40:49 +03:00
Stefanos Kornilios Mitsis Poiitidis
8a73783a07
AOTIR: Use FEXCore::Allocator
2021-04-29 08:16:21 +03:00
Stefanos Kornilios Mitsis Poiitidis
32b4b02302
AOTIR: mmap based loading
2021-04-28 13:08:43 +03:00
Ryan Houdek
6255eba524
Memory layout optimizations
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Some of these memory layouts weren't optimal for ARM loading.
This is now significantly improved
2021-04-26 23:48:22 -07:00
Ryan Houdek
04e0baadc6
Changes LogMan assert to defines
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C++ no-op functions can't optimize out the predicate arguments in all cases.
This was causing a problem where zero cost assertions weren't actually zero cost.
The only way to resolve this is to actually use macros sadly enough.
This will give a fairly hefty performance uplift with anything operating on IR.
2021-04-26 13:49:35 -07:00
Ryan Houdek
7d4380fe6d
Merge pull request #984 from FEX-Emu/skmp/relocation-fixes
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IR: Fix RIP relocation edge-cases
2021-04-26 10:11:24 -07:00
Ryan Houdek
7d5157b602
Merge pull request #983 from FEX-Emu/skmp/faster-l1
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LookupCache: Add new entries to L1C
2021-04-26 10:10:51 -07:00
Stefanos Kornilios Mitsis Poiitidis
b3564a4a48
IR: Fix RIP relocation edge-cases
2021-04-26 19:20:01 +03:00
Stefanos Kornilios Mitsis Poiitidis
df8b78b327
Dispatcher: Use Also lookup L1C when dispatching interpreter
2021-04-26 19:06:11 +03:00
Stefanos Kornilios Mitsis Poiitidis
2ea6a2a141
LookupCache: Fix L1C to actually cache entries
2021-04-26 18:38:03 +03:00
Stefanos Kornilios Mitsis Poiitidis
b45b7c3441
IR: Remove Entry from OP_HEADER, pass as parameter to CompileCode
2021-04-25 13:15:23 +03:00
Stefanos Kornilios Mitsis Poiitidis
7805552edb
LookupCache: Add new entries to L1C
2021-04-25 13:03:43 +03:00
Stefanos Kornilios Mitsis Poiitidis
60671ee6cb
Merge pull request #975 from Sonicadvance1/use_xxhash
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Switch from fasthash64 to xxhash's XXH3
2021-04-23 09:49:06 +03:00
Ryan Houdek
0b0db08ebf
Switch from fasthash64 to xxhash's XXH3
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Fixes #797
2021-04-18 18:13:27 -07:00
Ryan Houdek
967ac863be
Replaces naked mman usage in X86Dispatcher
2021-04-16 20:50:14 -07:00
Ryan Houdek
99ab9864aa
Replaces naked mman usage in X86HelperGen
2021-04-16 20:50:03 -07:00
Ryan Houdek
11246355e2
Replaces naked mman usage in LookupCache
2021-04-16 20:49:58 -07:00
Ryan Houdek
0d236940e0
Replaces naked mman usage in x86-64 JIT
2021-04-16 20:49:52 -07:00
Ryan Houdek
a0afb4be5a
Replaces naked mman usage in Arm64 JIT
2021-04-16 20:49:47 -07:00
Stefanos Kornilios Mitsis Poiitidis
22f1cf0e2a
More wip
2021-04-15 10:05:59 +03:00
Stefanos Kornilios Mitsis Poiitidis
80493487db
ELF Loading: Cleanups all around
2021-04-14 10:59:23 +03:00
Stefanos Kornilios Mitsis Poiitidis
59ce750af6
Elf: Add ELFCodeLoader2, with simplified loading logic
2021-04-13 15:59:36 +03:00
Ryan Houdek
66c8dd2013
First step in paranoid TSO mode
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This moves vector ops down the GPR atomic backpatch path.
Next step after this is to add SIGBUS based handlers for these rather than backpatching.
Needs more work to treat aligned versus unaligned vector loadstores differently
2021-04-06 18:48:36 -07:00
Ryan Houdek
91ac4ccdd8
Adds LDAXP and STLXP backpatch handlers
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This will be used in the next commit
2021-04-06 18:47:50 -07:00
Stefanos Kornilios Mitsis Poiitidis
50c3ee047c
Merge pull request #961 from Sonicadvance1/fix_segment_override
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Fixes segment register override on string instructions.
2021-04-06 09:24:23 +03:00
Stefanos Kornilios Mitsis Poiitidis
c0ef6da6a8
Merge pull request #960 from Sonicadvance1/more_cpuid
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Adds some more CPUID functions
2021-04-06 09:23:13 +03:00
Stefanos Kornilios Mitsis Poiitidis
4a5eefec25
Merge pull request #958 from Sonicadvance1/fix_atomic_zext
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Fixes Zext semantics on atomic ops with x64 JIT
2021-04-06 09:21:44 +03:00
Stefanos Kornilios Mitsis Poiitidis
c26f19ed4d
Merge pull request #950 from Sonicadvance1/fix_gcc_tests
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Fixes GCC tests
2021-04-06 09:05:45 +03:00
Stefanos Kornilios Mitsis Poiitidis
9619cea097
Merge pull request #949 from Sonicadvance1/arm64_print
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Adds support for Arm64 JIT to Print
2021-04-06 08:58:13 +03:00
Stefanos Kornilios Mitsis Poiitidis
44dbecc2ac
Merge pull request #948 from Sonicadvance1/fix_leak
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Fixes memory leak in CPU backends
2021-04-06 08:56:00 +03:00
Ryan Houdek
b7e81e867d
Fixes segment register override on string instructions.
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The segment prefix only overrides one side of the string instruction.
Passing in the flags was causing the instruction to have the segment override on both sides of the copy.
So something like `movsb es:[rdi], fs:[rsi]` was being interpreted as `movsb fs:[rdi], fs:[rsi]`
Same for all the string ops which is now fixed.
We can't unit test these currently since we can't set host segment register for confirmed host behaviour.
2021-04-05 21:28:31 -07:00
Ryan Houdek
4f276aae82
Adds comment for LEA and segment registers
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LEA doesn't give you the result with segment register applied to it.
Adds a comment to OpDispatcher to make it more clear
2021-04-05 21:28:25 -07:00
Ryan Houdek
c80254f6f4
Adds some more CPUID functions
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Noticed a game poking at these
2021-04-05 18:37:05 -07:00
Ryan Houdek
0dd1959d65
Fixes Zext semantics on atomic ops with x64 JIT
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Fixes Factorio 1.1.30 on x86-64 hosts
Fixes #957
2021-04-05 18:19:15 -07:00
Ryan Houdek
f8eabb4f33
Implements 64bit scalar VUMin on x86 JIT
2021-04-04 22:05:55 -07:00
Ryan Houdek
4da492d361
Fixes vector integer min and max on AArch64
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These instructions don't have a 64bit element variant.
Switch the 64bit element variant over to a coded variant similar to float min/max
2021-04-04 22:05:55 -07:00
Ryan Houdek
a200d2c91c
Fixes packed shift ops
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In the case of a shift value larger than the element size then the shift will zero the element.
Incoming shift amount is always a 64bit value which means that the value can become quite large on shifts.
Checks the incoming source and sets the maximum to be the element size, which works for AArch64's vector shifts
Which only operate on 8bit incoming shift amounts
2021-04-04 22:05:55 -07:00
Ryan Houdek
af205e9f5f
Fixes PEXTRW
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In the case of 16bit PEXTRW it will zext to 32bits which wasn't being done
2021-04-04 21:32:12 -07:00
Ryan Houdek
032d1fbba2
Fixes VFMIN/VFMax NaN behaviour
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In a world with NaNs we were hitting some undefined behaviour with fmin/fmax
Needed to change these over to something more complex to handle the NaN case.
ARMv8.7 alternative FP mode would solve this for the scalar case, but it still doesn't work for the vecto case sadly.
2021-04-04 21:29:46 -07:00
Ryan Houdek
313c4bb784
Fixes bug in VectorImm
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If passing in a 64bit immediate then movi doesn't behaviour how you would expect.
Instead to a tmp move + dup to implement it the way we want
2021-04-04 20:24:23 -07:00
Ryan Houdek
ceb484fd3a
Adds support for Arm64 JIT to Print
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Useful for debugging, supports both vector and GPR
2021-04-04 20:22:44 -07:00
Ryan Houdek
b98c7bd853
Moves AArch64's GetPhys to be a class function
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No need for it to be static
2021-04-04 20:21:06 -07:00
Ryan Houdek
4c045148b6
Fixes memory leak in CPU backends
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Dispatcher wasn't ever getting cleaned up.
Also ensures sharing it with the CompileService otherwise it crashes on use.
2021-04-04 20:19:35 -07:00
Ryan Houdek
9f29bba4aa
Fixes missing virtual destructor on Dispatcher class
2021-04-04 20:10:58 -07:00
