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Code Issues Packages Projects Releases 67 Wiki Activity
1,989 Commits 11 Branches 71 Tags
2e5f59cdc19240df5c9f79845636a585bceb7ee1
Commit Graph
1069 Commits
Author SHA1 Message Date
Scott Mansell 2e5f59cdc1 Merge pull request #734 from Sonicadvance1/remove_warnings_4 
Removes warnings from OpcodeDispatcher
 2021-02-01 16:45:37 +13:00
Scott Mansell 767813eb97 Merge pull request #735 from Sonicadvance1/remove_warnings_5 
Removes warning from X86Tables
 2021-02-01 16:44:24 +13:00
Scott Mansell 9c81fbb2fd Merge pull request #736 from Sonicadvance1/remove_warnings_6 
Removes warning from IRDumper
 2021-02-01 16:42:52 +13:00
Scott Mansell 5f624bec05 Merge pull request #733 from Sonicadvance1/remove_warnings_3 
Removes warnings from x86-64 JIT.cpp
 2021-02-01 16:42:10 +13:00
Scott Mansell a156210064 Merge pull request #738 from Sonicadvance1/remove_warnings_9 
Removes warnings from Register Allocation Pass
 2021-02-01 16:32:05 +13:00
Scott Mansell d4fbca3cbf Merge pull request #732 from Sonicadvance1/remove_warnings_2 
Removes warnings from Frontend
 2021-02-01 16:23:29 +13:00
Ryan Houdek 0c3ddd3016 Removes warnings from Register Allocation Pass 2021-01-31 08:00:28 -08:00
Ryan Houdek a90e2268f9 Removes warning from DeadStoreElimination 2021-01-31 07:59:26 -08:00
Ryan Houdek 175078b739 Removes warning from IRDumper 2021-01-31 07:58:58 -08:00
Ryan Houdek 9e55f1b177 Removes warning from X86Tables 2021-01-31 07:58:08 -08:00
Ryan Houdek 6012fcfee6 Removes warnings from OpcodeDispatcher 2021-01-31 07:57:28 -08:00
Ryan Houdek c2f4ea4646 Removes warnings from x86-64 JIT.cpp 2021-01-31 07:56:19 -08:00
Ryan Houdek 1f6017c37c Removes warnings from Frontend 2021-01-31 07:55:26 -08:00
Stefanos Kornilios Mitsis Poiitidis 1f7d815f3a LookupCache: Fix crash on L2 insertion 2021-01-29 22:00:07 +02:00
Stefanos Kornilios Mitsis Poiitidis 9ecde7a0b8 Interpreter: Move execution to IntepreterOps::ExecuteIR, single core refactor 2021-01-29 15:17:37 +02:00
Stefanos Kornilios Mitsis Poiitidis 972219043d Core: Refactor compilation driver, lifetime of objects 2021-01-29 10:42:55 +02:00
Stefanos Kornilios Mitsis Poiitidis 0e00d3dc15 RA: Optimize RAData 2021-01-29 10:42:48 +02:00
Stefanos Kornilios Mitsis Poiitidis a45c2c34e9 RA: Use RAData directly 2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis 513112919b RA: Move allocation data to RAData 2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis 791aa4c32c LookupCache: Add a third level cache that will always resolve all known blocks 2021-01-29 01:53:12 +02:00
Stefanos Kornilios Mitsis Poiitidis 0c9e05ed8f Rename BlockCache to LookupCache 2021-01-29 01:31:48 +02:00
Stefanos Kornilios Mitsis Poiitidis f872e178ac Merge pull request #718 from Sonicadvance1/32bit_sigret_handler 
Forces SIGRET handler to the lower 32bits VA on 32bit processes
 2021-01-27 20:16:51 +02:00
Stefanos Kornilios Mitsis Poiitidis ec31dc0872 Merge pull request #716 from Sonicadvance1/describe_tag 
Puts the FEX describe tag in CPUID
 2021-01-27 20:10:46 +02:00
Ryan Houdek 2437b89c7b Forces SIGRET handler to the lower 32bits VA on 32bit processes 
This is visible to the guest process so for 32bit it needs to be in the
lower 32bits.
 2021-01-27 07:54:30 -08:00
Ryan Houdek 5673a0e213 Puts the FEX describe tag in CPUID 
This is what shows up in /proc/cpuinfo

example on tagged release:   'model name      : FEX-2101'
example on untagged release: 'model name      : FEX-2101-64-g536be23f'

Fixes #661
 2021-01-27 07:20:14 -08:00
Ryan Houdek 3df344a78d Fixes some asserts from vixl and a bug in ExitSpillSRA 
Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.

Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location
 2021-01-27 00:53:27 -08:00
Ryan Houdek 6bca290611 Implements VBSL on AArch64 
This isn't quite optimal without RA constraints
 2021-01-26 03:01:48 -08:00
Ryan Houdek 513cb27825 Add TSX names to decode tables so we know what they are 
Rather than just stating UND

We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
 2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis b0365871b6 OpDisp: Address most 32-bit rip size issues 2021-01-25 15:04:12 +02:00
Ryan Houdek d4ffea5c31 Merge pull request #670 from FEX-Emu/skmp/faster-ra 
IR: Optimize runtime of optimization passes
 2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis 0546da7a75 Address review feedback 2021-01-22 11:01:36 +02:00
Stefanos Kornilios Mitsis Poiitidis 8b025d4c26 IRLoader: Actually set EntryRIP if the IR was parsed 2021-01-21 22:19:16 +02:00
Stefanos Kornilios Mitsis Poiitidis 3bd8731b26 IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner 2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis 13613c6de1 IR: Change ValidateCode to use two uint64_t instead of __uint128_t 2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis 1177c375ff IR: Further parser cleanups, add fence types 2021-01-21 21:17:27 +02:00
Stefanos Kornilios Mitsis Poiitidis 072067b5fd IR: Split parser from IRLoader, add IR::Parse() 2021-01-21 19:17:51 +02:00
Stefanos Kornilios Mitsis Poiitidis 773e5866b4 Merge pull request #666 from Sonicadvance1/handle_unaligned_caspal32 
Handle unaligned cmpxchg and cmpxchg8b on ARMv8.1+
 2021-01-21 13:30:18 +02:00
Stefanos Kornilios Mitsis Poiitidis 00ca576644 IRCompaction: Only memset in debug 2021-01-21 13:06:43 +02:00
Stefanos Kornilios Mitsis Poiitidis 036771d825 IR: Fix Printing and Parsing for float conds 2021-01-21 10:16:08 +02:00
Ryan Houdek 633ea045e5 Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler 
cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.

Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.

Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.

If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
 2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis 0e7db64ac7 RA: Run compation after spilling, not before 2021-01-21 01:01:02 +02:00
Stefanos Kornilios Mitsis Poiitidis ac1036ac92 IR: Sync Invalid class with RA 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c462eb400 ConsProp: Revert to ordered set for identical codegen 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 8aef9cb6a7 RA: Exit after first spill per iteration is found 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis d3fc85e18d RA: Make spans at least 1 offset long 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9f3ce47917 RA: Expire ending intervals before starting new ones 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis a9332e604a JIT/x64: Fix VAddV 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis e7e6b6654f RA: Cleanups 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis c3682f9a3b RA: Fix several bugs, get rid of virtual registers, remove unused complexity 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 47ee9af96c ConstProp: Keep pools in heap 2021-01-20 04:26:06 +02:00